diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -873,14 +873,18 @@ ManualCodegen = [{ { // builtin: (val0 address, val1 address, ..., ptr, vl) - IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), - Ops[NF + 1]->getType()}; - // intrinsic: (ptr, vl) - llvm::Value *Operands[] = {Ops[NF], Ops[NF + 1]}; + ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType()); + IntrinsicTypes = {ResultType, Ops[NF + 1]->getType()}; + // intrinsic: (passthru0, passthru1, ..., ptr, vl) + SmallVector Operands; + for (unsigned I = 0; I < NF; ++I) + Operands.push_back(llvm::UndefValue::get(ResultType)); + Operands.push_back(Ops[NF]); + Operands.push_back(Ops[NF + 1]); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); clang::CharUnits Align = - CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType()); + CGM.getNaturalPointeeTypeAlignment(E->getArg(NF)->getType()); llvm::Value *V; for (unsigned I = 0; I < NF; ++I) { llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I}); @@ -944,10 +948,14 @@ ManualCodegen = [{ { // builtin: (val0 address, val1 address, ..., ptr, new_vl, vl) - IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), - Ops[NF + 2]->getType()}; - // intrinsic: (ptr, vl) - llvm::Value *Operands[] = {Ops[NF], Ops[NF + 2]}; + ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType()); + IntrinsicTypes = {ResultType, Ops[NF + 2]->getType()}; + // intrinsic: (passthru0, passthru1, ..., ptr, vl) + SmallVector Operands; + for (unsigned I = 0; I < NF; ++I) + Operands.push_back(llvm::UndefValue::get(ResultType)); + Operands.push_back(Ops[NF]); + Operands.push_back(Ops[NF + 2]); Value *NewVL = Ops[NF + 1]; llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); @@ -1019,10 +1027,15 @@ ManualCodegen = [{ { // builtin: (val0 address, val1 address, ..., ptr, stride, vl) - IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), - Ops[NF + 2]->getType()}; - // intrinsic: (ptr, stride, vl) - llvm::Value *Operands[] = {Ops[NF], Ops[NF + 1], Ops[NF + 2]}; + ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType()); + IntrinsicTypes = {ResultType, Ops[NF + 2]->getType()}; + // intrinsic: (passthru0, passthru1, ..., ptr, stride, vl) + SmallVector Operands; + for (unsigned I = 0; I < NF; ++I) + Operands.push_back(llvm::UndefValue::get(ResultType)); + Operands.push_back(Ops[NF]); + Operands.push_back(Ops[NF + 1]); + Operands.push_back(Ops[NF + 2]); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); clang::CharUnits Align = @@ -1086,10 +1099,15 @@ ManualCodegen = [{ { // builtin: (val0 address, val1 address, ..., ptr, index, vl) - IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), - Ops[NF + 1]->getType(), Ops[NF + 2]->getType()}; - // intrinsic: (ptr, index, vl) - llvm::Value *Operands[] = {Ops[NF], Ops[NF + 1], Ops[NF + 2]}; + ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType()); + IntrinsicTypes = {ResultType, Ops[NF + 1]->getType(), Ops[NF + 2]->getType()}; + // intrinsic: (passthru0, passthru1, ..., ptr, index, vl) + SmallVector Operands; + for (unsigned I = 0; I < NF; ++I) + Operands.push_back(llvm::UndefValue::get(ResultType)); + Operands.push_back(Ops[NF]); + Operands.push_back(Ops[NF + 1]); + Operands.push_back(Ops[NF + 2]); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); clang::CharUnits Align = diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -200,7 +200,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -213,7 +213,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -228,7 +228,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -245,7 +245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -264,7 +264,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -285,7 +285,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -308,7 +308,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -333,7 +333,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -346,7 +346,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -361,7 +361,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -378,7 +378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -391,7 +391,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -404,7 +404,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -419,7 +419,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -455,7 +455,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -476,7 +476,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -499,7 +499,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -524,7 +524,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -537,7 +537,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -552,7 +552,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -582,7 +582,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -597,7 +597,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -614,7 +614,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -633,7 +633,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -654,7 +654,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -677,7 +677,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -715,7 +715,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -730,7 +730,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -747,7 +747,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -766,7 +766,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -787,7 +787,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -810,7 +810,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -848,7 +848,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -863,7 +863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -880,7 +880,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -893,7 +893,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -906,7 +906,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -921,7 +921,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -938,7 +938,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -957,7 +957,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -978,7 +978,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1001,7 +1001,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1026,7 +1026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1039,7 +1039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1054,7 +1054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1071,7 +1071,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1084,7 +1084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1097,7 +1097,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1112,7 +1112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1129,7 +1129,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1148,7 +1148,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1169,7 +1169,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1192,7 +1192,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1230,7 +1230,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1245,7 +1245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1262,7 +1262,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1275,7 +1275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1288,7 +1288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1303,7 +1303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1320,7 +1320,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1360,7 +1360,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1383,7 +1383,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1408,7 +1408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1421,7 +1421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1436,7 +1436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1453,7 +1453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1466,7 +1466,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1481,7 +1481,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1498,7 +1498,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1538,7 +1538,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1561,7 +1561,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1586,7 +1586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1599,7 +1599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1614,7 +1614,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1631,7 +1631,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1644,7 +1644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1657,7 +1657,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1672,7 +1672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1689,7 +1689,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1708,7 +1708,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1729,7 +1729,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1752,7 +1752,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1777,7 +1777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1790,7 +1790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1805,7 +1805,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1822,7 +1822,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1835,7 +1835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1848,7 +1848,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1863,7 +1863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1880,7 +1880,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1920,7 +1920,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1943,7 +1943,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1968,7 +1968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1981,7 +1981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1996,7 +1996,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2013,7 +2013,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2026,7 +2026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2039,7 +2039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2054,7 +2054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2071,7 +2071,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2090,7 +2090,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2111,7 +2111,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2134,7 +2134,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2159,7 +2159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2172,7 +2172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2187,7 +2187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2204,7 +2204,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2217,7 +2217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2230,7 +2230,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2262,7 +2262,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2281,7 +2281,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2302,7 +2302,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2325,7 +2325,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2350,7 +2350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2363,7 +2363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2395,7 +2395,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2408,7 +2408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2421,7 +2421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2436,7 +2436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2453,7 +2453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2472,7 +2472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2493,7 +2493,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2516,7 +2516,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2541,7 +2541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2554,7 +2554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2569,7 +2569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2586,7 +2586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2599,7 +2599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2612,7 +2612,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2627,7 +2627,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2663,7 +2663,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2684,7 +2684,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2707,7 +2707,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2732,7 +2732,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2745,7 +2745,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2760,7 +2760,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2790,7 +2790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2803,7 +2803,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2818,7 +2818,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2835,7 +2835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2854,7 +2854,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2875,7 +2875,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2898,7 +2898,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2923,7 +2923,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2936,7 +2936,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2951,7 +2951,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2968,7 +2968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2981,7 +2981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2994,7 +2994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3009,7 +3009,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3026,7 +3026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3045,7 +3045,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3066,7 +3066,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3089,7 +3089,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3114,7 +3114,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3127,7 +3127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3142,7 +3142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3159,7 +3159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3172,7 +3172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3185,7 +3185,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3200,7 +3200,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3217,7 +3217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3236,7 +3236,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3257,7 +3257,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3280,7 +3280,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3305,7 +3305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3318,7 +3318,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3333,7 +3333,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3350,7 +3350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3363,7 +3363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3376,7 +3376,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3391,7 +3391,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3408,7 +3408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3427,7 +3427,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3448,7 +3448,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3471,7 +3471,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3496,7 +3496,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3509,7 +3509,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3524,7 +3524,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3541,7 +3541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3554,7 +3554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3569,7 +3569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3586,7 +3586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3605,7 +3605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3626,7 +3626,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3649,7 +3649,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3674,7 +3674,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3687,7 +3687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3702,7 +3702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3719,7 +3719,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3738,7 +3738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3759,7 +3759,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3782,7 +3782,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3807,7 +3807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3820,7 +3820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3835,7 +3835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3852,7 +3852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3865,7 +3865,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3878,7 +3878,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3893,7 +3893,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3910,7 +3910,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3929,7 +3929,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3950,7 +3950,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3973,7 +3973,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3998,7 +3998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4011,7 +4011,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4026,7 +4026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4043,7 +4043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4056,7 +4056,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4069,7 +4069,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4101,7 +4101,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4120,7 +4120,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4141,7 +4141,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4164,7 +4164,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4189,7 +4189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4202,7 +4202,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4234,7 +4234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4247,7 +4247,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4260,7 +4260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4275,7 +4275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4292,7 +4292,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4311,7 +4311,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4332,7 +4332,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4355,7 +4355,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4380,7 +4380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4393,7 +4393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4408,7 +4408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4425,7 +4425,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4438,7 +4438,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4453,7 +4453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4470,7 +4470,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4489,7 +4489,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4510,7 +4510,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4533,7 +4533,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4558,7 +4558,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4571,7 +4571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4586,7 +4586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4603,7 +4603,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4629,7 +4629,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4644,7 +4644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4661,7 +4661,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4680,7 +4680,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4701,7 +4701,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4724,7 +4724,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4762,7 +4762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4777,7 +4777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4794,7 +4794,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4807,7 +4807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4820,7 +4820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4835,7 +4835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4852,7 +4852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4871,7 +4871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4892,7 +4892,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4915,7 +4915,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4940,7 +4940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4953,7 +4953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4968,7 +4968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4985,7 +4985,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4998,7 +4998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5011,7 +5011,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5026,7 +5026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5043,7 +5043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5062,7 +5062,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5083,7 +5083,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5106,7 +5106,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5131,7 +5131,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5144,7 +5144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5159,7 +5159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5176,7 +5176,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5189,7 +5189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5202,7 +5202,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5217,7 +5217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5234,7 +5234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5253,7 +5253,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5274,7 +5274,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5297,7 +5297,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5322,7 +5322,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5335,7 +5335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5350,7 +5350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5367,7 +5367,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5380,7 +5380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5408,7 +5408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5425,7 +5425,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5444,7 +5444,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5465,7 +5465,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5488,7 +5488,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5513,7 +5513,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5541,7 +5541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5558,7 +5558,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5571,7 +5571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5584,7 +5584,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5599,7 +5599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5616,7 +5616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5635,7 +5635,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5656,7 +5656,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5679,7 +5679,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5704,7 +5704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5717,7 +5717,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5732,7 +5732,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5749,7 +5749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5762,7 +5762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5775,7 +5775,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5790,7 +5790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5807,7 +5807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5826,7 +5826,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5847,7 +5847,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5870,7 +5870,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5895,7 +5895,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5908,7 +5908,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5923,7 +5923,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5940,7 +5940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5953,7 +5953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5966,7 +5966,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5981,7 +5981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5998,7 +5998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6017,7 +6017,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6038,7 +6038,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6061,7 +6061,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6086,7 +6086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6099,7 +6099,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6114,7 +6114,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6131,7 +6131,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6144,7 +6144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6157,7 +6157,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6189,7 +6189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6208,7 +6208,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6229,7 +6229,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6252,7 +6252,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6277,7 +6277,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6290,7 +6290,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6322,7 +6322,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6335,7 +6335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6348,7 +6348,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6363,7 +6363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6380,7 +6380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6399,7 +6399,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6420,7 +6420,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6443,7 +6443,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6468,7 +6468,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6481,7 +6481,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6496,7 +6496,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6513,7 +6513,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6717,7 +6717,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6730,7 +6730,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6745,7 +6745,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6762,7 +6762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6781,7 +6781,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6802,7 +6802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6825,7 +6825,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6850,7 +6850,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6863,7 +6863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6878,7 +6878,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6895,7 +6895,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6908,7 +6908,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6921,7 +6921,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6936,7 +6936,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6953,7 +6953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6972,7 +6972,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6993,7 +6993,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7016,7 +7016,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7041,7 +7041,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7054,7 +7054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7069,7 +7069,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7086,7 +7086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7099,7 +7099,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7112,7 +7112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7127,7 +7127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7144,7 +7144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7163,7 +7163,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7184,7 +7184,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7207,7 +7207,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7232,7 +7232,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7245,7 +7245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7260,7 +7260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7277,7 +7277,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7290,7 +7290,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7303,7 +7303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7318,7 +7318,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7335,7 +7335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7354,7 +7354,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7375,7 +7375,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7398,7 +7398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7423,7 +7423,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7436,7 +7436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7451,7 +7451,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7468,7 +7468,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -206,7 +206,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -227,7 +227,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -250,7 +250,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -288,7 +288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -303,7 +303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -320,7 +320,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -339,7 +339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -360,7 +360,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -383,7 +383,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -408,7 +408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -421,7 +421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -453,7 +453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -472,7 +472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -493,7 +493,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -516,7 +516,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -541,7 +541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -554,7 +554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -586,7 +586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -605,7 +605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -626,7 +626,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -649,7 +649,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -674,7 +674,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -687,7 +687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -719,7 +719,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -738,7 +738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -759,7 +759,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -782,7 +782,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -807,7 +807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -820,7 +820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -852,7 +852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -871,7 +871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -892,7 +892,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -915,7 +915,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -940,7 +940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -953,7 +953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -968,7 +968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -985,7 +985,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1004,7 +1004,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1025,7 +1025,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1048,7 +1048,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1073,7 +1073,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1086,7 +1086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1101,7 +1101,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1118,7 +1118,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1137,7 +1137,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1158,7 +1158,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1181,7 +1181,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1206,7 +1206,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1219,7 +1219,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1251,7 +1251,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1270,7 +1270,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1291,7 +1291,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1314,7 +1314,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1352,7 +1352,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1367,7 +1367,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1384,7 +1384,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1403,7 +1403,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1424,7 +1424,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1447,7 +1447,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1472,7 +1472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1485,7 +1485,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1500,7 +1500,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1536,7 +1536,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1557,7 +1557,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1580,7 +1580,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1605,7 +1605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1618,7 +1618,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1633,7 +1633,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1650,7 +1650,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1669,7 +1669,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1690,7 +1690,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1713,7 +1713,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1738,7 +1738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1751,7 +1751,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1766,7 +1766,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1783,7 +1783,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1802,7 +1802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1823,7 +1823,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1846,7 +1846,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1871,7 +1871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1884,7 +1884,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1916,7 +1916,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1935,7 +1935,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1956,7 +1956,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1979,7 +1979,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2004,7 +2004,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2017,7 +2017,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2032,7 +2032,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2049,7 +2049,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2068,7 +2068,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2089,7 +2089,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2112,7 +2112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2137,7 +2137,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2150,7 +2150,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2165,7 +2165,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2182,7 +2182,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2201,7 +2201,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2222,7 +2222,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2270,7 +2270,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2283,7 +2283,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2298,7 +2298,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2315,7 +2315,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2334,7 +2334,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2355,7 +2355,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2403,7 +2403,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2416,7 +2416,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2431,7 +2431,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2448,7 +2448,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2467,7 +2467,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2488,7 +2488,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2511,7 +2511,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2536,7 +2536,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2549,7 +2549,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2564,7 +2564,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2581,7 +2581,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2600,7 +2600,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2621,7 +2621,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2669,7 +2669,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2682,7 +2682,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2697,7 +2697,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2714,7 +2714,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2733,7 +2733,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2754,7 +2754,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2802,7 +2802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2815,7 +2815,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2830,7 +2830,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2847,7 +2847,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2866,7 +2866,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2887,7 +2887,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2910,7 +2910,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2935,7 +2935,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2948,7 +2948,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2963,7 +2963,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2980,7 +2980,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2999,7 +2999,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3020,7 +3020,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3043,7 +3043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3068,7 +3068,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3081,7 +3081,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3096,7 +3096,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3113,7 +3113,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3132,7 +3132,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3153,7 +3153,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3176,7 +3176,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3201,7 +3201,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3214,7 +3214,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3229,7 +3229,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3265,7 +3265,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3286,7 +3286,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3309,7 +3309,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3334,7 +3334,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3347,7 +3347,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3362,7 +3362,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3379,7 +3379,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3398,7 +3398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3419,7 +3419,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3442,7 +3442,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3467,7 +3467,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3480,7 +3480,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3495,7 +3495,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3512,7 +3512,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3531,7 +3531,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3552,7 +3552,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3575,7 +3575,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3600,7 +3600,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3613,7 +3613,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3628,7 +3628,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3645,7 +3645,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3664,7 +3664,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3685,7 +3685,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3708,7 +3708,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3733,7 +3733,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3746,7 +3746,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3761,7 +3761,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3778,7 +3778,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3797,7 +3797,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3818,7 +3818,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3841,7 +3841,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3866,7 +3866,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3879,7 +3879,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3894,7 +3894,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3911,7 +3911,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3930,7 +3930,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3951,7 +3951,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3974,7 +3974,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3999,7 +3999,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4012,7 +4012,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4027,7 +4027,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4044,7 +4044,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4063,7 +4063,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4132,7 +4132,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4145,7 +4145,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4160,7 +4160,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4177,7 +4177,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4196,7 +4196,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4240,7 +4240,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4265,7 +4265,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4278,7 +4278,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4293,7 +4293,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4310,7 +4310,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4329,7 +4329,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4350,7 +4350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4373,7 +4373,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4398,7 +4398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4411,7 +4411,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4426,7 +4426,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4443,7 +4443,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4462,7 +4462,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4483,7 +4483,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4506,7 +4506,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4531,7 +4531,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4544,7 +4544,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4559,7 +4559,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4576,7 +4576,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4595,7 +4595,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4639,7 +4639,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4664,7 +4664,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4677,7 +4677,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4692,7 +4692,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4709,7 +4709,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4728,7 +4728,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4772,7 +4772,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4797,7 +4797,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4810,7 +4810,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4825,7 +4825,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4842,7 +4842,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4861,7 +4861,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4882,7 +4882,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4905,7 +4905,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4930,7 +4930,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4943,7 +4943,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4958,7 +4958,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4975,7 +4975,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4994,7 +4994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5015,7 +5015,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5038,7 +5038,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5063,7 +5063,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5076,7 +5076,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5091,7 +5091,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5108,7 +5108,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5127,7 +5127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5148,7 +5148,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5171,7 +5171,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5196,7 +5196,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5209,7 +5209,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5224,7 +5224,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5241,7 +5241,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5260,7 +5260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5281,7 +5281,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5304,7 +5304,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5329,7 +5329,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5342,7 +5342,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5357,7 +5357,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5374,7 +5374,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5414,7 +5414,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5437,7 +5437,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5462,7 +5462,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5475,7 +5475,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5490,7 +5490,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5507,7 +5507,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5547,7 +5547,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5570,7 +5570,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5595,7 +5595,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5608,7 +5608,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5623,7 +5623,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5640,7 +5640,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5659,7 +5659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5680,7 +5680,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5703,7 +5703,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5728,7 +5728,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5741,7 +5741,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5756,7 +5756,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5773,7 +5773,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5792,7 +5792,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5813,7 +5813,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5836,7 +5836,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5861,7 +5861,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5874,7 +5874,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5889,7 +5889,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5906,7 +5906,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5925,7 +5925,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5946,7 +5946,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5969,7 +5969,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5994,7 +5994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6007,7 +6007,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6022,7 +6022,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6039,7 +6039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6058,7 +6058,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6079,7 +6079,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6102,7 +6102,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6127,7 +6127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6140,7 +6140,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6155,7 +6155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6191,7 +6191,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6212,7 +6212,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6235,7 +6235,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6260,7 +6260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6273,7 +6273,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6288,7 +6288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6324,7 +6324,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6345,7 +6345,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6368,7 +6368,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6393,7 +6393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6406,7 +6406,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6421,7 +6421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6438,7 +6438,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6457,7 +6457,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6478,7 +6478,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6501,7 +6501,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6723,7 +6723,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6744,7 +6744,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6767,7 +6767,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6792,7 +6792,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6805,7 +6805,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6820,7 +6820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6837,7 +6837,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6856,7 +6856,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6877,7 +6877,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6900,7 +6900,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -200,7 +200,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -213,7 +213,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -228,7 +228,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -245,7 +245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -264,7 +264,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -285,7 +285,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -308,7 +308,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -333,7 +333,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -346,7 +346,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -361,7 +361,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -378,7 +378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -391,7 +391,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -404,7 +404,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -419,7 +419,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -455,7 +455,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -476,7 +476,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -499,7 +499,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -524,7 +524,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -537,7 +537,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -552,7 +552,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -582,7 +582,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -597,7 +597,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -614,7 +614,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -633,7 +633,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -654,7 +654,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -677,7 +677,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -715,7 +715,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -730,7 +730,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -747,7 +747,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -766,7 +766,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -787,7 +787,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -810,7 +810,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -848,7 +848,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -863,7 +863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -880,7 +880,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -893,7 +893,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -906,7 +906,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -921,7 +921,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -938,7 +938,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -957,7 +957,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -978,7 +978,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1001,7 +1001,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1026,7 +1026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1039,7 +1039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1054,7 +1054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1071,7 +1071,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1084,7 +1084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1097,7 +1097,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1112,7 +1112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1129,7 +1129,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1148,7 +1148,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1169,7 +1169,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1192,7 +1192,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1230,7 +1230,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1245,7 +1245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1262,7 +1262,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1275,7 +1275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1288,7 +1288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1303,7 +1303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1320,7 +1320,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1360,7 +1360,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1383,7 +1383,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1408,7 +1408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1421,7 +1421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1436,7 +1436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1453,7 +1453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1466,7 +1466,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1481,7 +1481,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1498,7 +1498,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1538,7 +1538,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1561,7 +1561,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1586,7 +1586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1599,7 +1599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1614,7 +1614,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1631,7 +1631,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1644,7 +1644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1657,7 +1657,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1672,7 +1672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1689,7 +1689,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1708,7 +1708,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1729,7 +1729,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1752,7 +1752,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1777,7 +1777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1790,7 +1790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1805,7 +1805,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1822,7 +1822,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1835,7 +1835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1848,7 +1848,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1863,7 +1863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1880,7 +1880,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1920,7 +1920,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1943,7 +1943,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1968,7 +1968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1981,7 +1981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1996,7 +1996,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2013,7 +2013,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2026,7 +2026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2039,7 +2039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2054,7 +2054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2071,7 +2071,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2090,7 +2090,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2111,7 +2111,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2134,7 +2134,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2159,7 +2159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2172,7 +2172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2187,7 +2187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2204,7 +2204,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2217,7 +2217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2230,7 +2230,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2262,7 +2262,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2281,7 +2281,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2302,7 +2302,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2325,7 +2325,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2350,7 +2350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2363,7 +2363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2395,7 +2395,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2408,7 +2408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2421,7 +2421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2436,7 +2436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2453,7 +2453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2472,7 +2472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2493,7 +2493,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2516,7 +2516,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2541,7 +2541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2554,7 +2554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2569,7 +2569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2586,7 +2586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2599,7 +2599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2612,7 +2612,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2627,7 +2627,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2663,7 +2663,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2684,7 +2684,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2707,7 +2707,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2732,7 +2732,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2745,7 +2745,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2760,7 +2760,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2790,7 +2790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2803,7 +2803,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2818,7 +2818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2835,7 +2835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2854,7 +2854,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2875,7 +2875,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2898,7 +2898,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2923,7 +2923,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2936,7 +2936,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2951,7 +2951,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2968,7 +2968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2981,7 +2981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2994,7 +2994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3009,7 +3009,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3026,7 +3026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3045,7 +3045,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3066,7 +3066,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3089,7 +3089,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3114,7 +3114,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3127,7 +3127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3142,7 +3142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3159,7 +3159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3172,7 +3172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3185,7 +3185,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3200,7 +3200,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3217,7 +3217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3236,7 +3236,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3257,7 +3257,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3280,7 +3280,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3305,7 +3305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3318,7 +3318,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3333,7 +3333,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3350,7 +3350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3363,7 +3363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3376,7 +3376,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3391,7 +3391,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3408,7 +3408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3427,7 +3427,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3448,7 +3448,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3471,7 +3471,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3496,7 +3496,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3509,7 +3509,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3524,7 +3524,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3541,7 +3541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3554,7 +3554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3569,7 +3569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3586,7 +3586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3605,7 +3605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3626,7 +3626,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3649,7 +3649,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3674,7 +3674,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3687,7 +3687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3702,7 +3702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3719,7 +3719,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3738,7 +3738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3759,7 +3759,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3782,7 +3782,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3807,7 +3807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3820,7 +3820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3835,7 +3835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3852,7 +3852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3865,7 +3865,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3878,7 +3878,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3893,7 +3893,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3910,7 +3910,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3929,7 +3929,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3950,7 +3950,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3973,7 +3973,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3998,7 +3998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4011,7 +4011,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4026,7 +4026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4043,7 +4043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4056,7 +4056,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4069,7 +4069,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4101,7 +4101,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4120,7 +4120,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4141,7 +4141,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4164,7 +4164,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4189,7 +4189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4202,7 +4202,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4234,7 +4234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4247,7 +4247,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4260,7 +4260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4275,7 +4275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4292,7 +4292,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4311,7 +4311,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4332,7 +4332,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4355,7 +4355,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4380,7 +4380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4393,7 +4393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4408,7 +4408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4425,7 +4425,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4438,7 +4438,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4453,7 +4453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4470,7 +4470,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4489,7 +4489,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4510,7 +4510,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4533,7 +4533,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4558,7 +4558,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4571,7 +4571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4586,7 +4586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4603,7 +4603,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4629,7 +4629,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4644,7 +4644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4661,7 +4661,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4680,7 +4680,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4701,7 +4701,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4724,7 +4724,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4762,7 +4762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4777,7 +4777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4794,7 +4794,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4807,7 +4807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4820,7 +4820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4835,7 +4835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4852,7 +4852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4871,7 +4871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4892,7 +4892,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4915,7 +4915,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4940,7 +4940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4953,7 +4953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4968,7 +4968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4985,7 +4985,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4998,7 +4998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5011,7 +5011,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5026,7 +5026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5043,7 +5043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5062,7 +5062,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5083,7 +5083,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5106,7 +5106,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5131,7 +5131,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5144,7 +5144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5159,7 +5159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5176,7 +5176,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5189,7 +5189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5202,7 +5202,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5217,7 +5217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5234,7 +5234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5253,7 +5253,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5274,7 +5274,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5297,7 +5297,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5322,7 +5322,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5335,7 +5335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5350,7 +5350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5367,7 +5367,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5380,7 +5380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5408,7 +5408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5425,7 +5425,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5444,7 +5444,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5465,7 +5465,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5488,7 +5488,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5513,7 +5513,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5541,7 +5541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5558,7 +5558,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5571,7 +5571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5584,7 +5584,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5599,7 +5599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5616,7 +5616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5635,7 +5635,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5656,7 +5656,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5679,7 +5679,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5704,7 +5704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5717,7 +5717,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5732,7 +5732,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5749,7 +5749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5762,7 +5762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5775,7 +5775,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5790,7 +5790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5807,7 +5807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5826,7 +5826,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5847,7 +5847,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5870,7 +5870,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5895,7 +5895,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5908,7 +5908,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5923,7 +5923,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5940,7 +5940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5953,7 +5953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5966,7 +5966,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5981,7 +5981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5998,7 +5998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6017,7 +6017,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6038,7 +6038,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6061,7 +6061,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6086,7 +6086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6099,7 +6099,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6114,7 +6114,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6131,7 +6131,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6144,7 +6144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6157,7 +6157,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6189,7 +6189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6208,7 +6208,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6229,7 +6229,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6252,7 +6252,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6277,7 +6277,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6290,7 +6290,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6322,7 +6322,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6335,7 +6335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6348,7 +6348,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6363,7 +6363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6380,7 +6380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6399,7 +6399,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6420,7 +6420,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6443,7 +6443,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6468,7 +6468,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6481,7 +6481,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6496,7 +6496,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6513,7 +6513,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6717,7 +6717,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6730,7 +6730,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6745,7 +6745,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6762,7 +6762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6781,7 +6781,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6802,7 +6802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6825,7 +6825,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6850,7 +6850,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6863,7 +6863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6878,7 +6878,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6895,7 +6895,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6908,7 +6908,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6921,7 +6921,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6936,7 +6936,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6953,7 +6953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6972,7 +6972,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6993,7 +6993,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7016,7 +7016,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7041,7 +7041,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7054,7 +7054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7069,7 +7069,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7086,7 +7086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7099,7 +7099,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7112,7 +7112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7127,7 +7127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7144,7 +7144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7163,7 +7163,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7184,7 +7184,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7207,7 +7207,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7232,7 +7232,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7245,7 +7245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7260,7 +7260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7277,7 +7277,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7290,7 +7290,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7303,7 +7303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7318,7 +7318,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7335,7 +7335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7354,7 +7354,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7375,7 +7375,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7398,7 +7398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7423,7 +7423,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7436,7 +7436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7451,7 +7451,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7468,7 +7468,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -206,7 +206,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -227,7 +227,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -250,7 +250,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -288,7 +288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -303,7 +303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -320,7 +320,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -339,7 +339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -360,7 +360,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -383,7 +383,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -408,7 +408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -421,7 +421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -453,7 +453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -472,7 +472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -493,7 +493,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -516,7 +516,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -541,7 +541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -554,7 +554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -586,7 +586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -605,7 +605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -626,7 +626,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -649,7 +649,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -674,7 +674,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -687,7 +687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -719,7 +719,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -738,7 +738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -759,7 +759,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -782,7 +782,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -807,7 +807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -820,7 +820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -852,7 +852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -871,7 +871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -892,7 +892,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -915,7 +915,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -940,7 +940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -953,7 +953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -968,7 +968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -985,7 +985,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1004,7 +1004,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1025,7 +1025,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1048,7 +1048,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1073,7 +1073,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1086,7 +1086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1101,7 +1101,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1118,7 +1118,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1137,7 +1137,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1158,7 +1158,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1181,7 +1181,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1206,7 +1206,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1219,7 +1219,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1251,7 +1251,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1270,7 +1270,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1291,7 +1291,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1314,7 +1314,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1352,7 +1352,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1367,7 +1367,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1384,7 +1384,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1403,7 +1403,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1424,7 +1424,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1447,7 +1447,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1472,7 +1472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1485,7 +1485,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1500,7 +1500,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1536,7 +1536,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1557,7 +1557,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1580,7 +1580,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1605,7 +1605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1618,7 +1618,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1633,7 +1633,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1650,7 +1650,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1669,7 +1669,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1690,7 +1690,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1713,7 +1713,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1738,7 +1738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1751,7 +1751,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1766,7 +1766,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1783,7 +1783,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1802,7 +1802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1823,7 +1823,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1846,7 +1846,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1871,7 +1871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1884,7 +1884,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1916,7 +1916,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1935,7 +1935,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1956,7 +1956,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1979,7 +1979,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2004,7 +2004,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2017,7 +2017,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2032,7 +2032,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2049,7 +2049,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2068,7 +2068,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2089,7 +2089,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2112,7 +2112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2137,7 +2137,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2150,7 +2150,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2165,7 +2165,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2182,7 +2182,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2201,7 +2201,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2222,7 +2222,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2270,7 +2270,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2283,7 +2283,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2298,7 +2298,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2315,7 +2315,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2334,7 +2334,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2355,7 +2355,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2403,7 +2403,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2416,7 +2416,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2431,7 +2431,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2448,7 +2448,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2467,7 +2467,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2488,7 +2488,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2511,7 +2511,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2536,7 +2536,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2549,7 +2549,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2564,7 +2564,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2581,7 +2581,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2600,7 +2600,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2621,7 +2621,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2669,7 +2669,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2682,7 +2682,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2697,7 +2697,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2714,7 +2714,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2733,7 +2733,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2754,7 +2754,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2802,7 +2802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2815,7 +2815,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2830,7 +2830,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2847,7 +2847,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2866,7 +2866,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2887,7 +2887,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2910,7 +2910,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2935,7 +2935,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2948,7 +2948,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2963,7 +2963,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2980,7 +2980,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2999,7 +2999,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3020,7 +3020,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3043,7 +3043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3068,7 +3068,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3081,7 +3081,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3096,7 +3096,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3113,7 +3113,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3132,7 +3132,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3153,7 +3153,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3176,7 +3176,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3201,7 +3201,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3214,7 +3214,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3229,7 +3229,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3265,7 +3265,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3286,7 +3286,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3309,7 +3309,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3334,7 +3334,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3347,7 +3347,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3362,7 +3362,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3379,7 +3379,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3398,7 +3398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3419,7 +3419,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3442,7 +3442,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3467,7 +3467,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3480,7 +3480,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3495,7 +3495,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3512,7 +3512,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3531,7 +3531,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3552,7 +3552,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3575,7 +3575,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3600,7 +3600,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3613,7 +3613,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3628,7 +3628,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3645,7 +3645,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3664,7 +3664,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3685,7 +3685,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3708,7 +3708,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3733,7 +3733,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3746,7 +3746,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3761,7 +3761,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3778,7 +3778,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3797,7 +3797,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3818,7 +3818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3841,7 +3841,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3866,7 +3866,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3879,7 +3879,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3894,7 +3894,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3911,7 +3911,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3930,7 +3930,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3951,7 +3951,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3974,7 +3974,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3999,7 +3999,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4012,7 +4012,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4027,7 +4027,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4044,7 +4044,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4063,7 +4063,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4132,7 +4132,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4145,7 +4145,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4160,7 +4160,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4177,7 +4177,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4196,7 +4196,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4240,7 +4240,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4265,7 +4265,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4278,7 +4278,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4293,7 +4293,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4310,7 +4310,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4329,7 +4329,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4350,7 +4350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4373,7 +4373,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4398,7 +4398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4411,7 +4411,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4426,7 +4426,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4443,7 +4443,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4462,7 +4462,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4483,7 +4483,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4506,7 +4506,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4531,7 +4531,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4544,7 +4544,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4559,7 +4559,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4576,7 +4576,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4595,7 +4595,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4639,7 +4639,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4664,7 +4664,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4677,7 +4677,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4692,7 +4692,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4709,7 +4709,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4728,7 +4728,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4772,7 +4772,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4797,7 +4797,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4810,7 +4810,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4825,7 +4825,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4842,7 +4842,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4861,7 +4861,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4882,7 +4882,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4905,7 +4905,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4930,7 +4930,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4943,7 +4943,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4958,7 +4958,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4975,7 +4975,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4994,7 +4994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5015,7 +5015,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5038,7 +5038,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5063,7 +5063,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5076,7 +5076,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5091,7 +5091,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5108,7 +5108,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5127,7 +5127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5148,7 +5148,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5171,7 +5171,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5196,7 +5196,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5209,7 +5209,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5224,7 +5224,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5241,7 +5241,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5260,7 +5260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5281,7 +5281,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5304,7 +5304,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5329,7 +5329,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5342,7 +5342,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5357,7 +5357,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5374,7 +5374,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5414,7 +5414,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5437,7 +5437,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5462,7 +5462,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5475,7 +5475,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5490,7 +5490,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5507,7 +5507,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5547,7 +5547,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5570,7 +5570,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5595,7 +5595,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5608,7 +5608,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5623,7 +5623,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5640,7 +5640,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5659,7 +5659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5680,7 +5680,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5703,7 +5703,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5728,7 +5728,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5741,7 +5741,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5756,7 +5756,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5773,7 +5773,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5792,7 +5792,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5813,7 +5813,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5836,7 +5836,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5861,7 +5861,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5874,7 +5874,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5889,7 +5889,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5906,7 +5906,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5925,7 +5925,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5946,7 +5946,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5969,7 +5969,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5994,7 +5994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6007,7 +6007,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6022,7 +6022,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6039,7 +6039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6058,7 +6058,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6079,7 +6079,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6102,7 +6102,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6127,7 +6127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6140,7 +6140,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6155,7 +6155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6191,7 +6191,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6212,7 +6212,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6235,7 +6235,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6260,7 +6260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6273,7 +6273,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6288,7 +6288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6324,7 +6324,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6345,7 +6345,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6368,7 +6368,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6393,7 +6393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6406,7 +6406,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6421,7 +6421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6438,7 +6438,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6457,7 +6457,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6478,7 +6478,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6501,7 +6501,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6723,7 +6723,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6744,7 +6744,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6767,7 +6767,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6792,7 +6792,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6805,7 +6805,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6820,7 +6820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6837,7 +6837,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6856,7 +6856,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6877,7 +6877,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6900,7 +6900,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -200,7 +200,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -213,7 +213,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -228,7 +228,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -245,7 +245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -264,7 +264,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -285,7 +285,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -308,7 +308,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -333,7 +333,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -346,7 +346,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -361,7 +361,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -378,7 +378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -391,7 +391,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -404,7 +404,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -419,7 +419,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -455,7 +455,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -476,7 +476,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -499,7 +499,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -524,7 +524,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -537,7 +537,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -552,7 +552,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -582,7 +582,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -597,7 +597,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -614,7 +614,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -633,7 +633,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -654,7 +654,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -677,7 +677,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -715,7 +715,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -730,7 +730,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -747,7 +747,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -766,7 +766,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -787,7 +787,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -810,7 +810,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -848,7 +848,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -863,7 +863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -880,7 +880,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -893,7 +893,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -906,7 +906,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -921,7 +921,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -938,7 +938,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -957,7 +957,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -978,7 +978,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1001,7 +1001,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1026,7 +1026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1039,7 +1039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1054,7 +1054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1071,7 +1071,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1084,7 +1084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1097,7 +1097,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1112,7 +1112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1129,7 +1129,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1148,7 +1148,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1169,7 +1169,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1192,7 +1192,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1230,7 +1230,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1245,7 +1245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1262,7 +1262,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1275,7 +1275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1288,7 +1288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1303,7 +1303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1320,7 +1320,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1360,7 +1360,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1383,7 +1383,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1408,7 +1408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1421,7 +1421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1436,7 +1436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1453,7 +1453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1466,7 +1466,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1481,7 +1481,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1498,7 +1498,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1538,7 +1538,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1561,7 +1561,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1586,7 +1586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1599,7 +1599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1614,7 +1614,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1631,7 +1631,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1644,7 +1644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1657,7 +1657,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1672,7 +1672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1689,7 +1689,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1708,7 +1708,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1729,7 +1729,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1752,7 +1752,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1777,7 +1777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1790,7 +1790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1805,7 +1805,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1822,7 +1822,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1835,7 +1835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1848,7 +1848,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1863,7 +1863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1880,7 +1880,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1920,7 +1920,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1943,7 +1943,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1968,7 +1968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1981,7 +1981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1996,7 +1996,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2013,7 +2013,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2026,7 +2026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2039,7 +2039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2054,7 +2054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2071,7 +2071,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2090,7 +2090,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2111,7 +2111,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2134,7 +2134,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2159,7 +2159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2172,7 +2172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2187,7 +2187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2204,7 +2204,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2217,7 +2217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2230,7 +2230,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2262,7 +2262,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2281,7 +2281,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2302,7 +2302,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2325,7 +2325,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2350,7 +2350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2363,7 +2363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2395,7 +2395,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2408,7 +2408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2421,7 +2421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2436,7 +2436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2453,7 +2453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2472,7 +2472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2493,7 +2493,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2516,7 +2516,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2541,7 +2541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2554,7 +2554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2569,7 +2569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2586,7 +2586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2599,7 +2599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2612,7 +2612,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2627,7 +2627,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2663,7 +2663,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2684,7 +2684,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2707,7 +2707,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2732,7 +2732,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2745,7 +2745,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2760,7 +2760,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2790,7 +2790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2803,7 +2803,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2818,7 +2818,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2835,7 +2835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2854,7 +2854,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2875,7 +2875,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2898,7 +2898,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2923,7 +2923,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2936,7 +2936,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2951,7 +2951,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2968,7 +2968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2981,7 +2981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2994,7 +2994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3009,7 +3009,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3026,7 +3026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3045,7 +3045,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3066,7 +3066,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3089,7 +3089,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3114,7 +3114,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3127,7 +3127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3142,7 +3142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3159,7 +3159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3172,7 +3172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3185,7 +3185,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3200,7 +3200,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3217,7 +3217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3236,7 +3236,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3257,7 +3257,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3280,7 +3280,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3305,7 +3305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3318,7 +3318,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3333,7 +3333,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3350,7 +3350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3363,7 +3363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3376,7 +3376,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3391,7 +3391,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3408,7 +3408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3427,7 +3427,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3448,7 +3448,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3471,7 +3471,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3496,7 +3496,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3509,7 +3509,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3524,7 +3524,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3541,7 +3541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3554,7 +3554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3569,7 +3569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3586,7 +3586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3605,7 +3605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3626,7 +3626,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3649,7 +3649,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3674,7 +3674,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3687,7 +3687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3702,7 +3702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3719,7 +3719,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3738,7 +3738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3759,7 +3759,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3782,7 +3782,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3807,7 +3807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3820,7 +3820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3835,7 +3835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3852,7 +3852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3865,7 +3865,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3878,7 +3878,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3893,7 +3893,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3910,7 +3910,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3929,7 +3929,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3950,7 +3950,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3973,7 +3973,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3998,7 +3998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4011,7 +4011,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4026,7 +4026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4043,7 +4043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4056,7 +4056,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4069,7 +4069,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4101,7 +4101,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4120,7 +4120,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4141,7 +4141,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4164,7 +4164,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4189,7 +4189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4202,7 +4202,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4234,7 +4234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4247,7 +4247,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4260,7 +4260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4275,7 +4275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4292,7 +4292,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4311,7 +4311,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4332,7 +4332,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4355,7 +4355,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4380,7 +4380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4393,7 +4393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4408,7 +4408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4425,7 +4425,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4438,7 +4438,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4453,7 +4453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4470,7 +4470,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4489,7 +4489,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4510,7 +4510,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4533,7 +4533,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4558,7 +4558,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4571,7 +4571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4586,7 +4586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4603,7 +4603,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4629,7 +4629,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4644,7 +4644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4661,7 +4661,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4680,7 +4680,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4701,7 +4701,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4724,7 +4724,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4762,7 +4762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4777,7 +4777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4794,7 +4794,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4807,7 +4807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4820,7 +4820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4835,7 +4835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4852,7 +4852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4871,7 +4871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4892,7 +4892,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4915,7 +4915,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4940,7 +4940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4953,7 +4953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4968,7 +4968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4985,7 +4985,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4998,7 +4998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5011,7 +5011,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5026,7 +5026,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5043,7 +5043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5062,7 +5062,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5083,7 +5083,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5106,7 +5106,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5131,7 +5131,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5144,7 +5144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5159,7 +5159,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5176,7 +5176,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5189,7 +5189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5202,7 +5202,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5217,7 +5217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5234,7 +5234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5253,7 +5253,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5274,7 +5274,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5297,7 +5297,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5322,7 +5322,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5335,7 +5335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5350,7 +5350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5367,7 +5367,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5380,7 +5380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5408,7 +5408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5425,7 +5425,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5444,7 +5444,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5465,7 +5465,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5488,7 +5488,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5513,7 +5513,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5541,7 +5541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5558,7 +5558,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5571,7 +5571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5584,7 +5584,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5599,7 +5599,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5616,7 +5616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5635,7 +5635,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5656,7 +5656,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5679,7 +5679,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5704,7 +5704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5717,7 +5717,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5732,7 +5732,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5749,7 +5749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5762,7 +5762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5775,7 +5775,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5790,7 +5790,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5807,7 +5807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5826,7 +5826,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5847,7 +5847,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5870,7 +5870,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5895,7 +5895,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5908,7 +5908,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5923,7 +5923,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5940,7 +5940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5953,7 +5953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5966,7 +5966,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5981,7 +5981,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5998,7 +5998,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6017,7 +6017,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6038,7 +6038,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6061,7 +6061,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6086,7 +6086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6099,7 +6099,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6114,7 +6114,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6131,7 +6131,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6144,7 +6144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6157,7 +6157,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6189,7 +6189,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6208,7 +6208,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6229,7 +6229,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6252,7 +6252,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6277,7 +6277,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6290,7 +6290,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6322,7 +6322,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6335,7 +6335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6348,7 +6348,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6363,7 +6363,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6380,7 +6380,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6399,7 +6399,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6420,7 +6420,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6443,7 +6443,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6468,7 +6468,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6481,7 +6481,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6496,7 +6496,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6513,7 +6513,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f32.nxv2i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f32.nxv2i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f32.nxv4i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f32.nxv4i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f32.nxv4i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f32.nxv8i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6717,7 +6717,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6730,7 +6730,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6745,7 +6745,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6762,7 +6762,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6781,7 +6781,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6802,7 +6802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6825,7 +6825,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6850,7 +6850,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6863,7 +6863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6878,7 +6878,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6895,7 +6895,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6908,7 +6908,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6921,7 +6921,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6936,7 +6936,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6953,7 +6953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6972,7 +6972,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6993,7 +6993,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7016,7 +7016,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7041,7 +7041,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7054,7 +7054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7069,7 +7069,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7086,7 +7086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7099,7 +7099,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7112,7 +7112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7127,7 +7127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7144,7 +7144,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7163,7 +7163,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7184,7 +7184,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7207,7 +7207,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7232,7 +7232,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7245,7 +7245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7260,7 +7260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7277,7 +7277,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7290,7 +7290,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f64.nxv1i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7303,7 +7303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f64.nxv1i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7318,7 +7318,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7335,7 +7335,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7354,7 +7354,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7375,7 +7375,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7398,7 +7398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7423,7 +7423,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f64.nxv2i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7436,7 +7436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f64.nxv2i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7451,7 +7451,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f64.nxv2i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7468,7 +7468,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f64.nxv4i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c @@ -7481,7 +7481,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7494,7 +7494,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7509,7 +7509,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7526,7 +7526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7545,7 +7545,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7566,7 +7566,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7589,7 +7589,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7614,7 +7614,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7627,7 +7627,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7642,7 +7642,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7659,7 +7659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7672,7 +7672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7685,7 +7685,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7700,7 +7700,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7717,7 +7717,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7736,7 +7736,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7757,7 +7757,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7780,7 +7780,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7805,7 +7805,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7818,7 +7818,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7833,7 +7833,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7850,7 +7850,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7863,7 +7863,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7876,7 +7876,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7891,7 +7891,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7908,7 +7908,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7927,7 +7927,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7948,7 +7948,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7971,7 +7971,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7996,7 +7996,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8009,7 +8009,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8024,7 +8024,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -8041,7 +8041,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8054,7 +8054,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4f16.nxv4i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8067,7 +8067,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4f16.nxv4i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8082,7 +8082,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -8099,7 +8099,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -8118,7 +8118,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -8139,7 +8139,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -8162,7 +8162,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -8187,7 +8187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8f16.nxv8i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8200,7 +8200,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8f16.nxv8i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8215,7 +8215,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8f16.nxv8i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c @@ -6925,7 +6925,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6938,7 +6938,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6953,7 +6953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6970,7 +6970,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6989,7 +6989,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7010,7 +7010,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7033,7 +7033,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7058,7 +7058,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7071,7 +7071,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7086,7 +7086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7103,7 +7103,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7122,7 +7122,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7143,7 +7143,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7166,7 +7166,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7191,7 +7191,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7204,7 +7204,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7219,7 +7219,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7236,7 +7236,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7255,7 +7255,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7276,7 +7276,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7299,7 +7299,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7324,7 +7324,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7337,7 +7337,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7352,7 +7352,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7369,7 +7369,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7388,7 +7388,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7409,7 +7409,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7432,7 +7432,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7457,7 +7457,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7470,7 +7470,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7485,7 +7485,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7502,7 +7502,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7521,7 +7521,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7542,7 +7542,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7565,7 +7565,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7590,7 +7590,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7603,7 +7603,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7618,7 +7618,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7635,7 +7635,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7654,7 +7654,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7675,7 +7675,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7698,7 +7698,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7723,7 +7723,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f16.nxv1i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7736,7 +7736,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f16.nxv1i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7751,7 +7751,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7768,7 +7768,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7787,7 +7787,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7808,7 +7808,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7831,7 +7831,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7856,7 +7856,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2f16.nxv2i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7869,7 +7869,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2f16.nxv2i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7884,7 +7884,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7901,7 +7901,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7920,7 +7920,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7941,7 +7941,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7964,7 +7964,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -206,7 +206,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -227,7 +227,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -250,7 +250,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -288,7 +288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -303,7 +303,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -320,7 +320,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -339,7 +339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -360,7 +360,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -383,7 +383,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -408,7 +408,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -421,7 +421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -453,7 +453,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -472,7 +472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -493,7 +493,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -516,7 +516,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -541,7 +541,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -554,7 +554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -586,7 +586,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -605,7 +605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -626,7 +626,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -649,7 +649,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -674,7 +674,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -687,7 +687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -719,7 +719,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -738,7 +738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -759,7 +759,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -782,7 +782,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -807,7 +807,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -820,7 +820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -852,7 +852,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -871,7 +871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -892,7 +892,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -915,7 +915,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -940,7 +940,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -953,7 +953,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -968,7 +968,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -985,7 +985,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1004,7 +1004,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1025,7 +1025,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1048,7 +1048,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1073,7 +1073,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1086,7 +1086,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1101,7 +1101,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1118,7 +1118,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1137,7 +1137,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1158,7 +1158,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1181,7 +1181,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1206,7 +1206,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1219,7 +1219,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1251,7 +1251,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1270,7 +1270,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1291,7 +1291,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1314,7 +1314,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1352,7 +1352,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1367,7 +1367,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1384,7 +1384,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1403,7 +1403,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1424,7 +1424,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1447,7 +1447,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1472,7 +1472,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1485,7 +1485,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1500,7 +1500,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1536,7 +1536,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1557,7 +1557,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1580,7 +1580,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1605,7 +1605,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1618,7 +1618,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1633,7 +1633,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1650,7 +1650,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1669,7 +1669,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1690,7 +1690,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1713,7 +1713,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1738,7 +1738,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1751,7 +1751,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1766,7 +1766,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1783,7 +1783,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1802,7 +1802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1823,7 +1823,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1846,7 +1846,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1871,7 +1871,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1884,7 +1884,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1916,7 +1916,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1935,7 +1935,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1956,7 +1956,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1979,7 +1979,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2004,7 +2004,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2017,7 +2017,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2032,7 +2032,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2049,7 +2049,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2068,7 +2068,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2089,7 +2089,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2112,7 +2112,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2137,7 +2137,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2150,7 +2150,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2165,7 +2165,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2182,7 +2182,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2201,7 +2201,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2222,7 +2222,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2270,7 +2270,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2283,7 +2283,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2298,7 +2298,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2315,7 +2315,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2334,7 +2334,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2355,7 +2355,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2403,7 +2403,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2416,7 +2416,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2431,7 +2431,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2448,7 +2448,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2467,7 +2467,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2488,7 +2488,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2511,7 +2511,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2536,7 +2536,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2549,7 +2549,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2564,7 +2564,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2581,7 +2581,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2600,7 +2600,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2621,7 +2621,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2669,7 +2669,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2682,7 +2682,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2697,7 +2697,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2714,7 +2714,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2733,7 +2733,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2754,7 +2754,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2802,7 +2802,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2815,7 +2815,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2830,7 +2830,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2847,7 +2847,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2866,7 +2866,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2887,7 +2887,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2910,7 +2910,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2935,7 +2935,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2948,7 +2948,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2963,7 +2963,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2980,7 +2980,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2999,7 +2999,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3020,7 +3020,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3043,7 +3043,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3068,7 +3068,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3081,7 +3081,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3096,7 +3096,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3113,7 +3113,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3132,7 +3132,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3153,7 +3153,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3176,7 +3176,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3201,7 +3201,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3214,7 +3214,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3229,7 +3229,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3265,7 +3265,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3286,7 +3286,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3309,7 +3309,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3334,7 +3334,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3347,7 +3347,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3362,7 +3362,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3379,7 +3379,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3398,7 +3398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3419,7 +3419,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3442,7 +3442,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3467,7 +3467,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3480,7 +3480,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3495,7 +3495,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3512,7 +3512,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3531,7 +3531,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3552,7 +3552,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3575,7 +3575,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3600,7 +3600,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3613,7 +3613,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3628,7 +3628,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3645,7 +3645,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3664,7 +3664,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3685,7 +3685,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3708,7 +3708,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3733,7 +3733,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3746,7 +3746,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3761,7 +3761,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3778,7 +3778,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3797,7 +3797,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3818,7 +3818,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3841,7 +3841,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3866,7 +3866,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3879,7 +3879,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3894,7 +3894,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3911,7 +3911,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3930,7 +3930,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3951,7 +3951,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3974,7 +3974,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3999,7 +3999,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4012,7 +4012,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4027,7 +4027,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4044,7 +4044,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4063,7 +4063,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4132,7 +4132,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4145,7 +4145,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4160,7 +4160,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4177,7 +4177,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4196,7 +4196,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4240,7 +4240,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4265,7 +4265,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4278,7 +4278,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4293,7 +4293,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4310,7 +4310,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4329,7 +4329,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4350,7 +4350,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4373,7 +4373,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4398,7 +4398,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4411,7 +4411,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4426,7 +4426,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4443,7 +4443,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4462,7 +4462,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4483,7 +4483,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4506,7 +4506,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4531,7 +4531,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4544,7 +4544,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4559,7 +4559,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4576,7 +4576,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4595,7 +4595,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4639,7 +4639,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4664,7 +4664,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4677,7 +4677,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4692,7 +4692,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4709,7 +4709,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4728,7 +4728,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4772,7 +4772,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4797,7 +4797,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4810,7 +4810,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4825,7 +4825,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4842,7 +4842,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4861,7 +4861,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4882,7 +4882,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4905,7 +4905,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4930,7 +4930,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4943,7 +4943,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4958,7 +4958,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4975,7 +4975,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4994,7 +4994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5015,7 +5015,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5038,7 +5038,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5063,7 +5063,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5076,7 +5076,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5091,7 +5091,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5108,7 +5108,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5127,7 +5127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5148,7 +5148,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5171,7 +5171,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5196,7 +5196,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5209,7 +5209,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5224,7 +5224,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5241,7 +5241,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5260,7 +5260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5281,7 +5281,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5304,7 +5304,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5329,7 +5329,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5342,7 +5342,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5357,7 +5357,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5374,7 +5374,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5414,7 +5414,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5437,7 +5437,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5462,7 +5462,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5475,7 +5475,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5490,7 +5490,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5507,7 +5507,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5547,7 +5547,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5570,7 +5570,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5595,7 +5595,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5608,7 +5608,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5623,7 +5623,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5640,7 +5640,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5659,7 +5659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5680,7 +5680,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5703,7 +5703,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5728,7 +5728,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5741,7 +5741,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5756,7 +5756,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5773,7 +5773,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5792,7 +5792,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5813,7 +5813,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5836,7 +5836,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5861,7 +5861,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5874,7 +5874,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5889,7 +5889,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5906,7 +5906,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5925,7 +5925,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5946,7 +5946,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5969,7 +5969,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5994,7 +5994,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6007,7 +6007,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6022,7 +6022,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6039,7 +6039,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6058,7 +6058,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6079,7 +6079,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6102,7 +6102,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6127,7 +6127,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6140,7 +6140,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6155,7 +6155,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6191,7 +6191,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6212,7 +6212,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6235,7 +6235,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6260,7 +6260,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6273,7 +6273,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6288,7 +6288,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6324,7 +6324,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6345,7 +6345,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6368,7 +6368,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6393,7 +6393,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6406,7 +6406,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6421,7 +6421,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6438,7 +6438,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6457,7 +6457,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6478,7 +6478,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6501,7 +6501,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6723,7 +6723,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6744,7 +6744,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6767,7 +6767,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6792,7 +6792,7 @@ // CHECK-RV64-LABEL: @test_vloxseg2ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1f32.nxv1i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6805,7 +6805,7 @@ // CHECK-RV64-LABEL: @test_vloxseg3ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1f32.nxv1i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6820,7 +6820,7 @@ // CHECK-RV64-LABEL: @test_vloxseg4ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6837,7 +6837,7 @@ // CHECK-RV64-LABEL: @test_vloxseg5ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6856,7 +6856,7 @@ // CHECK-RV64-LABEL: @test_vloxseg6ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6877,7 +6877,7 @@ // CHECK-RV64-LABEL: @test_vloxseg7ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6900,7 +6900,7 @@ // CHECK-RV64-LABEL: @test_vloxseg8ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c @@ -15,7 +15,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -24,7 +24,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -48,7 +48,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -63,7 +63,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -76,7 +76,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -93,7 +93,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -108,7 +108,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -127,7 +127,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -144,7 +144,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -165,7 +165,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -184,7 +184,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -207,7 +207,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -228,7 +228,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -253,7 +253,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -262,7 +262,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -286,7 +286,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -301,7 +301,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -314,7 +314,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -331,7 +331,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -346,7 +346,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -365,7 +365,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -382,7 +382,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -403,7 +403,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -422,7 +422,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -445,7 +445,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -466,7 +466,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -491,7 +491,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -500,7 +500,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -513,7 +513,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -524,7 +524,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -539,7 +539,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -552,7 +552,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -584,7 +584,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -603,7 +603,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -620,7 +620,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -641,7 +641,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -660,7 +660,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -683,7 +683,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -704,7 +704,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -729,7 +729,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -738,7 +738,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -751,7 +751,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -762,7 +762,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -777,7 +777,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -790,7 +790,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -807,7 +807,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -822,7 +822,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -841,7 +841,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -858,7 +858,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -879,7 +879,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -898,7 +898,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -921,7 +921,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -942,7 +942,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -967,7 +967,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -976,7 +976,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -989,7 +989,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1000,7 +1000,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1015,7 +1015,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1028,7 +1028,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1045,7 +1045,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1054,7 +1054,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1067,7 +1067,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1076,7 +1076,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1089,7 +1089,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1100,7 +1100,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1115,7 +1115,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1128,7 +1128,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1145,7 +1145,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1160,7 +1160,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1179,7 +1179,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1196,7 +1196,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1236,7 +1236,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1259,7 +1259,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1280,7 +1280,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1305,7 +1305,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1314,7 +1314,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1327,7 +1327,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1338,7 +1338,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1353,7 +1353,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1366,7 +1366,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1383,7 +1383,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1398,7 +1398,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1417,7 +1417,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1434,7 +1434,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1455,7 +1455,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1474,7 +1474,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1497,7 +1497,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1518,7 +1518,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1543,7 +1543,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1552,7 +1552,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1565,7 +1565,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1576,7 +1576,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1591,7 +1591,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1604,7 +1604,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1621,7 +1621,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1636,7 +1636,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1655,7 +1655,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1672,7 +1672,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1693,7 +1693,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1712,7 +1712,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1735,7 +1735,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1756,7 +1756,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1781,7 +1781,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1790,7 +1790,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1803,7 +1803,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1814,7 +1814,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1829,7 +1829,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1842,7 +1842,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1859,7 +1859,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1868,7 +1868,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1881,7 +1881,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1890,7 +1890,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1903,7 +1903,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1914,7 +1914,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1929,7 +1929,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1942,7 +1942,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1959,7 +1959,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1974,7 +1974,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1993,7 +1993,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2010,7 +2010,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2031,7 +2031,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2050,7 +2050,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2073,7 +2073,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2094,7 +2094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2119,7 +2119,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2128,7 +2128,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2141,7 +2141,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2152,7 +2152,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2167,7 +2167,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2180,7 +2180,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2197,7 +2197,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2212,7 +2212,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2231,7 +2231,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2248,7 +2248,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2269,7 +2269,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2288,7 +2288,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2311,7 +2311,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2332,7 +2332,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2357,7 +2357,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2366,7 +2366,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2379,7 +2379,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2390,7 +2390,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2405,7 +2405,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2418,7 +2418,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2435,7 +2435,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2444,7 +2444,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2457,7 +2457,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2466,7 +2466,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2479,7 +2479,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2490,7 +2490,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2505,7 +2505,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2518,7 +2518,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2535,7 +2535,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i32( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2550,7 +2550,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2569,7 +2569,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i32( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2586,7 +2586,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2607,7 +2607,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2626,7 +2626,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2649,7 +2649,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2670,7 +2670,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2695,7 +2695,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2704,7 +2704,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2717,7 +2717,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2728,7 +2728,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2743,7 +2743,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2756,7 +2756,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2773,7 +2773,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2782,7 +2782,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2795,7 +2795,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2804,7 +2804,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2817,7 +2817,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2828,7 +2828,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2843,7 +2843,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2856,7 +2856,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2873,7 +2873,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2888,7 +2888,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2907,7 +2907,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2924,7 +2924,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2945,7 +2945,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2964,7 +2964,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2987,7 +2987,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3008,7 +3008,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3033,7 +3033,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3042,7 +3042,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3055,7 +3055,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3066,7 +3066,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3081,7 +3081,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3094,7 +3094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3111,7 +3111,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3126,7 +3126,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3145,7 +3145,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3162,7 +3162,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3183,7 +3183,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3202,7 +3202,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3225,7 +3225,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3271,7 +3271,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3280,7 +3280,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3293,7 +3293,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3304,7 +3304,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3319,7 +3319,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3332,7 +3332,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3349,7 +3349,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3364,7 +3364,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3383,7 +3383,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3400,7 +3400,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3421,7 +3421,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3440,7 +3440,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3463,7 +3463,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3484,7 +3484,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3509,7 +3509,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3518,7 +3518,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3531,7 +3531,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3542,7 +3542,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3557,7 +3557,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3570,7 +3570,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3587,7 +3587,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3602,7 +3602,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3621,7 +3621,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3638,7 +3638,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3659,7 +3659,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3678,7 +3678,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3701,7 +3701,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3722,7 +3722,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3747,7 +3747,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3756,7 +3756,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3769,7 +3769,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3780,7 +3780,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3795,7 +3795,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3808,7 +3808,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3825,7 +3825,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3834,7 +3834,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3847,7 +3847,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3856,7 +3856,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3869,7 +3869,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3880,7 +3880,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3895,7 +3895,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3908,7 +3908,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3925,7 +3925,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3940,7 +3940,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3959,7 +3959,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3976,7 +3976,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3997,7 +3997,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4016,7 +4016,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4039,7 +4039,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4060,7 +4060,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4085,7 +4085,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4094,7 +4094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4118,7 +4118,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4133,7 +4133,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4146,7 +4146,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4163,7 +4163,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4178,7 +4178,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4197,7 +4197,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4214,7 +4214,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4235,7 +4235,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4254,7 +4254,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4277,7 +4277,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4298,7 +4298,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4323,7 +4323,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4332,7 +4332,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4345,7 +4345,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4356,7 +4356,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4371,7 +4371,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4384,7 +4384,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4401,7 +4401,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4416,7 +4416,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4435,7 +4435,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4452,7 +4452,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4473,7 +4473,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4492,7 +4492,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4515,7 +4515,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4536,7 +4536,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4561,7 +4561,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4570,7 +4570,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4583,7 +4583,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4594,7 +4594,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4609,7 +4609,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4622,7 +4622,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4639,7 +4639,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4648,7 +4648,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4661,7 +4661,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4670,7 +4670,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4683,7 +4683,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4694,7 +4694,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4709,7 +4709,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4722,7 +4722,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4739,7 +4739,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4754,7 +4754,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4773,7 +4773,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4790,7 +4790,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4811,7 +4811,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4830,7 +4830,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4853,7 +4853,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4874,7 +4874,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4899,7 +4899,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4908,7 +4908,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4921,7 +4921,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4932,7 +4932,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4947,7 +4947,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4960,7 +4960,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4977,7 +4977,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4992,7 +4992,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5011,7 +5011,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5028,7 +5028,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5049,7 +5049,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5068,7 +5068,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5091,7 +5091,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5112,7 +5112,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5137,7 +5137,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5146,7 +5146,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5159,7 +5159,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5170,7 +5170,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5185,7 +5185,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5198,7 +5198,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5215,7 +5215,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5224,7 +5224,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5237,7 +5237,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5246,7 +5246,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5259,7 +5259,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5270,7 +5270,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5285,7 +5285,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5298,7 +5298,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5315,7 +5315,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i32( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5330,7 +5330,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5349,7 +5349,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i32( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5366,7 +5366,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5387,7 +5387,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5406,7 +5406,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5429,7 +5429,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5450,7 +5450,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5475,7 +5475,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5484,7 +5484,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5497,7 +5497,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5508,7 +5508,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5523,7 +5523,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5536,7 +5536,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5553,7 +5553,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5562,7 +5562,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5575,7 +5575,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5584,7 +5584,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5597,7 +5597,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5608,7 +5608,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5623,7 +5623,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5636,7 +5636,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5653,7 +5653,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f32.i32( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5668,7 +5668,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5687,7 +5687,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f32.i32( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5704,7 +5704,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5725,7 +5725,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f32.i32( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5744,7 +5744,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5767,7 +5767,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f32.i32( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5788,7 +5788,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5813,7 +5813,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5822,7 +5822,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5835,7 +5835,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5846,7 +5846,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5861,7 +5861,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5874,7 +5874,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5891,7 +5891,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f32.i32( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5906,7 +5906,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5925,7 +5925,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f32.i32( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5942,7 +5942,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5963,7 +5963,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f32.i32( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5982,7 +5982,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6005,7 +6005,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f32.i32( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6026,7 +6026,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6051,7 +6051,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6060,7 +6060,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6073,7 +6073,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6084,7 +6084,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6099,7 +6099,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6112,7 +6112,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6129,7 +6129,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6138,7 +6138,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6151,7 +6151,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6160,7 +6160,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6173,7 +6173,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f64.i32( undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6184,7 +6184,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6199,7 +6199,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f64.i32( undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6212,7 +6212,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6229,7 +6229,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f64.i32( undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6244,7 +6244,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6263,7 +6263,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f64.i32( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6280,7 +6280,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6301,7 +6301,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f64.i32( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6320,7 +6320,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6343,7 +6343,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f64.i32( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6364,7 +6364,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6389,7 +6389,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6398,7 +6398,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6411,7 +6411,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f64.i32( undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6422,7 +6422,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6437,7 +6437,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f64.i32( undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6450,7 +6450,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6467,7 +6467,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6476,7 +6476,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6489,7 +6489,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6498,7 +6498,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6511,7 +6511,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6522,7 +6522,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6537,7 +6537,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6550,7 +6550,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6567,7 +6567,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6582,7 +6582,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6601,7 +6601,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6618,7 +6618,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6639,7 +6639,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6658,7 +6658,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6681,7 +6681,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6702,7 +6702,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6727,7 +6727,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6736,7 +6736,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6749,7 +6749,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6760,7 +6760,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6775,7 +6775,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6788,7 +6788,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6805,7 +6805,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6820,7 +6820,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6839,7 +6839,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6856,7 +6856,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6877,7 +6877,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6896,7 +6896,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6919,7 +6919,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6940,7 +6940,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6965,7 +6965,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6974,7 +6974,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6987,7 +6987,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6998,7 +6998,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7013,7 +7013,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7026,7 +7026,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7043,7 +7043,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7058,7 +7058,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7077,7 +7077,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7094,7 +7094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7115,7 +7115,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7134,7 +7134,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7157,7 +7157,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7178,7 +7178,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7203,7 +7203,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7212,7 +7212,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7225,7 +7225,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7236,7 +7236,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7251,7 +7251,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7264,7 +7264,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7281,7 +7281,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16_v_f16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7290,7 +7290,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c @@ -15,7 +15,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -26,7 +26,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -41,7 +41,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -54,7 +54,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -71,7 +71,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -86,7 +86,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -105,7 +105,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -122,7 +122,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -143,7 +143,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -162,7 +162,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -185,7 +185,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -206,7 +206,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -231,7 +231,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_i8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -254,7 +254,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -281,7 +281,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -292,7 +292,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -307,7 +307,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -320,7 +320,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -337,7 +337,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -352,7 +352,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -371,7 +371,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -388,7 +388,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -409,7 +409,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -428,7 +428,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -451,7 +451,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -472,7 +472,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -497,7 +497,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_i8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -520,7 +520,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -547,7 +547,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -558,7 +558,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -573,7 +573,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -586,7 +586,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -603,7 +603,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -618,7 +618,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -637,7 +637,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -654,7 +654,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -675,7 +675,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -694,7 +694,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -717,7 +717,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -738,7 +738,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -763,7 +763,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_i8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -786,7 +786,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -813,7 +813,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -824,7 +824,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -839,7 +839,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -852,7 +852,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -869,7 +869,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -884,7 +884,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -903,7 +903,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv8i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -920,7 +920,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -941,7 +941,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -960,7 +960,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -983,7 +983,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -1004,7 +1004,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -1029,7 +1029,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_i8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -1052,7 +1052,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -1079,7 +1079,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -1090,7 +1090,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -1105,7 +1105,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv16i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -1118,7 +1118,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -1135,7 +1135,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_i8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv16i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -1150,7 +1150,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -1169,7 +1169,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv32i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -1180,7 +1180,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -1195,7 +1195,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -1206,7 +1206,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -1221,7 +1221,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -1251,7 +1251,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -1266,7 +1266,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -1285,7 +1285,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -1302,7 +1302,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -1323,7 +1323,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -1342,7 +1342,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -1365,7 +1365,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -1386,7 +1386,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -1411,7 +1411,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_i16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -1434,7 +1434,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -1461,7 +1461,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -1472,7 +1472,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -1487,7 +1487,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -1500,7 +1500,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -1532,7 +1532,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -1551,7 +1551,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -1568,7 +1568,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -1589,7 +1589,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -1608,7 +1608,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -1631,7 +1631,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -1652,7 +1652,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -1677,7 +1677,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_i16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -1700,7 +1700,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -1727,7 +1727,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -1738,7 +1738,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -1753,7 +1753,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -1766,7 +1766,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -1783,7 +1783,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -1798,7 +1798,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -1817,7 +1817,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -1834,7 +1834,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -1855,7 +1855,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -1874,7 +1874,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -1897,7 +1897,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -1918,7 +1918,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -1943,7 +1943,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_i16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -1966,7 +1966,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -1993,7 +1993,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2004,7 +2004,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2019,7 +2019,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -2032,7 +2032,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -2049,7 +2049,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_i16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -2064,7 +2064,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -2083,7 +2083,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_i16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2094,7 +2094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2109,7 +2109,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2120,7 +2120,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2135,7 +2135,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -2148,7 +2148,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -2165,7 +2165,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -2180,7 +2180,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -2199,7 +2199,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -2216,7 +2216,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -2237,7 +2237,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -2256,7 +2256,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -2279,7 +2279,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -2300,7 +2300,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -2325,7 +2325,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_i32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -2348,7 +2348,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -2375,7 +2375,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2386,7 +2386,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2401,7 +2401,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -2414,7 +2414,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -2431,7 +2431,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -2446,7 +2446,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -2465,7 +2465,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -2482,7 +2482,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -2503,7 +2503,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -2522,7 +2522,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -2545,7 +2545,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -2566,7 +2566,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -2591,7 +2591,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_i32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -2614,7 +2614,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -2641,7 +2641,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2652,7 +2652,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2667,7 +2667,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -2680,7 +2680,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -2697,7 +2697,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_i32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -2712,7 +2712,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -2731,7 +2731,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_i32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2742,7 +2742,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2757,7 +2757,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -2768,7 +2768,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -2783,7 +2783,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -2796,7 +2796,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -2813,7 +2813,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -2828,7 +2828,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -2847,7 +2847,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i64.i32( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -2864,7 +2864,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -2885,7 +2885,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -2904,7 +2904,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -2927,7 +2927,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -2948,7 +2948,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -2973,7 +2973,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64ff_v_i64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -2996,7 +2996,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64ff_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -3023,7 +3023,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3034,7 +3034,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3049,7 +3049,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -3062,7 +3062,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -3079,7 +3079,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_i64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -3094,7 +3094,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -3113,7 +3113,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_i64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3124,7 +3124,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3139,7 +3139,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3150,7 +3150,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3165,7 +3165,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -3178,7 +3178,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -3195,7 +3195,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -3210,7 +3210,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -3229,7 +3229,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -3267,7 +3267,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -3286,7 +3286,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -3309,7 +3309,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -3330,7 +3330,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -3355,7 +3355,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_u8mf8( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -3378,7 +3378,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -3405,7 +3405,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3416,7 +3416,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3431,7 +3431,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -3444,7 +3444,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -3461,7 +3461,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -3476,7 +3476,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -3495,7 +3495,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -3512,7 +3512,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -3533,7 +3533,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -3552,7 +3552,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -3575,7 +3575,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -3596,7 +3596,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -3621,7 +3621,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_u8mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -3644,7 +3644,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -3671,7 +3671,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3682,7 +3682,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3697,7 +3697,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -3710,7 +3710,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -3727,7 +3727,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -3742,7 +3742,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -3761,7 +3761,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -3778,7 +3778,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -3799,7 +3799,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -3818,7 +3818,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -3841,7 +3841,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -3862,7 +3862,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -3887,7 +3887,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_u8mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -3910,7 +3910,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -3937,7 +3937,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -3948,7 +3948,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -3963,7 +3963,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -3976,7 +3976,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -3993,7 +3993,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -4008,7 +4008,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -4027,7 +4027,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv8i8.i32( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -4044,7 +4044,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -4065,7 +4065,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -4128,7 +4128,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -4153,7 +4153,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e8ff_v_u8m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv8i8.i32( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -4176,7 +4176,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e8ff_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -4203,7 +4203,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -4214,7 +4214,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -4229,7 +4229,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e8ff_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv16i8.i32( undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -4242,7 +4242,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e8ff_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -4259,7 +4259,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e8ff_v_u8m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv16i8.i32( undef, undef, undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -4274,7 +4274,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e8ff_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -4293,7 +4293,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e8ff_v_u8m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv32i8.i32( undef, undef, i8* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -4304,7 +4304,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e8ff_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -4319,7 +4319,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -4330,7 +4330,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -4345,7 +4345,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -4358,7 +4358,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -4375,7 +4375,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -4390,7 +4390,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -4409,7 +4409,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -4426,7 +4426,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -4447,7 +4447,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -4466,7 +4466,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -4489,7 +4489,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -4510,7 +4510,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -4535,7 +4535,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_u16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -4558,7 +4558,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -4585,7 +4585,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -4596,7 +4596,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -4611,7 +4611,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -4624,7 +4624,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -4641,7 +4641,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -4656,7 +4656,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -4675,7 +4675,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -4692,7 +4692,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -4713,7 +4713,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -4732,7 +4732,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -4755,7 +4755,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -4776,7 +4776,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -4801,7 +4801,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_u16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -4824,7 +4824,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -4851,7 +4851,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -4862,7 +4862,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -4877,7 +4877,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -4890,7 +4890,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -4907,7 +4907,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -4922,7 +4922,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -4941,7 +4941,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4i16.i32( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -4958,7 +4958,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -4979,7 +4979,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -4998,7 +4998,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -5021,7 +5021,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -5042,7 +5042,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -5067,7 +5067,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_u16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4i16.i32( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -5090,7 +5090,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -5117,7 +5117,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5128,7 +5128,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5143,7 +5143,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8i16.i32( undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -5156,7 +5156,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -5173,7 +5173,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_u16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8i16.i32( undef, undef, undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -5188,7 +5188,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -5207,7 +5207,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_u16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16i16.i32( undef, undef, i16* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5218,7 +5218,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5233,7 +5233,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5244,7 +5244,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5259,7 +5259,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -5272,7 +5272,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -5289,7 +5289,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -5304,7 +5304,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -5323,7 +5323,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -5340,7 +5340,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -5361,7 +5361,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -5380,7 +5380,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -5403,7 +5403,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -5424,7 +5424,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -5449,7 +5449,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_u32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -5472,7 +5472,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -5499,7 +5499,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5510,7 +5510,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5525,7 +5525,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -5538,7 +5538,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -5555,7 +5555,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -5570,7 +5570,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -5589,7 +5589,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2i32.i32( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -5606,7 +5606,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -5627,7 +5627,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -5646,7 +5646,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -5669,7 +5669,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -5690,7 +5690,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -5715,7 +5715,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_u32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2i32.i32( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -5738,7 +5738,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -5765,7 +5765,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5776,7 +5776,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5791,7 +5791,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4i32.i32( undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -5804,7 +5804,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -5821,7 +5821,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_u32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4i32.i32( undef, undef, undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -5836,7 +5836,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -5855,7 +5855,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8i32.i32( undef, undef, i32* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5866,7 +5866,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5881,7 +5881,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -5892,7 +5892,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -5907,7 +5907,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -5920,7 +5920,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -5937,7 +5937,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -5952,7 +5952,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -5971,7 +5971,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1i64.i32( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -5988,7 +5988,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -6009,7 +6009,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -6028,7 +6028,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -6051,7 +6051,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -6072,7 +6072,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -6097,7 +6097,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64ff_v_u64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1i64.i32( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -6120,7 +6120,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64ff_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -6147,7 +6147,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6158,7 +6158,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6173,7 +6173,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2i64.i32( undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -6186,7 +6186,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -6203,7 +6203,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_u64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2i64.i32( undef, undef, undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -6218,7 +6218,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -6237,7 +6237,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_u64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4i64.i32( undef, undef, i64* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6248,7 +6248,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6263,7 +6263,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6274,7 +6274,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6289,7 +6289,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -6302,7 +6302,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -6319,7 +6319,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -6334,7 +6334,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -6353,7 +6353,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f32.i32( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -6370,7 +6370,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -6391,7 +6391,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f32.i32( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -6410,7 +6410,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -6433,7 +6433,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f32.i32( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -6454,7 +6454,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -6479,7 +6479,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_f32mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f32.i32( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -6502,7 +6502,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -6529,7 +6529,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6540,7 +6540,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6555,7 +6555,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -6568,7 +6568,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -6585,7 +6585,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -6600,7 +6600,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -6619,7 +6619,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2f32.i32( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -6636,7 +6636,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -6657,7 +6657,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2f32.i32( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -6676,7 +6676,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -6699,7 +6699,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2f32.i32( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -6720,7 +6720,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -6745,7 +6745,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e32ff_v_f32m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2f32.i32( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -6768,7 +6768,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e32ff_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -6795,7 +6795,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6806,7 +6806,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6821,7 +6821,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e32ff_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4f32.i32( undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -6834,7 +6834,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e32ff_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -6851,7 +6851,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e32ff_v_f32m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4f32.i32( undef, undef, undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -6866,7 +6866,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e32ff_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -6885,7 +6885,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e32ff_v_f32m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8f32.i32( undef, undef, float* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6896,7 +6896,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e32ff_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6911,7 +6911,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -6922,7 +6922,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -6937,7 +6937,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f64.i32( undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -6950,7 +6950,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -6967,7 +6967,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f64.i32( undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -6982,7 +6982,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -7001,7 +7001,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f64.i32( undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -7018,7 +7018,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -7039,7 +7039,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f64.i32( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -7058,7 +7058,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -7081,7 +7081,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f64.i32( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -7102,7 +7102,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -7127,7 +7127,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e64ff_v_f64m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f64.i32( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -7150,7 +7150,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e64ff_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -7177,7 +7177,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -7188,7 +7188,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -7203,7 +7203,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e64ff_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f64.i32( undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -7216,7 +7216,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e64ff_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -7233,7 +7233,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e64ff_v_f64m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f64.i32( undef, undef, undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -7248,7 +7248,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e64ff_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -7267,7 +7267,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e64ff_v_f64m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f64.i32( undef, undef, double* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -7278,7 +7278,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e64ff_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -7293,7 +7293,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv1f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -7304,7 +7304,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -7319,7 +7319,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv1f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -7332,7 +7332,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -7349,7 +7349,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv1f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -7364,7 +7364,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -7383,7 +7383,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv1f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -7400,7 +7400,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -7421,7 +7421,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv1f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -7440,7 +7440,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -7463,7 +7463,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv1f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -7484,7 +7484,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -7509,7 +7509,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_f16mf4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv1f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -7532,7 +7532,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -7559,7 +7559,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv2f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -7570,7 +7570,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -7585,7 +7585,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv2f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -7598,7 +7598,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -7615,7 +7615,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv2f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -7630,7 +7630,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -7649,7 +7649,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv2f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -7666,7 +7666,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -7687,7 +7687,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv2f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -7706,7 +7706,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -7729,7 +7729,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv2f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -7750,7 +7750,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -7775,7 +7775,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_f16mf2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv2f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -7798,7 +7798,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -7825,7 +7825,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv4f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -7836,7 +7836,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -7851,7 +7851,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv4f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -7864,7 +7864,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -7881,7 +7881,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv4f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -7896,7 +7896,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -7915,7 +7915,7 @@ // CHECK-RV32-LABEL: @test_vlseg5e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , i32 } @llvm.riscv.vlseg5ff.nxv4f16.i32( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i32 } [[TMP0]], 1 @@ -7932,7 +7932,7 @@ // // CHECK-RV64-LABEL: @test_vlseg5e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 @@ -7953,7 +7953,7 @@ // CHECK-RV32-LABEL: @test_vlseg6e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , i32 } @llvm.riscv.vlseg6ff.nxv4f16.i32( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i32 } [[TMP0]], 1 @@ -7972,7 +7972,7 @@ // // CHECK-RV64-LABEL: @test_vlseg6e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 @@ -7995,7 +7995,7 @@ // CHECK-RV32-LABEL: @test_vlseg7e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , i32 } @llvm.riscv.vlseg7ff.nxv4f16.i32( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i32 } [[TMP0]], 1 @@ -8016,7 +8016,7 @@ // // CHECK-RV64-LABEL: @test_vlseg7e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 @@ -8041,7 +8041,7 @@ // CHECK-RV32-LABEL: @test_vlseg8e16ff_v_f16m1( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i32 } @llvm.riscv.vlseg8ff.nxv4f16.i32( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i32 } [[TMP0]], 1 @@ -8064,7 +8064,7 @@ // // CHECK-RV64-LABEL: @test_vlseg8e16ff_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 @@ -8091,7 +8091,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv8f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -8102,7 +8102,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 @@ -8117,7 +8117,7 @@ // CHECK-RV32-LABEL: @test_vlseg3e16ff_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , i32 } @llvm.riscv.vlseg3ff.nxv8f16.i32( undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , i32 } [[TMP0]], 1 @@ -8130,7 +8130,7 @@ // // CHECK-RV64-LABEL: @test_vlseg3e16ff_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 @@ -8147,7 +8147,7 @@ // CHECK-RV32-LABEL: @test_vlseg4e16ff_v_f16m2( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , , , i32 } @llvm.riscv.vlseg4ff.nxv8f16.i32( undef, undef, undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i32 } [[TMP0]], 1 @@ -8162,7 +8162,7 @@ // // CHECK-RV64-LABEL: @test_vlseg4e16ff_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 @@ -8181,7 +8181,7 @@ // CHECK-RV32-LABEL: @test_vlseg2e16ff_v_f16m4( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16f16.i32(half* [[BASE:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.nxv16f16.i32( undef, undef, half* [[BASE:%.*]], i32 [[VL:%.*]]) // CHECK-RV32-NEXT: [[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0 // CHECK-RV32-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV32-NEXT: [[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1 @@ -8192,7 +8192,7 @@ // // CHECK-RV64-LABEL: @test_vlseg2e16ff_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16f16.i64(half* [[BASE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -206,7 +206,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -227,7 +227,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -250,7 +250,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -288,7 +288,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -303,7 +303,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -320,7 +320,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -339,7 +339,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -360,7 +360,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -383,7 +383,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -408,7 +408,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -421,7 +421,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -453,7 +453,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -472,7 +472,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -493,7 +493,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -516,7 +516,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -541,7 +541,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -554,7 +554,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -586,7 +586,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -599,7 +599,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -612,7 +612,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -627,7 +627,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -644,7 +644,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -663,7 +663,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -684,7 +684,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -707,7 +707,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -732,7 +732,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -745,7 +745,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -760,7 +760,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -777,7 +777,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -796,7 +796,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -817,7 +817,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -840,7 +840,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -865,7 +865,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -878,7 +878,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -893,7 +893,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -910,7 +910,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -929,7 +929,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -950,7 +950,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -973,7 +973,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -998,7 +998,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1011,7 +1011,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1026,7 +1026,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1043,7 +1043,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1056,7 +1056,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1069,7 +1069,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1084,7 +1084,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1101,7 +1101,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1120,7 +1120,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1141,7 +1141,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1164,7 +1164,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1189,7 +1189,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1202,7 +1202,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1253,7 +1253,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1274,7 +1274,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1297,7 +1297,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1322,7 +1322,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1335,7 +1335,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1350,7 +1350,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1367,7 +1367,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1380,7 +1380,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1393,7 +1393,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1408,7 +1408,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1425,7 +1425,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1444,7 +1444,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1465,7 +1465,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1488,7 +1488,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1513,7 +1513,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1526,7 +1526,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1541,7 +1541,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1558,7 +1558,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1571,7 +1571,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1584,7 +1584,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1599,7 +1599,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1616,7 +1616,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1635,7 +1635,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1656,7 +1656,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1679,7 +1679,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1704,7 +1704,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1717,7 +1717,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1732,7 +1732,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1749,7 +1749,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1768,7 +1768,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1789,7 +1789,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1812,7 +1812,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1837,7 +1837,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1850,7 +1850,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1865,7 +1865,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1882,7 +1882,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1901,7 +1901,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1922,7 +1922,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1945,7 +1945,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1970,7 +1970,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1983,7 +1983,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1998,7 +1998,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2015,7 +2015,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2034,7 +2034,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2055,7 +2055,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2078,7 +2078,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2103,7 +2103,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2116,7 +2116,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2131,7 +2131,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2148,7 +2148,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2161,7 +2161,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2174,7 +2174,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2189,7 +2189,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2206,7 +2206,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2225,7 +2225,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2246,7 +2246,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2269,7 +2269,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2294,7 +2294,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2307,7 +2307,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2322,7 +2322,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2339,7 +2339,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2358,7 +2358,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2379,7 +2379,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2402,7 +2402,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2427,7 +2427,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2440,7 +2440,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2455,7 +2455,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2472,7 +2472,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2491,7 +2491,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2512,7 +2512,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2535,7 +2535,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2560,7 +2560,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2573,7 +2573,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2588,7 +2588,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2605,7 +2605,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2618,7 +2618,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2631,7 +2631,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2646,7 +2646,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2663,7 +2663,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2682,7 +2682,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2703,7 +2703,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2726,7 +2726,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2751,7 +2751,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2764,7 +2764,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2779,7 +2779,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2796,7 +2796,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2815,7 +2815,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2836,7 +2836,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2859,7 +2859,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2884,7 +2884,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2897,7 +2897,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2912,7 +2912,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2929,7 +2929,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2942,7 +2942,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2955,7 +2955,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2970,7 +2970,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2987,7 +2987,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3006,7 +3006,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3027,7 +3027,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3050,7 +3050,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3075,7 +3075,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3088,7 +3088,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3103,7 +3103,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3120,7 +3120,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3133,7 +3133,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3146,7 +3146,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3161,7 +3161,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3178,7 +3178,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3197,7 +3197,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3218,7 +3218,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3241,7 +3241,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3266,7 +3266,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3279,7 +3279,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3294,7 +3294,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3311,7 +3311,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2f32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3330,7 +3330,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2f32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3351,7 +3351,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3374,7 +3374,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2f32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3399,7 +3399,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3412,7 +3412,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4f32.i64( undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3427,7 +3427,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4f32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3444,7 +3444,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8f32.i64(float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8f32.i64( undef, undef, float* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3457,7 +3457,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3470,7 +3470,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3485,7 +3485,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3502,7 +3502,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3521,7 +3521,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3542,7 +3542,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3565,7 +3565,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3590,7 +3590,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3603,7 +3603,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f64.i64( undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3618,7 +3618,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3635,7 +3635,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f64.i64(double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f64.i64( undef, undef, double* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7287,7 +7287,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7300,7 +7300,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7315,7 +7315,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7332,7 +7332,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7351,7 +7351,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7372,7 +7372,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7395,7 +7395,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7420,7 +7420,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7433,7 +7433,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7448,7 +7448,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7465,7 +7465,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7484,7 +7484,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7505,7 +7505,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7528,7 +7528,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7553,7 +7553,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7566,7 +7566,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7581,7 +7581,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7598,7 +7598,7 @@ // CHECK-RV64-LABEL: @test_vlsseg5e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4f16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7617,7 +7617,7 @@ // CHECK-RV64-LABEL: @test_vlsseg6e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4f16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7638,7 +7638,7 @@ // CHECK-RV64-LABEL: @test_vlsseg7e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7661,7 +7661,7 @@ // CHECK-RV64-LABEL: @test_vlsseg8e16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4f16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7686,7 +7686,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7699,7 +7699,7 @@ // CHECK-RV64-LABEL: @test_vlsseg3e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8f16.i64( undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7714,7 +7714,7 @@ // CHECK-RV64-LABEL: @test_vlsseg4e16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8f16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7731,7 +7731,7 @@ // CHECK-RV64-LABEL: @test_vlsseg2e16_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16f16.i64(half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16f16.i64( undef, undef, half* [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -200,7 +200,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -213,7 +213,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -228,7 +228,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -245,7 +245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -264,7 +264,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -285,7 +285,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -308,7 +308,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -333,7 +333,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -346,7 +346,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -361,7 +361,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -378,7 +378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -391,7 +391,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -404,7 +404,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -419,7 +419,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -455,7 +455,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -476,7 +476,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -499,7 +499,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -524,7 +524,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -537,7 +537,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -552,7 +552,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -582,7 +582,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -597,7 +597,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -614,7 +614,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -633,7 +633,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -654,7 +654,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -677,7 +677,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -715,7 +715,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -730,7 +730,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -747,7 +747,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -766,7 +766,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -787,7 +787,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -810,7 +810,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -848,7 +848,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -863,7 +863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -880,7 +880,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -893,7 +893,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -906,7 +906,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -921,7 +921,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -938,7 +938,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -957,7 +957,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -978,7 +978,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1001,7 +1001,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1026,7 +1026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1039,7 +1039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1054,7 +1054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1071,7 +1071,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1084,7 +1084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1097,7 +1097,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1112,7 +1112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1129,7 +1129,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1148,7 +1148,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1169,7 +1169,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1192,7 +1192,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1217,7 +1217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1230,7 +1230,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1245,7 +1245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1262,7 +1262,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1275,7 +1275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1288,7 +1288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1303,7 +1303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1320,7 +1320,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1360,7 +1360,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1383,7 +1383,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1408,7 +1408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1421,7 +1421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1436,7 +1436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1453,7 +1453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1466,7 +1466,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1481,7 +1481,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1498,7 +1498,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1538,7 +1538,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1561,7 +1561,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1586,7 +1586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1599,7 +1599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1614,7 +1614,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1631,7 +1631,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1644,7 +1644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1657,7 +1657,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1672,7 +1672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1689,7 +1689,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1708,7 +1708,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1729,7 +1729,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1752,7 +1752,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1777,7 +1777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1790,7 +1790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1805,7 +1805,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1822,7 +1822,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1835,7 +1835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1848,7 +1848,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1863,7 +1863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1880,7 +1880,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1920,7 +1920,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1943,7 +1943,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1968,7 +1968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1981,7 +1981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1996,7 +1996,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2013,7 +2013,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2026,7 +2026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2039,7 +2039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2054,7 +2054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2071,7 +2071,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2090,7 +2090,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2111,7 +2111,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2134,7 +2134,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2159,7 +2159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2172,7 +2172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2187,7 +2187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2204,7 +2204,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2217,7 +2217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2230,7 +2230,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2262,7 +2262,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2281,7 +2281,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2302,7 +2302,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2325,7 +2325,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2350,7 +2350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2363,7 +2363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2395,7 +2395,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2408,7 +2408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2421,7 +2421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2436,7 +2436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2453,7 +2453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2472,7 +2472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2493,7 +2493,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2516,7 +2516,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2541,7 +2541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2554,7 +2554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2569,7 +2569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2586,7 +2586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2599,7 +2599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2612,7 +2612,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2627,7 +2627,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2663,7 +2663,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2684,7 +2684,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2707,7 +2707,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2732,7 +2732,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2745,7 +2745,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2760,7 +2760,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2790,7 +2790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2803,7 +2803,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2818,7 +2818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2835,7 +2835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2854,7 +2854,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2875,7 +2875,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2898,7 +2898,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2923,7 +2923,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2936,7 +2936,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2951,7 +2951,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2968,7 +2968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2981,7 +2981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2994,7 +2994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3009,7 +3009,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3026,7 +3026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3045,7 +3045,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3066,7 +3066,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3089,7 +3089,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3114,7 +3114,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3127,7 +3127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3142,7 +3142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3159,7 +3159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3172,7 +3172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3185,7 +3185,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3200,7 +3200,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3217,7 +3217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3236,7 +3236,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3257,7 +3257,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3280,7 +3280,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3305,7 +3305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3318,7 +3318,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3333,7 +3333,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3350,7 +3350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv32i8.nxv32i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3363,7 +3363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3376,7 +3376,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3391,7 +3391,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3408,7 +3408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3427,7 +3427,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3448,7 +3448,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3471,7 +3471,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3496,7 +3496,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i8.nxv16i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3509,7 +3509,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv16i8.nxv16i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3524,7 +3524,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv16i8.nxv16i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3541,7 +3541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i8.nxv8i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3554,7 +3554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i8.nxv8i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3569,7 +3569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3586,7 +3586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3605,7 +3605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3626,7 +3626,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3649,7 +3649,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv8i8.nxv8i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3674,7 +3674,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3687,7 +3687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3702,7 +3702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3719,7 +3719,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3738,7 +3738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3759,7 +3759,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3782,7 +3782,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3807,7 +3807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3820,7 +3820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3835,7 +3835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3852,7 +3852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3865,7 +3865,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3878,7 +3878,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3893,7 +3893,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3910,7 +3910,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3929,7 +3929,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3950,7 +3950,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3973,7 +3973,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3998,7 +3998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4011,7 +4011,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4026,7 +4026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4043,7 +4043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4056,7 +4056,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4069,7 +4069,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4101,7 +4101,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4120,7 +4120,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4141,7 +4141,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4164,7 +4164,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4189,7 +4189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4202,7 +4202,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4234,7 +4234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16i16.nxv16i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4247,7 +4247,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i16.nxv4i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4260,7 +4260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i16.nxv4i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4275,7 +4275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4292,7 +4292,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4311,7 +4311,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4332,7 +4332,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4355,7 +4355,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4380,7 +4380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i16.nxv8i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4393,7 +4393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8i16.nxv8i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4408,7 +4408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8i16.nxv8i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4425,7 +4425,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4438,7 +4438,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4453,7 +4453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4470,7 +4470,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4489,7 +4489,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4510,7 +4510,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4533,7 +4533,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4558,7 +4558,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4571,7 +4571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4586,7 +4586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4603,7 +4603,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4629,7 +4629,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4644,7 +4644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4661,7 +4661,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4680,7 +4680,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4701,7 +4701,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4724,7 +4724,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4762,7 +4762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4777,7 +4777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4794,7 +4794,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4807,7 +4807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4820,7 +4820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4835,7 +4835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4852,7 +4852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4871,7 +4871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4892,7 +4892,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4915,7 +4915,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4940,7 +4940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4953,7 +4953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4968,7 +4968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4985,7 +4985,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4998,7 +4998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i32.nxv2i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5011,7 +5011,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i32.nxv2i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5026,7 +5026,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5043,7 +5043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5062,7 +5062,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5083,7 +5083,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5106,7 +5106,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5131,7 +5131,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i32.nxv4i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5144,7 +5144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i32.nxv4i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5159,7 +5159,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i32.nxv4i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5176,7 +5176,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8i32.nxv8i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5189,7 +5189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5202,7 +5202,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5217,7 +5217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5234,7 +5234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5253,7 +5253,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5274,7 +5274,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5297,7 +5297,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5322,7 +5322,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5335,7 +5335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i8.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5350,7 +5350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i8.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5367,7 +5367,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i8.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5380,7 +5380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5408,7 +5408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5425,7 +5425,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5444,7 +5444,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5465,7 +5465,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5488,7 +5488,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5513,7 +5513,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i16.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5541,7 +5541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i16.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5558,7 +5558,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i16.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5571,7 +5571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5584,7 +5584,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5599,7 +5599,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5616,7 +5616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5635,7 +5635,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5656,7 +5656,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5679,7 +5679,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5704,7 +5704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5717,7 +5717,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i32.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5732,7 +5732,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i32.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5749,7 +5749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i32.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5762,7 +5762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i64.nxv1i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5775,7 +5775,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i64.nxv1i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5790,7 +5790,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5807,7 +5807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5826,7 +5826,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5847,7 +5847,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5870,7 +5870,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5895,7 +5895,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i64.nxv2i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5908,7 +5908,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i64.nxv2i64.i64( undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5923,7 +5923,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i64.nxv2i64.i64( undef, undef, undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5940,7 +5940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64(i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i64.nxv4i64.i64( undef, undef, i64* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5953,7 +5953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5966,7 +5966,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5981,7 +5981,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5998,7 +5998,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6017,7 +6017,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6038,7 +6038,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6061,7 +6061,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6086,7 +6086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6099,7 +6099,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6114,7 +6114,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6131,7 +6131,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6144,7 +6144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6157,7 +6157,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6189,7 +6189,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6208,7 +6208,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6229,7 +6229,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6252,7 +6252,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6277,7 +6277,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6290,7 +6290,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6322,7 +6322,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6335,7 +6335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6348,7 +6348,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6363,7 +6363,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6380,7 +6380,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6399,7 +6399,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6420,7 +6420,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6443,7 +6443,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6468,7 +6468,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6481,7 +6481,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6496,7 +6496,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6513,7 +6513,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f32.nxv2i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f32.nxv2i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f32.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f32.nxv4i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f32.nxv4i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f32.nxv4i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f32.nxv8i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6717,7 +6717,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6730,7 +6730,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6745,7 +6745,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6762,7 +6762,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6781,7 +6781,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6802,7 +6802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6825,7 +6825,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6850,7 +6850,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6863,7 +6863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i8.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6878,7 +6878,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i8.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6895,7 +6895,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i8.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i8.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6908,7 +6908,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6921,7 +6921,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6936,7 +6936,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6953,7 +6953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6972,7 +6972,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6993,7 +6993,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7016,7 +7016,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7041,7 +7041,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7054,7 +7054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i16.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7069,7 +7069,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i16.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7086,7 +7086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i16.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i16.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7099,7 +7099,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7112,7 +7112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7127,7 +7127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7144,7 +7144,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7163,7 +7163,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7184,7 +7184,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7207,7 +7207,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7232,7 +7232,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7245,7 +7245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i32.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7260,7 +7260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i32.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7277,7 +7277,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i32.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i32.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7290,7 +7290,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f64.nxv1i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7303,7 +7303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f64.nxv1i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7318,7 +7318,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7335,7 +7335,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7354,7 +7354,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7375,7 +7375,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7398,7 +7398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f64.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7423,7 +7423,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f64.nxv2i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7436,7 +7436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f64.nxv2i64.i64( undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7451,7 +7451,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f64m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f64.nxv2i64.i64( undef, undef, undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7468,7 +7468,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f64m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i64.i64(double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f64.nxv4i64.i64( undef, undef, double* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 8 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c @@ -7481,7 +7481,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7494,7 +7494,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7509,7 +7509,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7526,7 +7526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7545,7 +7545,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7566,7 +7566,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7589,7 +7589,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7614,7 +7614,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7627,7 +7627,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7642,7 +7642,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7659,7 +7659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7672,7 +7672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7685,7 +7685,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7700,7 +7700,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7717,7 +7717,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7736,7 +7736,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7757,7 +7757,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7780,7 +7780,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7805,7 +7805,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7818,7 +7818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7833,7 +7833,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7850,7 +7850,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7863,7 +7863,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7876,7 +7876,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7891,7 +7891,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7908,7 +7908,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7927,7 +7927,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7948,7 +7948,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7971,7 +7971,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7996,7 +7996,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8009,7 +8009,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8024,7 +8024,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -8041,7 +8041,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f16m4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16f16.nxv16i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8054,7 +8054,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4f16.nxv4i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8067,7 +8067,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4f16.nxv4i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8082,7 +8082,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -8099,7 +8099,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -8118,7 +8118,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -8139,7 +8139,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -8162,7 +8162,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4f16.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -8187,7 +8187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8f16.nxv8i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -8200,7 +8200,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8f16.nxv8i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -8215,7 +8215,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f16m2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8f16.nxv8i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c @@ -6912,7 +6912,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6925,7 +6925,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6940,7 +6940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6957,7 +6957,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6976,7 +6976,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6997,7 +6997,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7020,7 +7020,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7045,7 +7045,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i8.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7058,7 +7058,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i8.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7073,7 +7073,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7090,7 +7090,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7109,7 +7109,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7130,7 +7130,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7153,7 +7153,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i8.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7178,7 +7178,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7191,7 +7191,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7206,7 +7206,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7223,7 +7223,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7242,7 +7242,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7263,7 +7263,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7286,7 +7286,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7311,7 +7311,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i16.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7324,7 +7324,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i16.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7339,7 +7339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7356,7 +7356,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7375,7 +7375,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7396,7 +7396,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7419,7 +7419,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i16.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7444,7 +7444,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7457,7 +7457,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7472,7 +7472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7489,7 +7489,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7508,7 +7508,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7529,7 +7529,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7552,7 +7552,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7577,7 +7577,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i32.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7590,7 +7590,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i32.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7605,7 +7605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7622,7 +7622,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7641,7 +7641,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7662,7 +7662,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7685,7 +7685,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i32.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7710,7 +7710,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f16.nxv1i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7723,7 +7723,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f16.nxv1i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7738,7 +7738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7755,7 +7755,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7774,7 +7774,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7795,7 +7795,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7818,7 +7818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -7843,7 +7843,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2f16.nxv2i64.i64( undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -7856,7 +7856,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2f16.nxv2i64.i64( undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -7871,7 +7871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -7888,7 +7888,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -7907,7 +7907,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -7928,7 +7928,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -7951,7 +7951,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i64.i64(half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2f16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, half* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c @@ -9,7 +9,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -22,7 +22,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -37,7 +37,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -54,7 +54,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -73,7 +73,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -94,7 +94,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -117,7 +117,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -142,7 +142,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -155,7 +155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -170,7 +170,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -187,7 +187,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -206,7 +206,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -227,7 +227,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -250,7 +250,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -275,7 +275,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -288,7 +288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -303,7 +303,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -320,7 +320,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -339,7 +339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -360,7 +360,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -383,7 +383,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -408,7 +408,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -421,7 +421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -436,7 +436,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -453,7 +453,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -472,7 +472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -493,7 +493,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -516,7 +516,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -541,7 +541,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -554,7 +554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -569,7 +569,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -586,7 +586,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -605,7 +605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -626,7 +626,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -649,7 +649,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -674,7 +674,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -687,7 +687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -702,7 +702,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -719,7 +719,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -738,7 +738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -759,7 +759,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -782,7 +782,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -807,7 +807,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -820,7 +820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -835,7 +835,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -852,7 +852,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -871,7 +871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -892,7 +892,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -915,7 +915,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -940,7 +940,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -953,7 +953,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -968,7 +968,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -985,7 +985,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1004,7 +1004,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1025,7 +1025,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1048,7 +1048,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1073,7 +1073,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1086,7 +1086,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1101,7 +1101,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1118,7 +1118,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1137,7 +1137,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1158,7 +1158,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1181,7 +1181,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1206,7 +1206,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1219,7 +1219,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1234,7 +1234,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1251,7 +1251,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1270,7 +1270,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1291,7 +1291,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1314,7 +1314,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1339,7 +1339,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1352,7 +1352,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1367,7 +1367,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1384,7 +1384,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1403,7 +1403,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1424,7 +1424,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1447,7 +1447,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1472,7 +1472,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1485,7 +1485,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1500,7 +1500,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1517,7 +1517,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1536,7 +1536,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1557,7 +1557,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1580,7 +1580,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1605,7 +1605,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1618,7 +1618,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1633,7 +1633,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1650,7 +1650,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1669,7 +1669,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1690,7 +1690,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1713,7 +1713,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1738,7 +1738,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1751,7 +1751,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1766,7 +1766,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1783,7 +1783,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1802,7 +1802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1823,7 +1823,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1846,7 +1846,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -1871,7 +1871,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -1884,7 +1884,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -1899,7 +1899,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -1916,7 +1916,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -1935,7 +1935,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -1956,7 +1956,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -1979,7 +1979,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2004,7 +2004,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2017,7 +2017,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2032,7 +2032,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2049,7 +2049,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2068,7 +2068,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2089,7 +2089,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2112,7 +2112,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2137,7 +2137,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2150,7 +2150,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2165,7 +2165,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2182,7 +2182,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2201,7 +2201,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2222,7 +2222,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2245,7 +2245,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2270,7 +2270,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2283,7 +2283,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2298,7 +2298,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2315,7 +2315,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2334,7 +2334,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2355,7 +2355,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2378,7 +2378,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2403,7 +2403,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2416,7 +2416,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2431,7 +2431,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2448,7 +2448,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2467,7 +2467,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2488,7 +2488,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2511,7 +2511,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2536,7 +2536,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2549,7 +2549,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2564,7 +2564,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2581,7 +2581,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2600,7 +2600,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2621,7 +2621,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2644,7 +2644,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2669,7 +2669,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2682,7 +2682,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2697,7 +2697,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2714,7 +2714,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2733,7 +2733,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2754,7 +2754,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2777,7 +2777,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2802,7 +2802,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2815,7 +2815,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2830,7 +2830,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2847,7 +2847,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2866,7 +2866,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -2887,7 +2887,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -2910,7 +2910,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -2935,7 +2935,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -2948,7 +2948,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -2963,7 +2963,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -2980,7 +2980,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -2999,7 +2999,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3020,7 +3020,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3043,7 +3043,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3068,7 +3068,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3081,7 +3081,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3096,7 +3096,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3113,7 +3113,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3132,7 +3132,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3153,7 +3153,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3176,7 +3176,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_i32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3201,7 +3201,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3214,7 +3214,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3229,7 +3229,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3246,7 +3246,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3265,7 +3265,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3286,7 +3286,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3309,7 +3309,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3334,7 +3334,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3347,7 +3347,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3362,7 +3362,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3379,7 +3379,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3398,7 +3398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3419,7 +3419,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3442,7 +3442,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3467,7 +3467,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i8.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3480,7 +3480,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i8.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3495,7 +3495,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3512,7 +3512,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3531,7 +3531,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3552,7 +3552,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3575,7 +3575,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3600,7 +3600,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3613,7 +3613,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3628,7 +3628,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3645,7 +3645,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3664,7 +3664,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3685,7 +3685,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3708,7 +3708,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3733,7 +3733,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3746,7 +3746,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3761,7 +3761,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3778,7 +3778,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3797,7 +3797,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3818,7 +3818,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3841,7 +3841,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3866,7 +3866,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i16.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -3879,7 +3879,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i16.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -3894,7 +3894,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -3911,7 +3911,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -3930,7 +3930,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -3951,7 +3951,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -3974,7 +3974,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -3999,7 +3999,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4012,7 +4012,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4027,7 +4027,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4044,7 +4044,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4063,7 +4063,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4084,7 +4084,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4107,7 +4107,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4132,7 +4132,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4145,7 +4145,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4160,7 +4160,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4177,7 +4177,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4196,7 +4196,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4217,7 +4217,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4240,7 +4240,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4265,7 +4265,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i32.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4278,7 +4278,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i32.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4293,7 +4293,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4310,7 +4310,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4329,7 +4329,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4350,7 +4350,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4373,7 +4373,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4398,7 +4398,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i8.nxv1i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4411,7 +4411,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i8.nxv1i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4426,7 +4426,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4443,7 +4443,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4462,7 +4462,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4483,7 +4483,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4506,7 +4506,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf8( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i8.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4531,7 +4531,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i8.nxv2i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4544,7 +4544,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i8.nxv2i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4559,7 +4559,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4576,7 +4576,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4595,7 +4595,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4616,7 +4616,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4639,7 +4639,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i8.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4664,7 +4664,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4i8.nxv4i64.i64( undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4677,7 +4677,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4i8.nxv4i64.i64( undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4692,7 +4692,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4709,7 +4709,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4728,7 +4728,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4749,7 +4749,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4772,7 +4772,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u8mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64(i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4i8.nxv4i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i8* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 1 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4797,7 +4797,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4810,7 +4810,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4825,7 +4825,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4842,7 +4842,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4861,7 +4861,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -4882,7 +4882,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -4905,7 +4905,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -4930,7 +4930,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i8.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -4943,7 +4943,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i8.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -4958,7 +4958,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -4975,7 +4975,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -4994,7 +4994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5015,7 +5015,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5038,7 +5038,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5063,7 +5063,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5076,7 +5076,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5091,7 +5091,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5108,7 +5108,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5127,7 +5127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5148,7 +5148,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5171,7 +5171,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5196,7 +5196,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i16.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5209,7 +5209,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i16.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5224,7 +5224,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5241,7 +5241,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5260,7 +5260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5281,7 +5281,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5304,7 +5304,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5329,7 +5329,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5342,7 +5342,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5357,7 +5357,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5374,7 +5374,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5393,7 +5393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5414,7 +5414,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5437,7 +5437,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5462,7 +5462,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i32.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5475,7 +5475,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i32.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5490,7 +5490,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5507,7 +5507,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5526,7 +5526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5547,7 +5547,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5570,7 +5570,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5595,7 +5595,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i16.nxv1i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5608,7 +5608,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i16.nxv1i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5623,7 +5623,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5640,7 +5640,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5659,7 +5659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5680,7 +5680,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5703,7 +5703,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16mf4( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i16.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5728,7 +5728,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2i16.nxv2i64.i64( undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5741,7 +5741,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2i16.nxv2i64.i64( undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5756,7 +5756,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5773,7 +5773,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5792,7 +5792,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5813,7 +5813,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5836,7 +5836,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u16mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64(i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2i16.nxv2i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i16* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 2 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5861,7 +5861,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i8.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -5874,7 +5874,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i8.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -5889,7 +5889,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -5906,7 +5906,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -5925,7 +5925,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -5946,7 +5946,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -5969,7 +5969,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -5994,7 +5994,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i16.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6007,7 +6007,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i16.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6022,7 +6022,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6039,7 +6039,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6058,7 +6058,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6079,7 +6079,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6102,7 +6102,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6127,7 +6127,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6140,7 +6140,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i32.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6155,7 +6155,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6172,7 +6172,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6191,7 +6191,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6212,7 +6212,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6235,7 +6235,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6260,7 +6260,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1i32.nxv1i64.i64( undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6273,7 +6273,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1i32.nxv1i64.i64( undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6288,7 +6288,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6305,7 +6305,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6324,7 +6324,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6345,7 +6345,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6368,7 +6368,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_u32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64(i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1i32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, i32* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6393,7 +6393,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i8.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6406,7 +6406,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i8.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6421,7 +6421,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6438,7 +6438,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6457,7 +6457,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6478,7 +6478,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6501,7 +6501,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei8_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i8.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i8.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6526,7 +6526,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i16.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6539,7 +6539,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i16.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6554,7 +6554,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6571,7 +6571,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6590,7 +6590,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6611,7 +6611,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6634,7 +6634,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei16_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i16.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i16.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6659,7 +6659,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i32.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6672,7 +6672,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i32.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6687,7 +6687,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6704,7 +6704,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6723,7 +6723,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6744,7 +6744,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6767,7 +6767,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei32_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i32.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i32.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 @@ -6792,7 +6792,7 @@ // CHECK-RV64-LABEL: @test_vluxseg2ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1f32.nxv1i64.i64( undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 @@ -6805,7 +6805,7 @@ // CHECK-RV64-LABEL: @test_vluxseg3ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1f32.nxv1i64.i64( undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 @@ -6820,7 +6820,7 @@ // CHECK-RV64-LABEL: @test_vluxseg4ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 @@ -6837,7 +6837,7 @@ // CHECK-RV64-LABEL: @test_vluxseg5ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 @@ -6856,7 +6856,7 @@ // CHECK-RV64-LABEL: @test_vluxseg6ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 @@ -6877,7 +6877,7 @@ // CHECK-RV64-LABEL: @test_vluxseg7ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 @@ -6900,7 +6900,7 @@ // CHECK-RV64-LABEL: @test_vluxseg8ei64_v_f32mf2( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i64.i64(float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1f32.nxv1i64.i64( undef, undef, undef, undef, undef, undef, undef, undef, float* [[BASE:%.*]], [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 // CHECK-RV64-NEXT: store [[TMP1]], * [[V0:%.*]], align 4 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -842,13 +842,14 @@ } // For unit stride segment load - // Input: (pointer, vl) + // Input: (passthru, pointer, vl) class RISCVUSSegLoad : Intrinsic, !add(nf, -1))), - [LLVMPointerToElt<0>, llvm_anyint_ty], - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { - let VLOperand = 1; + !listconcat(!listsplat(LLVMMatchType<0>, nf), + [LLVMPointerToElt<0>, llvm_anyint_ty]), + [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + let VLOperand = !add(nf, 1); } // For unit stride segment load with mask // Input: (maskedoff, pointer, mask, vl, policy) @@ -865,16 +866,17 @@ } // For unit stride fault-only-first segment load - // Input: (pointer, vl) + // Input: (passthru, pointer, vl) // Output: (data, vl) // NOTE: We model this with default memory properties since we model writing // VL as a side effect. IntrReadMem, IntrHasSideEffects does not work. class RISCVUSSegLoadFF : Intrinsic, !add(nf, -1)), [llvm_anyint_ty]), - [LLVMPointerToElt<0>, LLVMMatchType<1>], - [NoCapture>]>, RISCVVIntrinsic { - let VLOperand = 1; + !listconcat(!listsplat(LLVMMatchType<0>, nf), + [LLVMPointerToElt<0>, LLVMMatchType<1>]), + [NoCapture>]>, RISCVVIntrinsic { + let VLOperand = !add(nf, 1); } // For unit stride fault-only-first segment load with mask // Input: (maskedoff, pointer, mask, vl, policy) @@ -894,13 +896,14 @@ } // For stride segment load - // Input: (pointer, offset, vl) + // Input: (passthru, pointer, offset, vl) class RISCVSSegLoad : Intrinsic, !add(nf, -1))), - [LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>], - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { - let VLOperand = 2; + !listconcat(!listsplat(LLVMMatchType<0>, nf), + [LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>]), + [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + let VLOperand = !add(nf, 2); } // For stride segment load with mask // Input: (maskedoff, pointer, offset, mask, vl, policy) @@ -918,13 +921,14 @@ } // For indexed segment load - // Input: (pointer, index, vl) + // Input: (passthru, pointer, index, vl) class RISCVISegLoad : Intrinsic, !add(nf, -1))), - [LLVMPointerToElt<0>, llvm_anyvector_ty, llvm_anyint_ty], - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { - let VLOperand = 2; + !listconcat(!listsplat(LLVMMatchType<0>, nf), + [LLVMPointerToElt<0>, llvm_anyvector_ty, llvm_anyint_ty]), + [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + let VLOperand = !add(nf, 2); } // For indexed segment load with mask // Input: (maskedoff, pointer, index, mask, vl, policy) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -124,6 +124,7 @@ struct VLSEGPseudo { uint16_t NF : 4; uint16_t Masked : 1; + uint16_t IsTU : 1; uint16_t Strided : 1; uint16_t FF : 1; uint16_t Log2SEW : 3; @@ -134,6 +135,7 @@ struct VLXSEGPseudo { uint16_t NF : 4; uint16_t Masked : 1; + uint16_t IsTU : 1; uint16_t Ordered : 1; uint16_t Log2SEW : 3; uint16_t LMUL : 3; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -311,6 +311,10 @@ Operands.push_back(Glue); } +static bool isAllUndef(ArrayRef Values) { + return llvm::all_of(Values, [](SDValue V) { return V->isUndef(); }); +} + void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided) { SDLoc DL(Node); @@ -321,19 +325,21 @@ unsigned CurOp = 2; SmallVector Operands; - if (IsMasked) { - SmallVector Regs(Node->op_begin() + CurOp, - Node->op_begin() + CurOp + NF); - SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); - Operands.push_back(MaskedOff); - CurOp += NF; + + SmallVector Regs(Node->op_begin() + CurOp, + Node->op_begin() + CurOp + NF); + bool IsTU = IsMasked || !isAllUndef(Regs); + if (IsTU) { + SDValue Merge = createTuple(*CurDAG, Regs, NF, LMUL); + Operands.push_back(Merge); } + CurOp += NF; addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided, Operands, /*IsLoad=*/true); const RISCV::VLSEGPseudo *P = - RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, Log2SEW, + RISCV::getVLSEGPseudo(NF, IsMasked, IsTU, IsStrided, /*FF*/ false, Log2SEW, static_cast(LMUL)); MachineSDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); @@ -363,20 +369,22 @@ unsigned CurOp = 2; SmallVector Operands; - if (IsMasked) { - SmallVector Regs(Node->op_begin() + CurOp, - Node->op_begin() + CurOp + NF); + + SmallVector Regs(Node->op_begin() + CurOp, + Node->op_begin() + CurOp + NF); + bool IsTU = IsMasked || !isAllUndef(Regs); + if (IsTU) { SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); Operands.push_back(MaskedOff); - CurOp += NF; } + CurOp += NF; addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, /*IsStridedOrIndexed*/ false, Operands, /*IsLoad=*/true); const RISCV::VLSEGPseudo *P = - RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true, + RISCV::getVLSEGPseudo(NF, IsMasked, IsTU, /*Strided*/ false, /*FF*/ true, Log2SEW, static_cast(LMUL)); MachineSDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, MVT::Glue, Operands); @@ -418,13 +426,15 @@ unsigned CurOp = 2; SmallVector Operands; - if (IsMasked) { - SmallVector Regs(Node->op_begin() + CurOp, - Node->op_begin() + CurOp + NF); + + SmallVector Regs(Node->op_begin() + CurOp, + Node->op_begin() + CurOp + NF); + bool IsTU = IsMasked || !isAllUndef(Regs); + if (IsTU) { SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); Operands.push_back(MaskedOff); - CurOp += NF; } + CurOp += NF; MVT IndexVT; addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, @@ -441,7 +451,7 @@ "values when XLEN=32"); } const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( - NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast(LMUL), + NF, IsMasked, IsTU, IsOrdered, IndexLog2EEW, static_cast(LMUL), static_cast(IndexLMUL)); MachineSDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4903,9 +4903,12 @@ SmallVector ContainerVTs(NF, ContainerVT); ContainerVTs.push_back(MVT::Other); SDVTList VTs = DAG.getVTList(ContainerVTs); + SmallVector Ops = {Load->getChain(), IntID}; + Ops.insert(Ops.end(), NF, DAG.getUNDEF(ContainerVT)); + Ops.push_back(Op.getOperand(2)); + Ops.push_back(VL); SDValue Result = - DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, - {Load->getChain(), IntID, Op.getOperand(2), VL}, + DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, Load->getMemoryVT(), Load->getMemOperand()); SmallVector Results; for (unsigned int RetIdx = 0; RetIdx < NF; RetIdx++) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -503,9 +503,10 @@ let PrimaryKeyName = "getVSXPseudo"; } -class RISCVVLSEG N, bit M, bit Str, bit F, bits<3> S, bits<3> L> { +class RISCVVLSEG N, bit M, bit TU, bit Str, bit F, bits<3> S, bits<3> L> { bits<4> NF = N; bits<1> Masked = M; + bits<1> IsTU = TU; bits<1> Strided = Str; bits<1> FF = F; bits<3> Log2SEW = S; @@ -516,14 +517,15 @@ def RISCVVLSEGTable : GenericTable { let FilterClass = "RISCVVLSEG"; let CppTypeName = "VLSEGPseudo"; - let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"]; - let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"]; + let Fields = ["NF", "Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"]; + let PrimaryKey = ["NF", "Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL"]; let PrimaryKeyName = "getVLSEGPseudo"; } -class RISCVVLXSEG N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> { +class RISCVVLXSEG N, bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> { bits<4> NF = N; bits<1> Masked = M; + bits<1> IsTU = TU; bits<1> Ordered = O; bits<3> Log2SEW = S; bits<3> LMUL = L; @@ -534,8 +536,8 @@ def RISCVVLXSEGTable : GenericTable { let FilterClass = "RISCVVLXSEG"; let CppTypeName = "VLXSEGPseudo"; - let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; - let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; + let Fields = ["NF", "Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; + let PrimaryKey = ["NF", "Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; let PrimaryKeyName = "getVLXSEGPseudo"; } @@ -1313,13 +1315,29 @@ Pseudo<(outs RetClass:$rd), (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG.val, VLMul> { + let mayLoad = 1; + let mayStore = 0; + let hasSideEffects = 0; + let HasVLOp = 1; + let HasSEWOp = 1; + let HasDummyMask = 1; + let BaseInstr = !cast(PseudoToVInst.VInst); +} + +class VPseudoUSSegLoadNoMaskTU NF, bit isFF>: + Pseudo<(outs RetClass:$rd), + (ins RetClass:$dest, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>, + RISCVVPseudo, + RISCVVLSEG.val, VLMul> { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; let HasVLOp = 1; let HasSEWOp = 1; let HasDummyMask = 1; + let HasMergeOp = 1; + let Constraints = "$rd = $dest"; let BaseInstr = !cast(PseudoToVInst.VInst); } @@ -1328,7 +1346,7 @@ (ins GetVRegNoV0.R:$merge, GPR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG.val, VLMul> { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1345,7 +1363,7 @@ Pseudo<(outs RetClass:$rd), (ins GPR:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG.val, VLMul> { let mayLoad = 1; let mayLoad = 1; let mayStore = 0; @@ -1356,13 +1374,30 @@ let BaseInstr = !cast(PseudoToVInst.VInst); } +class VPseudoSSegLoadNoMaskTU NF>: + Pseudo<(outs RetClass:$rd), + (ins RetClass:$merge, GPR:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>, + RISCVVPseudo, + RISCVVLSEG.val, VLMul> { + let mayLoad = 1; + let mayLoad = 1; + let mayStore = 0; + let hasSideEffects = 0; + let HasVLOp = 1; + let HasSEWOp = 1; + let HasDummyMask = 1; + let HasMergeOp = 1; + let Constraints = "$rd = $merge"; + let BaseInstr = !cast(PseudoToVInst.VInst); +} + class VPseudoSSegLoadMask NF>: Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$merge, GPR:$rs1, GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG.val, VLMul> { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1380,7 +1415,7 @@ Pseudo<(outs RetClass:$rd), (ins GPR:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLXSEG.val, VLMul, LMUL> { + RISCVVLXSEG.val, VLMul, LMUL> { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1393,6 +1428,25 @@ let BaseInstr = !cast(PseudoToVInst.VInst); } +class VPseudoISegLoadNoMaskTU LMUL, + bits<4> NF, bit Ordered>: + Pseudo<(outs RetClass:$rd), + (ins RetClass:$merge, GPR:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>, + RISCVVPseudo, + RISCVVLXSEG.val, VLMul, LMUL> { + let mayLoad = 1; + let mayStore = 0; + let hasSideEffects = 0; + // For vector indexed segment loads, the destination vector register groups + // cannot overlap the source vector register group + let Constraints = "@earlyclobber $rd, $rd = $merge"; + let HasVLOp = 1; + let HasSEWOp = 1; + let HasDummyMask = 1; + let HasMergeOp = 1; + let BaseInstr = !cast(PseudoToVInst.VInst); +} + class VPseudoISegLoadMask LMUL, bits<4> NF, bit Ordered>: Pseudo<(outs GetVRegNoV0.R:$rd), @@ -1400,7 +1454,7 @@ IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLXSEG.val, VLMul, LMUL> { + RISCVVLXSEG.val, VLMul, LMUL> { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -2751,6 +2805,8 @@ defvar FFStr = !if(isFF, "FF", ""); def nf # "E" # eew # FFStr # "_V_" # LInfo : VPseudoUSSegLoadNoMask; + def nf # "E" # eew # FFStr # "_V_" # LInfo # "_TU" : + VPseudoUSSegLoadNoMaskTU; def nf # "E" # eew # FFStr # "_V_" # LInfo # "_MASK" : VPseudoUSSegLoadMask; } @@ -2767,6 +2823,7 @@ foreach nf = NFSet.L in { defvar vreg = SegRegClass.RC; def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask; + def nf # "E" # eew # "_V_" # LInfo # "_TU" : VPseudoSSegLoadNoMaskTU; def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask; } } @@ -2793,6 +2850,9 @@ def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo : VPseudoISegLoadNoMask; + def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_TU" : + VPseudoISegLoadNoMaskTU; def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" : VPseudoISegLoadMask; diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll --- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll +++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll @@ -148,7 +148,7 @@ ; SUBREGLIVENESS-NEXT: addi sp, sp, 32 ; SUBREGLIVENESS-NEXT: ret entry: - %i = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(half* nonnull poison, poison, i64 55) + %i = call { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( undef, undef, half* nonnull poison, poison, i64 55) %i1 = extractvalue { , } %i, 0 %i2 = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64( poison, poison, poison, zeroinitializer, i64 36, i64 0) call void @func() @@ -161,7 +161,7 @@ } declare void @func() -declare { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(half* nocapture, , i64) +declare { , } @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( , , half* nocapture, , i64) declare @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(, , , , i64, i64 immarg) declare @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(, , , , i64, i64 immarg) declare @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(, , , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll @@ -50,7 +50,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i32 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -103,7 +103,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i32 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -160,7 +160,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i32 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -217,7 +217,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i32 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -280,15 +280,15 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i32 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,,} %0, 1 ret %1 } -declare {,} @llvm.riscv.vlseg2.nxv1i32(i32* , i32) -declare {,} @llvm.riscv.vlseg2.nxv2i32(i32* , i32) -declare {,} @llvm.riscv.vlseg2.nxv4i32(i32* , i32) -declare {,} @llvm.riscv.vlseg2.nxv8i32(i32* , i32) -declare {,,} @llvm.riscv.vlseg3.nxv4i32(i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1i32(,, i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2i32(,, i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4i32(,, i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8i32(,, i32* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4i32(,,, i32* , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll @@ -50,7 +50,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i64 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -103,7 +103,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i64 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -160,7 +160,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i64 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -217,7 +217,7 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i64 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,} %0, 1 @@ -280,15 +280,15 @@ ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i64 %vl) call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() %1 = extractvalue {,,} %0, 1 ret %1 } -declare {,} @llvm.riscv.vlseg2.nxv1i32(i32* , i64) -declare {,} @llvm.riscv.vlseg2.nxv2i32(i32* , i64) -declare {,} @llvm.riscv.vlseg2.nxv4i32(i32* , i64) -declare {,} @llvm.riscv.vlseg2.nxv8i32(i32* , i64) -declare {,,} @llvm.riscv.vlseg3.nxv4i32(i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1i32(,, i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2i32(,, i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4i32(,, i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8i32(,, i32* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4i32(,,, i32* , i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i32, i32) define @test_vloxseg2_nxv16i16_nxv16i16(i16* %base, %index, i32 %vl) { @@ -13,7 +13,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -31,7 +31,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i8(,, i16*, , , i32, i32) define @test_vloxseg2_nxv16i16_nxv16i8(i16* %base, %index, i32 %vl) { @@ -42,7 +42,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -60,7 +60,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i32(,, i16*, , , i32, i32) define @test_vloxseg2_nxv16i16_nxv16i32(i16* %base, %index, i32 %vl) { @@ -71,7 +71,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -89,7 +89,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -100,7 +100,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -118,7 +118,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i32(,, i8*, , , i32, i32) define @test_vloxseg2_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -129,7 +129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -147,7 +147,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -158,7 +158,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -176,7 +176,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i8(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -187,7 +187,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -207,7 +207,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i32(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -218,7 +218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -238,7 +238,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i16(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -249,7 +249,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -269,7 +269,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i8(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -280,7 +280,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -302,7 +302,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i32(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -313,7 +313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -335,7 +335,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i16(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -346,7 +346,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -368,7 +368,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i8(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -379,7 +379,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -402,7 +402,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i32(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -413,7 +413,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -436,7 +436,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i16(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -447,7 +447,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -470,7 +470,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i8(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -481,7 +481,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -505,7 +505,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i32(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -516,7 +516,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -540,7 +540,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i16(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -551,7 +551,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -575,7 +575,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i8(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -586,7 +586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -611,7 +611,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i32(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -622,7 +622,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -647,7 +647,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i16(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -658,7 +658,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -683,7 +683,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i8(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -694,7 +694,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -720,7 +720,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i32(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -731,7 +731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -757,7 +757,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i16(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -768,7 +768,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -794,7 +794,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -805,7 +805,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -823,7 +823,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -834,7 +834,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -852,7 +852,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i32(,, i8*, , , i32, i32) define @test_vloxseg2_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -863,7 +863,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -881,7 +881,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i16(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -892,7 +892,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -911,7 +911,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i8(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -922,7 +922,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -942,7 +942,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i32(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -953,7 +953,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -972,7 +972,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i16(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -983,7 +983,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1004,7 +1004,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i8(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -1015,7 +1015,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1037,7 +1037,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i32(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -1048,7 +1048,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1068,7 +1068,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32(,, i32*, , , i32, i32) define @test_vloxseg2_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1079,7 +1079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1097,7 +1097,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i8(,, i32*, , , i32, i32) define @test_vloxseg2_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1108,7 +1108,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1126,7 +1126,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i16(,, i32*, , , i32, i32) define @test_vloxseg2_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1137,7 +1137,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1155,7 +1155,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i32(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1166,7 +1166,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1186,7 +1186,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i8(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1197,7 +1197,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1217,7 +1217,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i16(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1228,7 +1228,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1248,7 +1248,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i32(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1259,7 +1259,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1281,7 +1281,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i8(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1292,7 +1292,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1314,7 +1314,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i16(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1325,7 +1325,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1347,7 +1347,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i32(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1358,7 +1358,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1381,7 +1381,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i8(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1392,7 +1392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1415,7 +1415,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i16(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1426,7 +1426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1449,7 +1449,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i32(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1460,7 +1460,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1484,7 +1484,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i8(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1495,7 +1495,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1519,7 +1519,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i16(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1530,7 +1530,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1554,7 +1554,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i32(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1565,7 +1565,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1590,7 +1590,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i8(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1601,7 +1601,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1626,7 +1626,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i16(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1637,7 +1637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1662,7 +1662,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i32(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1673,7 +1673,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1699,7 +1699,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i8(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1710,7 +1710,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1736,7 +1736,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i16(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1747,7 +1747,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1773,7 +1773,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i16(,, i16*, , , i32, i32) define @test_vloxseg2_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1784,7 +1784,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1802,7 +1802,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i8(,, i16*, , , i32, i32) define @test_vloxseg2_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1813,7 +1813,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1831,7 +1831,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i32(,, i16*, , , i32, i32) define @test_vloxseg2_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -1842,7 +1842,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1860,7 +1860,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i16(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1871,7 +1871,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1891,7 +1891,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i8(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1902,7 +1902,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1922,7 +1922,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i32(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -1933,7 +1933,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1952,7 +1952,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i16(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1963,7 +1963,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1985,7 +1985,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i8(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1996,7 +1996,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2018,7 +2018,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i32(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2029,7 +2029,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2050,7 +2050,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i16(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2061,7 +2061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2084,7 +2084,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i8(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2095,7 +2095,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2118,7 +2118,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i32(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2129,7 +2129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2152,7 +2152,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i16(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2163,7 +2163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2187,7 +2187,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i8(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2198,7 +2198,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2222,7 +2222,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i32(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2233,7 +2233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2257,7 +2257,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i16(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2268,7 +2268,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2293,7 +2293,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i8(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2304,7 +2304,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2329,7 +2329,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i32(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2340,7 +2340,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2365,7 +2365,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i16(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2376,7 +2376,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2402,7 +2402,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i8(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2413,7 +2413,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2439,7 +2439,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i32(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2450,7 +2450,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2476,7 +2476,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i8(,, i32*, , , i32, i32) define @test_vloxseg2_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2487,7 +2487,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2505,7 +2505,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i32(,, i32*, , , i32, i32) define @test_vloxseg2_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2516,7 +2516,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2534,7 +2534,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(,, i32*, , , i32, i32) define @test_vloxseg2_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2545,7 +2545,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2563,7 +2563,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i8(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2574,7 +2574,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2594,7 +2594,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i32(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2605,7 +2605,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2625,7 +2625,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2636,7 +2636,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2656,7 +2656,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i8(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2667,7 +2667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2689,7 +2689,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i32(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2700,7 +2700,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2722,7 +2722,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2733,7 +2733,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2755,7 +2755,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i8(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2766,7 +2766,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2789,7 +2789,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i32(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2800,7 +2800,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2823,7 +2823,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(,,,,, i32*, , , i32, i32) define @test_vloxseg5_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2834,7 +2834,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2857,7 +2857,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i8(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2868,7 +2868,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2892,7 +2892,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i32(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2903,7 +2903,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2927,7 +2927,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(,,,,,, i32*, , , i32, i32) define @test_vloxseg6_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2938,7 +2938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2962,7 +2962,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i8(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2973,7 +2973,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2998,7 +2998,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i32(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -3009,7 +3009,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3034,7 +3034,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(,,,,,,, i32*, , , i32, i32) define @test_vloxseg7_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -3045,7 +3045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3070,7 +3070,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i8(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -3081,7 +3081,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3107,7 +3107,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i32(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -3118,7 +3118,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3144,7 +3144,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(,,,,,,,, i32*, , , i32, i32) define @test_vloxseg8_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -3155,7 +3155,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3181,7 +3181,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i16(,, i16*, , , i32, i32) define @test_vloxseg2_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3192,7 +3192,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3210,7 +3210,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i8(,, i16*, , , i32, i32) define @test_vloxseg2_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3221,7 +3221,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3239,7 +3239,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i32(,, i16*, , , i32, i32) define @test_vloxseg2_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3250,7 +3250,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3268,7 +3268,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i16(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3279,7 +3279,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3299,7 +3299,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i8(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3310,7 +3310,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3330,7 +3330,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i32(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3341,7 +3341,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3360,7 +3360,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i16(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3371,7 +3371,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3393,7 +3393,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i8(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3404,7 +3404,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3426,7 +3426,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i32(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3437,7 +3437,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3458,7 +3458,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3469,7 +3469,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3487,7 +3487,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3498,7 +3498,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3516,7 +3516,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i32(,, i8*, , , i32, i32) define @test_vloxseg2_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3527,7 +3527,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3545,7 +3545,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i16(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3556,7 +3556,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3575,7 +3575,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i8(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3586,7 +3586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3606,7 +3606,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i32(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3617,7 +3617,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3636,7 +3636,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i16(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3647,7 +3647,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3668,7 +3668,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i8(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3679,7 +3679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3701,7 +3701,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i32(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3712,7 +3712,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3732,7 +3732,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i16(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3743,7 +3743,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3766,7 +3766,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i8(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3777,7 +3777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3800,7 +3800,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i32(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3811,7 +3811,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3832,7 +3832,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i16(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3843,7 +3843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3867,7 +3867,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i8(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3878,7 +3878,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3902,7 +3902,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i32(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3913,7 +3913,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3936,7 +3936,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i16(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3947,7 +3947,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3972,7 +3972,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i8(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3983,7 +3983,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4008,7 +4008,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i32(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -4019,7 +4019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4044,7 +4044,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i16(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -4055,7 +4055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4081,7 +4081,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i8(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -4092,7 +4092,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4118,7 +4118,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i32(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -4129,7 +4129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4155,7 +4155,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i16(,, i32*, , , i32, i32) define @test_vloxseg2_nxv8i32_nxv8i16(i32* %base, %index, i32 %vl) { @@ -4166,7 +4166,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4184,7 +4184,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i8(,, i32*, , , i32, i32) define @test_vloxseg2_nxv8i32_nxv8i8(i32* %base, %index, i32 %vl) { @@ -4195,7 +4195,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4213,7 +4213,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i32(,, i32*, , , i32, i32) define @test_vloxseg2_nxv8i32_nxv8i32(i32* %base, %index, i32 %vl) { @@ -4224,7 +4224,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4242,7 +4242,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4253,7 +4253,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4271,7 +4271,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4282,7 +4282,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4300,7 +4300,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i32(,, i8*, , , i32, i32) define @test_vloxseg2_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4311,7 +4311,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4329,7 +4329,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i16(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4340,7 +4340,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4360,7 +4360,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i8(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4371,7 +4371,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4391,7 +4391,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i32(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4402,7 +4402,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4421,7 +4421,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i16(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4432,7 +4432,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4454,7 +4454,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i8(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4465,7 +4465,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4487,7 +4487,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i32(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4498,7 +4498,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4519,7 +4519,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i16(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4530,7 +4530,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4553,7 +4553,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i8(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4564,7 +4564,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4587,7 +4587,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i32(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4598,7 +4598,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4621,7 +4621,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i16(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4632,7 +4632,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4656,7 +4656,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i8(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4667,7 +4667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4691,7 +4691,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i32(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4702,7 +4702,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4726,7 +4726,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i16(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4737,7 +4737,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4762,7 +4762,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i8(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4773,7 +4773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4798,7 +4798,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i32(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4809,7 +4809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4834,7 +4834,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i16(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4845,7 +4845,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4871,7 +4871,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i8(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4882,7 +4882,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4908,7 +4908,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i32(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4919,7 +4919,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4945,7 +4945,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i8(,, i16*, , , i32, i32) define @test_vloxseg2_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -4956,7 +4956,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4974,7 +4974,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i32(,, i16*, , , i32, i32) define @test_vloxseg2_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -4985,7 +4985,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5003,7 +5003,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i16(,, i16*, , , i32, i32) define @test_vloxseg2_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5014,7 +5014,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5032,7 +5032,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i8(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5043,7 +5043,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5063,7 +5063,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i32(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5074,7 +5074,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5094,7 +5094,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i16(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5105,7 +5105,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5125,7 +5125,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i8(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5136,7 +5136,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5158,7 +5158,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i32(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5169,7 +5169,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5191,7 +5191,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i16(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5202,7 +5202,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5224,7 +5224,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i8(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5235,7 +5235,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5258,7 +5258,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i32(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5269,7 +5269,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5292,7 +5292,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i16(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5303,7 +5303,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5326,7 +5326,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i8(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5337,7 +5337,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5361,7 +5361,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i32(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5372,7 +5372,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5396,7 +5396,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i16(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5407,7 +5407,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5431,7 +5431,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i8(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5442,7 +5442,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5467,7 +5467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i32(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5478,7 +5478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5503,7 +5503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i16(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5514,7 +5514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5539,7 +5539,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i8(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5550,7 +5550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5576,7 +5576,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i32(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5587,7 +5587,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5613,7 +5613,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i16(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5624,7 +5624,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5650,7 +5650,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv32i8.nxv32i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv32i8_nxv32i16(i8* %base, %index, i32 %vl) { @@ -5661,7 +5661,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5679,7 +5679,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv32i8.nxv32i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv32i8_nxv32i8(i8* %base, %index, i32 %vl) { @@ -5690,7 +5690,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5708,7 +5708,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i32(,, i8*, , , i32, i32) define @test_vloxseg2_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5719,7 +5719,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5737,7 +5737,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i8(,, i8*, , , i32, i32) define @test_vloxseg2_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5748,7 +5748,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5766,7 +5766,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(i8*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(,, i8*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i16(,, i8*, , , i32, i32) define @test_vloxseg2_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5777,7 +5777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5795,7 +5795,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i32(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5806,7 +5806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5826,7 +5826,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i8(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5837,7 +5837,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5857,7 +5857,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(i8*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i16(,,, i8*, , , i32, i32) define @test_vloxseg3_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5868,7 +5868,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5888,7 +5888,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i32(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5899,7 +5899,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5921,7 +5921,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i8(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5932,7 +5932,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5954,7 +5954,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i16(,,,, i8*, , , i32, i32) define @test_vloxseg4_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5965,7 +5965,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5987,7 +5987,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i32(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5998,7 +5998,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6021,7 +6021,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i8(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6032,7 +6032,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6055,7 +6055,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i16(,,,,, i8*, , , i32, i32) define @test_vloxseg5_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6066,7 +6066,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6089,7 +6089,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i32(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6100,7 +6100,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6124,7 +6124,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i8(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6135,7 +6135,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6159,7 +6159,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i16(,,,,,, i8*, , , i32, i32) define @test_vloxseg6_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6170,7 +6170,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6194,7 +6194,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i32(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6205,7 +6205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6230,7 +6230,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i8(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6241,7 +6241,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6266,7 +6266,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i16(,,,,,,, i8*, , , i32, i32) define @test_vloxseg7_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6277,7 +6277,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6302,7 +6302,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i32(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6313,7 +6313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6339,7 +6339,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i8(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6350,7 +6350,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6376,7 +6376,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i16(,,,,,,,, i8*, , , i32, i32) define @test_vloxseg8_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6387,7 +6387,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6413,7 +6413,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i32(,, i16*, , , i32, i32) define @test_vloxseg2_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6424,7 +6424,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6442,7 +6442,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i8(,, i16*, , , i32, i32) define @test_vloxseg2_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6453,7 +6453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6471,7 +6471,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(i16*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(,, i16*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i16(,, i16*, , , i32, i32) define @test_vloxseg2_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6482,7 +6482,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6500,7 +6500,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i32(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6511,7 +6511,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6531,7 +6531,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i8(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6542,7 +6542,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6562,7 +6562,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(i16*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i16(,,, i16*, , , i32, i32) define @test_vloxseg3_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6573,7 +6573,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6593,7 +6593,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i32(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6604,7 +6604,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6626,7 +6626,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i8(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6637,7 +6637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6659,7 +6659,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i16(,,,, i16*, , , i32, i32) define @test_vloxseg4_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6670,7 +6670,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6692,7 +6692,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i32(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6703,7 +6703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6726,7 +6726,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i8(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6737,7 +6737,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6760,7 +6760,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i16(,,,,, i16*, , , i32, i32) define @test_vloxseg5_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6771,7 +6771,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6794,7 +6794,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i32(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6805,7 +6805,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6829,7 +6829,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i8(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6840,7 +6840,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6864,7 +6864,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i16(,,,,,, i16*, , , i32, i32) define @test_vloxseg6_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6875,7 +6875,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6899,7 +6899,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i32(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6910,7 +6910,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6935,7 +6935,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i8(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6946,7 +6946,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6971,7 +6971,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i16(,,,,,,, i16*, , , i32, i32) define @test_vloxseg7_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6982,7 +6982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7007,7 +7007,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i32(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -7018,7 +7018,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7044,7 +7044,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i8(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -7055,7 +7055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7081,7 +7081,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i16(,,,,,,,, i16*, , , i32, i32) define @test_vloxseg8_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -7092,7 +7092,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7118,7 +7118,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i16(,, i32*, , , i32, i32) define @test_vloxseg2_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7129,7 +7129,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7147,7 +7147,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i8(,, i32*, , , i32, i32) define @test_vloxseg2_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7158,7 +7158,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7176,7 +7176,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(i32*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(,, i32*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i32(,, i32*, , , i32, i32) define @test_vloxseg2_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7187,7 +7187,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7205,7 +7205,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i16(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7216,7 +7216,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7236,7 +7236,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i8(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7247,7 +7247,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7267,7 +7267,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(i32*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i32(,,, i32*, , , i32, i32) define @test_vloxseg3_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7278,7 +7278,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7298,7 +7298,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i16(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7309,7 +7309,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7331,7 +7331,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i8(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7342,7 +7342,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7364,7 +7364,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(i32*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i32(,,,, i32*, , , i32, i32) define @test_vloxseg4_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7375,7 +7375,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7397,7 +7397,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i16(,, half*, , , i32, i32) define @test_vloxseg2_nxv16f16_nxv16i16(half* %base, %index, i32 %vl) { @@ -7408,7 +7408,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7426,7 +7426,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i8(,, half*, , , i32, i32) define @test_vloxseg2_nxv16f16_nxv16i8(half* %base, %index, i32 %vl) { @@ -7437,7 +7437,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7455,7 +7455,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i32(,, half*, , , i32, i32) define @test_vloxseg2_nxv16f16_nxv16i32(half* %base, %index, i32 %vl) { @@ -7466,7 +7466,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7484,7 +7484,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i16(,, double*, , , i32, i32) define @test_vloxseg2_nxv4f64_nxv4i16(double* %base, %index, i32 %vl) { @@ -7495,7 +7495,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7513,7 +7513,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i8(,, double*, , , i32, i32) define @test_vloxseg2_nxv4f64_nxv4i8(double* %base, %index, i32 %vl) { @@ -7524,7 +7524,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7542,7 +7542,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i32(,, double*, , , i32, i32) define @test_vloxseg2_nxv4f64_nxv4i32(double* %base, %index, i32 %vl) { @@ -7553,7 +7553,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7571,7 +7571,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i8(,, double*, , , i32, i32) define @test_vloxseg2_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7582,7 +7582,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7600,7 +7600,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i32(,, double*, , , i32, i32) define @test_vloxseg2_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7611,7 +7611,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7629,7 +7629,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i16(,, double*, , , i32, i32) define @test_vloxseg2_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7640,7 +7640,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7658,7 +7658,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i8(,,, double*, , , i32, i32) define @test_vloxseg3_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7669,7 +7669,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7689,7 +7689,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i32(,,, double*, , , i32, i32) define @test_vloxseg3_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7700,7 +7700,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7720,7 +7720,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i16(,,, double*, , , i32, i32) define @test_vloxseg3_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7731,7 +7731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7751,7 +7751,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i8(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7762,7 +7762,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7784,7 +7784,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i32(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7795,7 +7795,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7817,7 +7817,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i16(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7828,7 +7828,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7850,7 +7850,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i8(,,,,, double*, , , i32, i32) define @test_vloxseg5_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7861,7 +7861,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7884,7 +7884,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i32(,,,,, double*, , , i32, i32) define @test_vloxseg5_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7895,7 +7895,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7918,7 +7918,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i16(,,,,, double*, , , i32, i32) define @test_vloxseg5_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7929,7 +7929,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7952,7 +7952,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i8(,,,,,, double*, , , i32, i32) define @test_vloxseg6_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7963,7 +7963,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7987,7 +7987,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i32(,,,,,, double*, , , i32, i32) define @test_vloxseg6_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7998,7 +7998,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8022,7 +8022,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i16(,,,,,, double*, , , i32, i32) define @test_vloxseg6_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8033,7 +8033,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8057,7 +8057,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i8(,,,,,,, double*, , , i32, i32) define @test_vloxseg7_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -8068,7 +8068,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8093,7 +8093,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i32(,,,,,,, double*, , , i32, i32) define @test_vloxseg7_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -8104,7 +8104,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8129,7 +8129,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i16(,,,,,,, double*, , , i32, i32) define @test_vloxseg7_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8140,7 +8140,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8165,7 +8165,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i8(,,,,,,,, double*, , , i32, i32) define @test_vloxseg8_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -8176,7 +8176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8202,7 +8202,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i32(,,,,,,,, double*, , , i32, i32) define @test_vloxseg8_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -8213,7 +8213,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8239,7 +8239,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i16(,,,,,,,, double*, , , i32, i32) define @test_vloxseg8_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8250,7 +8250,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8276,7 +8276,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i32(,, float*, , , i32, i32) define @test_vloxseg2_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8287,7 +8287,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8305,7 +8305,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i8(,, float*, , , i32, i32) define @test_vloxseg2_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8316,7 +8316,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8334,7 +8334,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i16(,, float*, , , i32, i32) define @test_vloxseg2_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8345,7 +8345,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8363,7 +8363,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i32(,,, float*, , , i32, i32) define @test_vloxseg3_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8374,7 +8374,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8394,7 +8394,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i8(,,, float*, , , i32, i32) define @test_vloxseg3_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8405,7 +8405,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8425,7 +8425,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i16(,,, float*, , , i32, i32) define @test_vloxseg3_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8436,7 +8436,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8456,7 +8456,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i32(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8467,7 +8467,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8489,7 +8489,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i8(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8500,7 +8500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8522,7 +8522,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i16(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8533,7 +8533,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8555,7 +8555,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i32(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8566,7 +8566,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8589,7 +8589,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i8(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8600,7 +8600,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8623,7 +8623,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i16(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8634,7 +8634,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8657,7 +8657,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i32(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8668,7 +8668,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8692,7 +8692,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i8(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8703,7 +8703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8727,7 +8727,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i16(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8738,7 +8738,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8762,7 +8762,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i32(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8773,7 +8773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8798,7 +8798,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i8(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8809,7 +8809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8834,7 +8834,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i16(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8845,7 +8845,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8870,7 +8870,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i32(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8881,7 +8881,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8907,7 +8907,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i8(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8918,7 +8918,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8944,7 +8944,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i16(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8955,7 +8955,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8981,7 +8981,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i8(,, half*, , , i32, i32) define @test_vloxseg2_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -8992,7 +8992,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9010,7 +9010,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i32(,, half*, , , i32, i32) define @test_vloxseg2_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9021,7 +9021,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9039,7 +9039,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i16(,, half*, , , i32, i32) define @test_vloxseg2_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9050,7 +9050,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9068,7 +9068,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i8(,,, half*, , , i32, i32) define @test_vloxseg3_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9079,7 +9079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9099,7 +9099,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i32(,,, half*, , , i32, i32) define @test_vloxseg3_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9110,7 +9110,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9130,7 +9130,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i16(,,, half*, , , i32, i32) define @test_vloxseg3_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9141,7 +9141,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9161,7 +9161,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i8(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9172,7 +9172,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9194,7 +9194,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i32(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9205,7 +9205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9227,7 +9227,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i16(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9238,7 +9238,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9260,7 +9260,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i8(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9271,7 +9271,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9294,7 +9294,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i32(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9305,7 +9305,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9328,7 +9328,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i16(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9339,7 +9339,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9362,7 +9362,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i8(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9373,7 +9373,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9397,7 +9397,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i32(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9408,7 +9408,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9432,7 +9432,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i16(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9443,7 +9443,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9467,7 +9467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i8(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9478,7 +9478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9503,7 +9503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i32(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9514,7 +9514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9539,7 +9539,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i16(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9550,7 +9550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9575,7 +9575,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i8(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9586,7 +9586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9612,7 +9612,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i32(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9623,7 +9623,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9649,7 +9649,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i16(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9660,7 +9660,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9686,7 +9686,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i8(,, float*, , , i32, i32) define @test_vloxseg2_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9697,7 +9697,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9715,7 +9715,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i32(,, float*, , , i32, i32) define @test_vloxseg2_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9726,7 +9726,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9744,7 +9744,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i16(,, float*, , , i32, i32) define @test_vloxseg2_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9755,7 +9755,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9773,7 +9773,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i8(,,, float*, , , i32, i32) define @test_vloxseg3_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9784,7 +9784,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9804,7 +9804,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i32(,,, float*, , , i32, i32) define @test_vloxseg3_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9815,7 +9815,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9835,7 +9835,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i16(,,, float*, , , i32, i32) define @test_vloxseg3_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9846,7 +9846,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9866,7 +9866,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i8(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9877,7 +9877,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9899,7 +9899,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i32(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9910,7 +9910,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9932,7 +9932,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i16(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9943,7 +9943,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9965,7 +9965,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i8(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9976,7 +9976,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9999,7 +9999,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i32(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10010,7 +10010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10033,7 +10033,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i16(,,,,, float*, , , i32, i32) define @test_vloxseg5_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10044,7 +10044,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10067,7 +10067,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i8(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10078,7 +10078,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10102,7 +10102,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i32(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10113,7 +10113,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10137,7 +10137,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i16(,,,,,, float*, , , i32, i32) define @test_vloxseg6_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10148,7 +10148,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10172,7 +10172,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i8(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10183,7 +10183,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10208,7 +10208,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i32(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10219,7 +10219,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10244,7 +10244,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i16(,,,,,,, float*, , , i32, i32) define @test_vloxseg7_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10255,7 +10255,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10280,7 +10280,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i8(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10291,7 +10291,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10317,7 +10317,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i32(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10328,7 +10328,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10354,7 +10354,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i16(,,,,,,,, float*, , , i32, i32) define @test_vloxseg8_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10365,7 +10365,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10391,7 +10391,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i16(,, half*, , , i32, i32) define @test_vloxseg2_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10402,7 +10402,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10420,7 +10420,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i8(,, half*, , , i32, i32) define @test_vloxseg2_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10431,7 +10431,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10449,7 +10449,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i32(,, half*, , , i32, i32) define @test_vloxseg2_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10460,7 +10460,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10478,7 +10478,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i16(,,, half*, , , i32, i32) define @test_vloxseg3_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10489,7 +10489,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10509,7 +10509,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i8(,,, half*, , , i32, i32) define @test_vloxseg3_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10520,7 +10520,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10540,7 +10540,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i32(,,, half*, , , i32, i32) define @test_vloxseg3_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10551,7 +10551,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10570,7 +10570,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i16(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10581,7 +10581,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10603,7 +10603,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i8(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10614,7 +10614,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10636,7 +10636,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i32(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10647,7 +10647,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10668,7 +10668,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i16(,, float*, , , i32, i32) define @test_vloxseg2_nxv8f32_nxv8i16(float* %base, %index, i32 %vl) { @@ -10679,7 +10679,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10697,7 +10697,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i8(,, float*, , , i32, i32) define @test_vloxseg2_nxv8f32_nxv8i8(float* %base, %index, i32 %vl) { @@ -10708,7 +10708,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10726,7 +10726,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i32(,, float*, , , i32, i32) define @test_vloxseg2_nxv8f32_nxv8i32(float* %base, %index, i32 %vl) { @@ -10737,7 +10737,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10755,7 +10755,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i32(,, double*, , , i32, i32) define @test_vloxseg2_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10766,7 +10766,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10784,7 +10784,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i8(,, double*, , , i32, i32) define @test_vloxseg2_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10795,7 +10795,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10813,7 +10813,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(double*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(,, double*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i16(,, double*, , , i32, i32) define @test_vloxseg2_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -10824,7 +10824,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10842,7 +10842,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i32(,,, double*, , , i32, i32) define @test_vloxseg3_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10853,7 +10853,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10873,7 +10873,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i8(,,, double*, , , i32, i32) define @test_vloxseg3_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10884,7 +10884,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10904,7 +10904,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(double*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(,,, double*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i16(,,, double*, , , i32, i32) define @test_vloxseg3_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -10915,7 +10915,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10935,7 +10935,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i32(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10946,7 +10946,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10968,7 +10968,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i8(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10979,7 +10979,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11001,7 +11001,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(double*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(,,,, double*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i16(,,,, double*, , , i32, i32) define @test_vloxseg4_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -11012,7 +11012,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11034,7 +11034,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i16(,, half*, , , i32, i32) define @test_vloxseg2_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11045,7 +11045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11063,7 +11063,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i8(,, half*, , , i32, i32) define @test_vloxseg2_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11074,7 +11074,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11092,7 +11092,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i32(,, half*, , , i32, i32) define @test_vloxseg2_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11103,7 +11103,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11121,7 +11121,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i16(,,, half*, , , i32, i32) define @test_vloxseg3_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11132,7 +11132,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11152,7 +11152,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i8(,,, half*, , , i32, i32) define @test_vloxseg3_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11163,7 +11163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11183,7 +11183,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i32(,,, half*, , , i32, i32) define @test_vloxseg3_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11194,7 +11194,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11213,7 +11213,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i16(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11224,7 +11224,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11246,7 +11246,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i8(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11257,7 +11257,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11279,7 +11279,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i32(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11290,7 +11290,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11311,7 +11311,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i16(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11322,7 +11322,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11345,7 +11345,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i8(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11356,7 +11356,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11379,7 +11379,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i32(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11390,7 +11390,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11413,7 +11413,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i16(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11424,7 +11424,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11448,7 +11448,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i8(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11459,7 +11459,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11483,7 +11483,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i32(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11494,7 +11494,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11518,7 +11518,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i16(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11529,7 +11529,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11554,7 +11554,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i8(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11565,7 +11565,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11590,7 +11590,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i32(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11601,7 +11601,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11626,7 +11626,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i16(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11637,7 +11637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11663,7 +11663,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i8(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11674,7 +11674,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11700,7 +11700,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i32(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11711,7 +11711,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11737,7 +11737,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i32(,, half*, , , i32, i32) define @test_vloxseg2_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11748,7 +11748,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11766,7 +11766,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i8(,, half*, , , i32, i32) define @test_vloxseg2_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11777,7 +11777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11795,7 +11795,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(half*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(,, half*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i16(,, half*, , , i32, i32) define @test_vloxseg2_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11806,7 +11806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11824,7 +11824,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i32(,,, half*, , , i32, i32) define @test_vloxseg3_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11835,7 +11835,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11855,7 +11855,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i8(,,, half*, , , i32, i32) define @test_vloxseg3_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11866,7 +11866,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11886,7 +11886,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(half*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(,,, half*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i16(,,, half*, , , i32, i32) define @test_vloxseg3_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11897,7 +11897,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11917,7 +11917,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i32(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11928,7 +11928,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11950,7 +11950,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i8(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11961,7 +11961,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11983,7 +11983,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(half*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i16(,,,, half*, , , i32, i32) define @test_vloxseg4_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11994,7 +11994,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12016,7 +12016,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i32(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12027,7 +12027,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12050,7 +12050,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i8(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12061,7 +12061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12084,7 +12084,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i16(,,,,, half*, , , i32, i32) define @test_vloxseg5_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12095,7 +12095,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12118,7 +12118,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i32(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12129,7 +12129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12153,7 +12153,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i8(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12164,7 +12164,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12188,7 +12188,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i16(,,,,,, half*, , , i32, i32) define @test_vloxseg6_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12199,7 +12199,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12223,7 +12223,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i32(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12234,7 +12234,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12259,7 +12259,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i8(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12270,7 +12270,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12295,7 +12295,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i16(,,,,,,, half*, , , i32, i32) define @test_vloxseg7_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12306,7 +12306,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12331,7 +12331,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i32(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12342,7 +12342,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12368,7 +12368,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i8(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12379,7 +12379,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12405,7 +12405,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i16(,,,,,,,, half*, , , i32, i32) define @test_vloxseg8_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12416,7 +12416,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12442,7 +12442,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i16(,, float*, , , i32, i32) define @test_vloxseg2_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12453,7 +12453,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12471,7 +12471,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i8(,, float*, , , i32, i32) define @test_vloxseg2_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12482,7 +12482,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12500,7 +12500,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(float*, , i32) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(,, float*, , i32) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i32(,, float*, , , i32, i32) define @test_vloxseg2_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12511,7 +12511,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12529,7 +12529,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i16(,,, float*, , , i32, i32) define @test_vloxseg3_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12540,7 +12540,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12560,7 +12560,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i8(,,, float*, , , i32, i32) define @test_vloxseg3_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12571,7 +12571,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12591,7 +12591,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(float*, , i32) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(,,, float*, , i32) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i32(,,, float*, , , i32, i32) define @test_vloxseg3_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12602,7 +12602,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12622,7 +12622,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i16(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12633,7 +12633,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12655,7 +12655,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i8(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12666,7 +12666,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12688,7 +12688,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(float*, , i32) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i32(,,,, float*, , , i32, i32) define @test_vloxseg4_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12699,7 +12699,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i64, i64) define @test_vloxseg2_nxv16i16_nxv16i16(i16* %base, %index, i64 %vl) { @@ -13,7 +13,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -31,7 +31,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i8(,, i16*, , , i64, i64) define @test_vloxseg2_nxv16i16_nxv16i8(i16* %base, %index, i64 %vl) { @@ -42,7 +42,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -60,7 +60,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i32(,, i16*, , , i64, i64) define @test_vloxseg2_nxv16i16_nxv16i32(i16* %base, %index, i64 %vl) { @@ -71,7 +71,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -89,7 +89,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i32(,, i32*, , , i64, i64) define @test_vloxseg2_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -100,7 +100,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -118,7 +118,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i8(,, i32*, , , i64, i64) define @test_vloxseg2_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -129,7 +129,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -147,7 +147,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i64(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i64(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i64(,, i32*, , , i64, i64) define @test_vloxseg2_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -158,7 +158,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -176,7 +176,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i32.nxv4i16(,, i32*, , , i64, i64) define @test_vloxseg2_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -187,7 +187,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i32.nxv4i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -205,7 +205,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i32(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -216,7 +216,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -236,7 +236,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i8(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -247,7 +247,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -267,7 +267,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i64(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i64(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -278,7 +278,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -297,7 +297,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i32.nxv4i16(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -308,7 +308,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i32.nxv4i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -328,7 +328,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i32(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -339,7 +339,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -361,7 +361,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i8(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -372,7 +372,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -394,7 +394,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i64(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i64(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -405,7 +405,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -426,7 +426,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i32.nxv4i16(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -437,7 +437,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i32.nxv4i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -459,7 +459,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -470,7 +470,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -488,7 +488,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -499,7 +499,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -517,7 +517,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i8.nxv16i32(,, i8*, , , i64, i64) define @test_vloxseg2_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -528,7 +528,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i8.nxv16i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -546,7 +546,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i16(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -557,7 +557,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -576,7 +576,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i8(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -587,7 +587,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -607,7 +607,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv16i8.nxv16i32(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -618,7 +618,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv16i8.nxv16i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -637,7 +637,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i16(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -648,7 +648,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -669,7 +669,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i8(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -680,7 +680,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -702,7 +702,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv16i8.nxv16i32(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -713,7 +713,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv16i8.nxv16i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -733,7 +733,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i64(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i64(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i64.nxv1i64(,, i64*, , , i64, i64) define @test_vloxseg2_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -744,7 +744,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -762,7 +762,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i32(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i32(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i64.nxv1i32(,, i64*, , , i64, i64) define @test_vloxseg2_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -773,7 +773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -791,7 +791,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i16(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i16(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i64.nxv1i16(,, i64*, , , i64, i64) define @test_vloxseg2_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -802,7 +802,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -820,7 +820,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i8(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i8(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i64.nxv1i8(,, i64*, , , i64, i64) define @test_vloxseg2_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -831,7 +831,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i64.nxv1i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -849,7 +849,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i64(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i64(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i64.nxv1i64(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -860,7 +860,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i64( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -880,7 +880,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i32(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i32(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i64.nxv1i32(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -891,7 +891,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i32( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -911,7 +911,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i16(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i16(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i64.nxv1i16(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -922,7 +922,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i16( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -942,7 +942,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i8(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i8(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i64.nxv1i8(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -953,7 +953,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i64.nxv1i8( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -973,7 +973,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i64(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i64.nxv1i64(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -984,7 +984,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i64( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1006,7 +1006,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i32(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i64.nxv1i32(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1017,7 +1017,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i32( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1039,7 +1039,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i16(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i64.nxv1i16(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1050,7 +1050,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i16( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1072,7 +1072,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i8(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i64.nxv1i8(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1083,7 +1083,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i64.nxv1i8( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1105,7 +1105,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i64(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i64.nxv1i64(,,,,, i64*, , , i64, i64) define @test_vloxseg5_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1116,7 +1116,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1139,7 +1139,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i32(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i64.nxv1i32(,,,,, i64*, , , i64, i64) define @test_vloxseg5_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1150,7 +1150,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1173,7 +1173,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i16(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i64.nxv1i16(,,,,, i64*, , , i64, i64) define @test_vloxseg5_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1184,7 +1184,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1207,7 +1207,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i8(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i64.nxv1i8(,,,,, i64*, , , i64, i64) define @test_vloxseg5_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1218,7 +1218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1241,7 +1241,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i64(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i64.nxv1i64(,,,,,, i64*, , , i64, i64) define @test_vloxseg6_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1252,7 +1252,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1276,7 +1276,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i32(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i64.nxv1i32(,,,,,, i64*, , , i64, i64) define @test_vloxseg6_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1287,7 +1287,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1311,7 +1311,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i16(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i64.nxv1i16(,,,,,, i64*, , , i64, i64) define @test_vloxseg6_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1322,7 +1322,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1346,7 +1346,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i8(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i64.nxv1i8(,,,,,, i64*, , , i64, i64) define @test_vloxseg6_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1357,7 +1357,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1381,7 +1381,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i64(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i64.nxv1i64(,,,,,,, i64*, , , i64, i64) define @test_vloxseg7_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1392,7 +1392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1417,7 +1417,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i32(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i64.nxv1i32(,,,,,,, i64*, , , i64, i64) define @test_vloxseg7_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1428,7 +1428,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1453,7 +1453,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i16(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i64.nxv1i16(,,,,,,, i64*, , , i64, i64) define @test_vloxseg7_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1464,7 +1464,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1489,7 +1489,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i8(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i64.nxv1i8(,,,,,,, i64*, , , i64, i64) define @test_vloxseg7_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1500,7 +1500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1525,7 +1525,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i64(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i64.nxv1i64(,,,,,,,, i64*, , , i64, i64) define @test_vloxseg8_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1536,7 +1536,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1562,7 +1562,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i32(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i64.nxv1i32(,,,,,,,, i64*, , , i64, i64) define @test_vloxseg8_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1573,7 +1573,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1599,7 +1599,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i16(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i64.nxv1i16(,,,,,,,, i64*, , , i64, i64) define @test_vloxseg8_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1610,7 +1610,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1636,7 +1636,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i8(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i64.nxv1i8(,,,,,,,, i64*, , , i64, i64) define @test_vloxseg8_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1647,7 +1647,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1673,7 +1673,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i64(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i64(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i64(,, i32*, , , i64, i64) define @test_vloxseg2_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1684,7 +1684,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1702,7 +1702,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i32(,, i32*, , , i64, i64) define @test_vloxseg2_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1713,7 +1713,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1731,7 +1731,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i16(,, i32*, , , i64, i64) define @test_vloxseg2_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1742,7 +1742,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1760,7 +1760,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i32.nxv1i8(,, i32*, , , i64, i64) define @test_vloxseg2_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -1771,7 +1771,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i32.nxv1i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1789,7 +1789,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i64(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i64(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1800,7 +1800,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1820,7 +1820,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i32(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1831,7 +1831,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1851,7 +1851,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i16(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1862,7 +1862,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1882,7 +1882,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i32.nxv1i8(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -1893,7 +1893,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i32.nxv1i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1913,7 +1913,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i64(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1924,7 +1924,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1946,7 +1946,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i32(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1957,7 +1957,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1979,7 +1979,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i16(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1990,7 +1990,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2012,7 +2012,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i32.nxv1i8(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2023,7 +2023,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i32.nxv1i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2045,7 +2045,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i64(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i64(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2056,7 +2056,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2079,7 +2079,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i32(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2090,7 +2090,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2113,7 +2113,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i16(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2124,7 +2124,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2147,7 +2147,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i32.nxv1i8(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2158,7 +2158,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2181,7 +2181,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i64(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i64(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2192,7 +2192,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2216,7 +2216,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i32(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2227,7 +2227,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2251,7 +2251,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i16(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2262,7 +2262,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2286,7 +2286,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i32.nxv1i8(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2321,7 +2321,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i64(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i64(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2332,7 +2332,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2357,7 +2357,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i32(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2368,7 +2368,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2393,7 +2393,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i16(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2404,7 +2404,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2429,7 +2429,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i32.nxv1i8(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2440,7 +2440,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2465,7 +2465,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i64(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i64(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2476,7 +2476,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2502,7 +2502,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i32(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2513,7 +2513,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2539,7 +2539,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i16(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2550,7 +2550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2576,7 +2576,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i32.nxv1i8(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2587,7 +2587,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2613,7 +2613,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i16(,, i16*, , , i64, i64) define @test_vloxseg2_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2624,7 +2624,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2642,7 +2642,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i8(,, i16*, , , i64, i64) define @test_vloxseg2_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2653,7 +2653,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2671,7 +2671,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i64(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i64(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i64(,, i16*, , , i64, i64) define @test_vloxseg2_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2682,7 +2682,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2700,7 +2700,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i16.nxv8i32(,, i16*, , , i64, i64) define @test_vloxseg2_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2711,7 +2711,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i16.nxv8i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2729,7 +2729,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i16(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2740,7 +2740,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2760,7 +2760,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i8(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2771,7 +2771,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2791,7 +2791,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i64(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i64(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2802,7 +2802,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2821,7 +2821,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i16.nxv8i32(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2832,7 +2832,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i16.nxv8i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2851,7 +2851,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i16(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2862,7 +2862,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2884,7 +2884,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i8(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2895,7 +2895,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2917,7 +2917,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i64(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i64(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2928,7 +2928,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2948,7 +2948,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i16.nxv8i32(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2959,7 +2959,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i16.nxv8i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2980,7 +2980,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i32(,, i8*, , , i64, i64) define @test_vloxseg2_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -2991,7 +2991,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3009,7 +3009,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3020,7 +3020,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3038,7 +3038,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i64(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i64(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i64(,, i8*, , , i64, i64) define @test_vloxseg2_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3049,7 +3049,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3067,7 +3067,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i8.nxv4i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3078,7 +3078,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i8.nxv4i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3096,7 +3096,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i32(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3107,7 +3107,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3126,7 +3126,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i8(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3137,7 +3137,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3157,7 +3157,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i64(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i64(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3168,7 +3168,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3187,7 +3187,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i8.nxv4i16(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3198,7 +3198,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i8.nxv4i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3218,7 +3218,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i32(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3229,7 +3229,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3250,7 +3250,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i8(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3261,7 +3261,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3283,7 +3283,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i64(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3294,7 +3294,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3314,7 +3314,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i8.nxv4i16(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3325,7 +3325,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i8.nxv4i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3347,7 +3347,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i32(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3358,7 +3358,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3381,7 +3381,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i8(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3392,7 +3392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3415,7 +3415,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i64(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3426,7 +3426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3447,7 +3447,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i8.nxv4i16(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3458,7 +3458,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3481,7 +3481,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i32(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3492,7 +3492,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3516,7 +3516,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i8(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3527,7 +3527,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3551,7 +3551,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i64(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3562,7 +3562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3585,7 +3585,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i8.nxv4i16(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3596,7 +3596,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3620,7 +3620,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i32(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3631,7 +3631,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3656,7 +3656,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i8(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3667,7 +3667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3692,7 +3692,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i64(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3703,7 +3703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3728,7 +3728,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i8.nxv4i16(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3764,7 +3764,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i32(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3775,7 +3775,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3801,7 +3801,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i8(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3812,7 +3812,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3838,7 +3838,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i64(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3849,7 +3849,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3875,7 +3875,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i8.nxv4i16(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3886,7 +3886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3912,7 +3912,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i64(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i64(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i64(,, i16*, , , i64, i64) define @test_vloxseg2_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -3923,7 +3923,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3941,7 +3941,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i32(,, i16*, , , i64, i64) define @test_vloxseg2_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -3952,7 +3952,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3970,7 +3970,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i16(,, i16*, , , i64, i64) define @test_vloxseg2_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -3981,7 +3981,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3999,7 +3999,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i16.nxv1i8(,, i16*, , , i64, i64) define @test_vloxseg2_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i16.nxv1i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4028,7 +4028,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i64(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i64(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4039,7 +4039,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4059,7 +4059,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i32(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4070,7 +4070,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4090,7 +4090,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i16(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4101,7 +4101,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4121,7 +4121,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i16.nxv1i8(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4132,7 +4132,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i16.nxv1i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4152,7 +4152,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i64(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4163,7 +4163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4185,7 +4185,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i32(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4196,7 +4196,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4218,7 +4218,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i16(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4229,7 +4229,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4251,7 +4251,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i16.nxv1i8(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4262,7 +4262,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i16.nxv1i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4284,7 +4284,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i64(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4295,7 +4295,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4318,7 +4318,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i32(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4329,7 +4329,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4352,7 +4352,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i16(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4363,7 +4363,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4386,7 +4386,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i16.nxv1i8(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4397,7 +4397,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4420,7 +4420,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i64(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4431,7 +4431,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4455,7 +4455,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i32(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4466,7 +4466,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4490,7 +4490,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i16(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4501,7 +4501,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4525,7 +4525,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i16.nxv1i8(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4536,7 +4536,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4560,7 +4560,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i64(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4571,7 +4571,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4596,7 +4596,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i32(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4607,7 +4607,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4632,7 +4632,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i16(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4643,7 +4643,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4668,7 +4668,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i16.nxv1i8(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4679,7 +4679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4704,7 +4704,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i64(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4715,7 +4715,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4741,7 +4741,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i32(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4752,7 +4752,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4778,7 +4778,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i16(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4789,7 +4789,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4815,7 +4815,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i16.nxv1i8(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4826,7 +4826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4852,7 +4852,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32(,, i32*, , , i64, i64) define @test_vloxseg2_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -4863,7 +4863,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4881,7 +4881,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i8(,, i32*, , , i64, i64) define @test_vloxseg2_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -4892,7 +4892,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4910,7 +4910,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i16(,, i32*, , , i64, i64) define @test_vloxseg2_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -4921,7 +4921,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4939,7 +4939,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i64(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i64(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i64(,, i32*, , , i64, i64) define @test_vloxseg2_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -4950,7 +4950,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i32.nxv2i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4968,7 +4968,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i32(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -4979,7 +4979,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4999,7 +4999,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i8(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5010,7 +5010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5030,7 +5030,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i16(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5041,7 +5041,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5061,7 +5061,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i64(i32*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i32.nxv2i64(,,, i32*, , , i64, i64) define @test_vloxseg3_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5072,7 +5072,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i32.nxv2i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5091,7 +5091,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i32(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5102,7 +5102,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5124,7 +5124,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i8(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5135,7 +5135,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5157,7 +5157,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i16(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5168,7 +5168,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5190,7 +5190,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i32.nxv2i64(,,,, i32*, , , i64, i64) define @test_vloxseg4_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5201,7 +5201,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i32.nxv2i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5222,7 +5222,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i32(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5233,7 +5233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5256,7 +5256,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i8(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5267,7 +5267,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5290,7 +5290,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i16(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5301,7 +5301,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5324,7 +5324,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i64(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i32.nxv2i64(,,,,, i32*, , , i64, i64) define @test_vloxseg5_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5335,7 +5335,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5358,7 +5358,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i32(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5369,7 +5369,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5393,7 +5393,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i8(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5404,7 +5404,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5428,7 +5428,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i16(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5439,7 +5439,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5463,7 +5463,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i64(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i32.nxv2i64(,,,,,, i32*, , , i64, i64) define @test_vloxseg6_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5474,7 +5474,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5498,7 +5498,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i32(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5509,7 +5509,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5534,7 +5534,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i8(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5545,7 +5545,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5570,7 +5570,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i16(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5581,7 +5581,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5606,7 +5606,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i64(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i32.nxv2i64(,,,,,,, i32*, , , i64, i64) define @test_vloxseg7_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5617,7 +5617,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5642,7 +5642,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i32(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5653,7 +5653,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5679,7 +5679,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i8(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5690,7 +5690,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5716,7 +5716,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i16(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5727,7 +5727,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5753,7 +5753,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i64(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i32.nxv2i64(,,,,,,,, i32*, , , i64, i64) define @test_vloxseg8_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5764,7 +5764,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i32.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5790,7 +5790,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -5801,7 +5801,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5819,7 +5819,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -5830,7 +5830,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5848,7 +5848,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i64(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i64(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i64(,, i8*, , , i64, i64) define @test_vloxseg2_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -5859,7 +5859,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5877,7 +5877,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i8.nxv8i32(,, i8*, , , i64, i64) define @test_vloxseg2_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -5888,7 +5888,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i8.nxv8i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5906,7 +5906,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i16(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -5917,7 +5917,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5936,7 +5936,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i8(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -5947,7 +5947,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5967,7 +5967,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i64(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i64(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -5978,7 +5978,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5997,7 +5997,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8i8.nxv8i32(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6008,7 +6008,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8i8.nxv8i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6027,7 +6027,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i16(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6038,7 +6038,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6059,7 +6059,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i8(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6070,7 +6070,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6092,7 +6092,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i64(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6103,7 +6103,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6123,7 +6123,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8i8.nxv8i32(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6134,7 +6134,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8i8.nxv8i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6154,7 +6154,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i16(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6165,7 +6165,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6188,7 +6188,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i8(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6199,7 +6199,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6222,7 +6222,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i64(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6233,7 +6233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6254,7 +6254,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv8i8.nxv8i32(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6265,7 +6265,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6286,7 +6286,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i16(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6297,7 +6297,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6321,7 +6321,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i8(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6332,7 +6332,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6356,7 +6356,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i64(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6367,7 +6367,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6389,7 +6389,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv8i8.nxv8i32(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6400,7 +6400,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6423,7 +6423,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i16(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6434,7 +6434,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6459,7 +6459,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i8(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6470,7 +6470,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6495,7 +6495,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i64(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6506,7 +6506,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6529,7 +6529,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv8i8.nxv8i32(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6540,7 +6540,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6565,7 +6565,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i16(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6576,7 +6576,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6602,7 +6602,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i8(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6613,7 +6613,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6639,7 +6639,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i64(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6650,7 +6650,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6674,7 +6674,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv8i8.nxv8i32(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6685,7 +6685,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv8i8.nxv8i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6711,7 +6711,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i32(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i32(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i64.nxv4i32(,, i64*, , , i64, i64) define @test_vloxseg2_nxv4i64_nxv4i32(i64* %base, %index, i64 %vl) { @@ -6722,7 +6722,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6740,7 +6740,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i8(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i8(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i64.nxv4i8(,, i64*, , , i64, i64) define @test_vloxseg2_nxv4i64_nxv4i8(i64* %base, %index, i64 %vl) { @@ -6751,7 +6751,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6769,7 +6769,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i64(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i64(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i64.nxv4i64(,, i64*, , , i64, i64) define @test_vloxseg2_nxv4i64_nxv4i64(i64* %base, %index, i64 %vl) { @@ -6780,7 +6780,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6798,7 +6798,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i16(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i16(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i64.nxv4i16(,, i64*, , , i64, i64) define @test_vloxseg2_nxv4i64_nxv4i16(i64* %base, %index, i64 %vl) { @@ -6809,7 +6809,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i64.nxv4i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6827,7 +6827,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i32(,, i16*, , , i64, i64) define @test_vloxseg2_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -6838,7 +6838,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6856,7 +6856,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i8(,, i16*, , , i64, i64) define @test_vloxseg2_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -6867,7 +6867,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6885,7 +6885,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i64(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i64(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i64(,, i16*, , , i64, i64) define @test_vloxseg2_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -6896,7 +6896,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6914,7 +6914,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4i16.nxv4i16(,, i16*, , , i64, i64) define @test_vloxseg2_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -6925,7 +6925,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4i16.nxv4i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6943,7 +6943,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i32(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -6954,7 +6954,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6973,7 +6973,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i8(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -6984,7 +6984,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7004,7 +7004,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i64(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i64(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7015,7 +7015,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7034,7 +7034,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4i16.nxv4i16(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7045,7 +7045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4i16.nxv4i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7065,7 +7065,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i32(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7076,7 +7076,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7097,7 +7097,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i8(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7108,7 +7108,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7130,7 +7130,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i64(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7141,7 +7141,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7161,7 +7161,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4i16.nxv4i16(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7172,7 +7172,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4i16.nxv4i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7194,7 +7194,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i32(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7205,7 +7205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7228,7 +7228,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i8(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7239,7 +7239,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7262,7 +7262,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i64(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7273,7 +7273,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7294,7 +7294,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4i16.nxv4i16(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7305,7 +7305,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7328,7 +7328,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i32(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7339,7 +7339,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7363,7 +7363,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i8(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7374,7 +7374,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7398,7 +7398,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i64(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7409,7 +7409,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7432,7 +7432,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4i16.nxv4i16(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7443,7 +7443,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7467,7 +7467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i32(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7478,7 +7478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7503,7 +7503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i8(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7514,7 +7514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7539,7 +7539,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i64(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7550,7 +7550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7575,7 +7575,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4i16.nxv4i16(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7586,7 +7586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7611,7 +7611,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i32(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7622,7 +7622,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7648,7 +7648,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i8(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7659,7 +7659,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7685,7 +7685,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i64(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7696,7 +7696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7722,7 +7722,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4i16.nxv4i16(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7733,7 +7733,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4i16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7759,7 +7759,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i64(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i64(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i64(,, i8*, , , i64, i64) define @test_vloxseg2_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -7770,7 +7770,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7788,7 +7788,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i32(,, i8*, , , i64, i64) define @test_vloxseg2_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -7799,7 +7799,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7817,7 +7817,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -7828,7 +7828,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7846,7 +7846,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1i8.nxv1i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -7857,7 +7857,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1i8.nxv1i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7875,7 +7875,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i64(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i64(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -7886,7 +7886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7906,7 +7906,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i32(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -7917,7 +7917,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7937,7 +7937,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i16(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -7948,7 +7948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7968,7 +7968,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1i8.nxv1i8(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -7979,7 +7979,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1i8.nxv1i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7999,7 +7999,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i64(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8010,7 +8010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8032,7 +8032,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i32(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8043,7 +8043,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8065,7 +8065,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i16(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8076,7 +8076,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8098,7 +8098,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1i8.nxv1i8(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8109,7 +8109,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1i8.nxv1i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8131,7 +8131,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i64(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8142,7 +8142,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8165,7 +8165,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i32(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8176,7 +8176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8199,7 +8199,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i16(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8210,7 +8210,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8233,7 +8233,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1i8.nxv1i8(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8244,7 +8244,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8267,7 +8267,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i64(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8278,7 +8278,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8302,7 +8302,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i32(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8313,7 +8313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8337,7 +8337,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i16(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8348,7 +8348,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8372,7 +8372,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1i8.nxv1i8(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8383,7 +8383,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8407,7 +8407,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i64(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8418,7 +8418,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8443,7 +8443,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i32(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8454,7 +8454,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8479,7 +8479,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i16(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8490,7 +8490,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8515,7 +8515,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1i8.nxv1i8(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8526,7 +8526,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8551,7 +8551,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i64(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8562,7 +8562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8588,7 +8588,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i32(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8599,7 +8599,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8625,7 +8625,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i16(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8636,7 +8636,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8662,7 +8662,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1i8.nxv1i8(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8673,7 +8673,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1i8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8699,7 +8699,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i32(,, i8*, , , i64, i64) define @test_vloxseg2_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8710,7 +8710,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8728,7 +8728,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8739,7 +8739,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8757,7 +8757,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -8768,7 +8768,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8786,7 +8786,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i64(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i64(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i8.nxv2i64(,, i8*, , , i64, i64) define @test_vloxseg2_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -8797,7 +8797,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i8.nxv2i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8815,7 +8815,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i32(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8826,7 +8826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8846,7 +8846,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i8(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8857,7 +8857,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8877,7 +8877,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i16(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -8888,7 +8888,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8908,7 +8908,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i64(i8*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i8.nxv2i64(,,, i8*, , , i64, i64) define @test_vloxseg3_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -8919,7 +8919,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i8.nxv2i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8938,7 +8938,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i32(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8949,7 +8949,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8971,7 +8971,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i8(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8982,7 +8982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9004,7 +9004,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i16(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9015,7 +9015,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9037,7 +9037,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i8.nxv2i64(,,,, i8*, , , i64, i64) define @test_vloxseg4_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9048,7 +9048,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i8.nxv2i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9069,7 +9069,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i32(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9080,7 +9080,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9103,7 +9103,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i8(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9114,7 +9114,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9137,7 +9137,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i16(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9148,7 +9148,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9171,7 +9171,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i8.nxv2i64(,,,,, i8*, , , i64, i64) define @test_vloxseg5_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9182,7 +9182,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9205,7 +9205,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i32(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9216,7 +9216,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9240,7 +9240,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i8(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9251,7 +9251,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9275,7 +9275,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i16(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9286,7 +9286,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9310,7 +9310,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i8.nxv2i64(,,,,,, i8*, , , i64, i64) define @test_vloxseg6_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9321,7 +9321,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9345,7 +9345,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i32(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9356,7 +9356,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9381,7 +9381,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i8(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9392,7 +9392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9417,7 +9417,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i16(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9428,7 +9428,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9453,7 +9453,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i8.nxv2i64(,,,,,,, i8*, , , i64, i64) define @test_vloxseg7_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9464,7 +9464,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9489,7 +9489,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i32(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9500,7 +9500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9526,7 +9526,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i8(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9537,7 +9537,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9563,7 +9563,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i16(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9574,7 +9574,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9600,7 +9600,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i8.nxv2i64(,,,,,,,, i8*, , , i64, i64) define @test_vloxseg8_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9611,7 +9611,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i8.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9637,7 +9637,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i16(,, i32*, , , i64, i64) define @test_vloxseg2_nxv8i32_nxv8i16(i32* %base, %index, i64 %vl) { @@ -9648,7 +9648,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9666,7 +9666,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i8(,, i32*, , , i64, i64) define @test_vloxseg2_nxv8i32_nxv8i8(i32* %base, %index, i64 %vl) { @@ -9677,7 +9677,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9695,7 +9695,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i64(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i64(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i64(,, i32*, , , i64, i64) define @test_vloxseg2_nxv8i32_nxv8i64(i32* %base, %index, i64 %vl) { @@ -9706,7 +9706,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9724,7 +9724,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(i32*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(,, i32*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8i32.nxv8i32(,, i32*, , , i64, i64) define @test_vloxseg2_nxv8i32_nxv8i32(i32* %base, %index, i64 %vl) { @@ -9735,7 +9735,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8i32.nxv8i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9753,7 +9753,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv32i8.nxv32i16(,, i8*, , , i64, i64) define @test_vloxseg2_nxv32i8_nxv32i16(i8* %base, %index, i64 %vl) { @@ -9764,7 +9764,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9782,7 +9782,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(i8*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(,, i8*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv32i8.nxv32i8(,, i8*, , , i64, i64) define @test_vloxseg2_nxv32i8_nxv32i8(i8* %base, %index, i64 %vl) { @@ -9793,7 +9793,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv32i8.nxv32i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9811,7 +9811,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i32(,, i16*, , , i64, i64) define @test_vloxseg2_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -9822,7 +9822,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9840,7 +9840,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i8(,, i16*, , , i64, i64) define @test_vloxseg2_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -9851,7 +9851,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9869,7 +9869,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i16(,, i16*, , , i64, i64) define @test_vloxseg2_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -9880,7 +9880,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9898,7 +9898,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i64(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i64(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i16.nxv2i64(,, i16*, , , i64, i64) define @test_vloxseg2_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -9909,7 +9909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i16.nxv2i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9927,7 +9927,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i32(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -9938,7 +9938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9958,7 +9958,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i8(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -9969,7 +9969,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9989,7 +9989,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i16(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10000,7 +10000,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10020,7 +10020,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i64(i16*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i16.nxv2i64(,,, i16*, , , i64, i64) define @test_vloxseg3_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10031,7 +10031,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i16.nxv2i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10050,7 +10050,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i32(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10061,7 +10061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10083,7 +10083,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i8(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10094,7 +10094,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10116,7 +10116,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i16(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10127,7 +10127,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10149,7 +10149,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i16.nxv2i64(,,,, i16*, , , i64, i64) define @test_vloxseg4_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10160,7 +10160,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i16.nxv2i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10181,7 +10181,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i32(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10192,7 +10192,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10215,7 +10215,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i8(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10226,7 +10226,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10249,7 +10249,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i16(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10260,7 +10260,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10283,7 +10283,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2i16.nxv2i64(,,,,, i16*, , , i64, i64) define @test_vloxseg5_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10294,7 +10294,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10317,7 +10317,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i32(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10328,7 +10328,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10352,7 +10352,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i8(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10363,7 +10363,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10387,7 +10387,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i16(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10398,7 +10398,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10422,7 +10422,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2i16.nxv2i64(,,,,,, i16*, , , i64, i64) define @test_vloxseg6_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10433,7 +10433,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10457,7 +10457,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i32(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10468,7 +10468,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10493,7 +10493,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i8(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10504,7 +10504,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10529,7 +10529,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i16(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10540,7 +10540,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10565,7 +10565,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2i16.nxv2i64(,,,,,,, i16*, , , i64, i64) define @test_vloxseg7_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10576,7 +10576,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10601,7 +10601,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i32(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10612,7 +10612,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10638,7 +10638,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i8(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10649,7 +10649,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10675,7 +10675,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i16(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10686,7 +10686,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10712,7 +10712,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2i16.nxv2i64(,,,,,,,, i16*, , , i64, i64) define @test_vloxseg8_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10723,7 +10723,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2i16.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10749,7 +10749,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i32(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i32(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i64.nxv2i32(,, i64*, , , i64, i64) define @test_vloxseg2_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -10760,7 +10760,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10778,7 +10778,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i8(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i8(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i64.nxv2i8(,, i64*, , , i64, i64) define @test_vloxseg2_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -10789,7 +10789,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10807,7 +10807,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i16(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i16(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i64.nxv2i16(,, i64*, , , i64, i64) define @test_vloxseg2_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -10818,7 +10818,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10836,7 +10836,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i64(i64*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i64(,, i64*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2i64.nxv2i64(,, i64*, , , i64, i64) define @test_vloxseg2_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -10847,7 +10847,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2i64.nxv2i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10865,7 +10865,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i32(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i32(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i64.nxv2i32(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -10876,7 +10876,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i32( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10896,7 +10896,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i8(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i8(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i64.nxv2i8(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -10907,7 +10907,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i8( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10927,7 +10927,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i16(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i16(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i64.nxv2i16(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -10938,7 +10938,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i16( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10958,7 +10958,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i64(i64*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i64(,,, i64*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2i64.nxv2i64(,,, i64*, , , i64, i64) define @test_vloxseg3_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -10969,7 +10969,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2i64.nxv2i64( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10989,7 +10989,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i32(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i32(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i64.nxv2i32(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -11000,7 +11000,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i32( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11022,7 +11022,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i8(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i8(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i64.nxv2i8(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -11033,7 +11033,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i8( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11055,7 +11055,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i16(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i16(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i64.nxv2i16(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -11066,7 +11066,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i16( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11088,7 +11088,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i64(i64*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i64(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2i64.nxv2i64(,,,, i64*, , , i64, i64) define @test_vloxseg4_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -11099,7 +11099,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2i64.nxv2i64( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11121,7 +11121,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i16(,, half*, , , i64, i64) define @test_vloxseg2_nxv16f16_nxv16i16(half* %base, %index, i64 %vl) { @@ -11132,7 +11132,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11150,7 +11150,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i8(,, half*, , , i64, i64) define @test_vloxseg2_nxv16f16_nxv16i8(half* %base, %index, i64 %vl) { @@ -11161,7 +11161,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11179,7 +11179,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16f16.nxv16i32(,, half*, , , i64, i64) define @test_vloxseg2_nxv16f16_nxv16i32(half* %base, %index, i64 %vl) { @@ -11190,7 +11190,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11208,7 +11208,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i32(,, double*, , , i64, i64) define @test_vloxseg2_nxv4f64_nxv4i32(double* %base, %index, i64 %vl) { @@ -11219,7 +11219,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11237,7 +11237,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i8(,, double*, , , i64, i64) define @test_vloxseg2_nxv4f64_nxv4i8(double* %base, %index, i64 %vl) { @@ -11248,7 +11248,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11266,7 +11266,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i64(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i64(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i64(,, double*, , , i64, i64) define @test_vloxseg2_nxv4f64_nxv4i64(double* %base, %index, i64 %vl) { @@ -11277,7 +11277,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11295,7 +11295,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f64.nxv4i16(,, double*, , , i64, i64) define @test_vloxseg2_nxv4f64_nxv4i16(double* %base, %index, i64 %vl) { @@ -11306,7 +11306,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f64.nxv4i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11324,7 +11324,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i64(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i64(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i64(,, double*, , , i64, i64) define @test_vloxseg2_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11335,7 +11335,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11353,7 +11353,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i32(,, double*, , , i64, i64) define @test_vloxseg2_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11364,7 +11364,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11382,7 +11382,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i16(,, double*, , , i64, i64) define @test_vloxseg2_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11393,7 +11393,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11411,7 +11411,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f64.nxv1i8(,, double*, , , i64, i64) define @test_vloxseg2_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11422,7 +11422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f64.nxv1i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11440,7 +11440,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i64(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i64(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i64(,,, double*, , , i64, i64) define @test_vloxseg3_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11451,7 +11451,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i64( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11471,7 +11471,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i32(,,, double*, , , i64, i64) define @test_vloxseg3_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11482,7 +11482,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i32( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11502,7 +11502,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i16(,,, double*, , , i64, i64) define @test_vloxseg3_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11513,7 +11513,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i16( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11533,7 +11533,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f64.nxv1i8(,,, double*, , , i64, i64) define @test_vloxseg3_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11544,7 +11544,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f64.nxv1i8( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11564,7 +11564,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i64(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i64(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i64(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11575,7 +11575,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i64( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11597,7 +11597,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i32(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11608,7 +11608,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i32( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11630,7 +11630,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i16(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11641,7 +11641,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i16( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11663,7 +11663,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f64.nxv1i8(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11674,7 +11674,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f64.nxv1i8( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11696,7 +11696,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i64(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i64(,,,,, double*, , , i64, i64) define @test_vloxseg5_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11707,7 +11707,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11730,7 +11730,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i32(,,,,, double*, , , i64, i64) define @test_vloxseg5_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11741,7 +11741,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11764,7 +11764,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i16(,,,,, double*, , , i64, i64) define @test_vloxseg5_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11775,7 +11775,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11798,7 +11798,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f64.nxv1i8(,,,,, double*, , , i64, i64) define @test_vloxseg5_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11809,7 +11809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11832,7 +11832,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i64(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i64(,,,,,, double*, , , i64, i64) define @test_vloxseg6_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11843,7 +11843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11867,7 +11867,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i32(,,,,,, double*, , , i64, i64) define @test_vloxseg6_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11878,7 +11878,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11902,7 +11902,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i16(,,,,,, double*, , , i64, i64) define @test_vloxseg6_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11913,7 +11913,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11937,7 +11937,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f64.nxv1i8(,,,,,, double*, , , i64, i64) define @test_vloxseg6_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11948,7 +11948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11972,7 +11972,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i64(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i64(,,,,,,, double*, , , i64, i64) define @test_vloxseg7_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11983,7 +11983,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12008,7 +12008,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i32(,,,,,,, double*, , , i64, i64) define @test_vloxseg7_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -12019,7 +12019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12044,7 +12044,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i16(,,,,,,, double*, , , i64, i64) define @test_vloxseg7_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -12055,7 +12055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12080,7 +12080,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f64.nxv1i8(,,,,,,, double*, , , i64, i64) define @test_vloxseg7_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -12091,7 +12091,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12116,7 +12116,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i64(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i64(,,,,,,,, double*, , , i64, i64) define @test_vloxseg8_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -12127,7 +12127,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12153,7 +12153,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i32(,,,,,,,, double*, , , i64, i64) define @test_vloxseg8_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -12164,7 +12164,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12190,7 +12190,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i16(,,,,,,,, double*, , , i64, i64) define @test_vloxseg8_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -12201,7 +12201,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12227,7 +12227,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f64.nxv1i8(,,,,,,,, double*, , , i64, i64) define @test_vloxseg8_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -12238,7 +12238,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12264,7 +12264,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i32(,, float*, , , i64, i64) define @test_vloxseg2_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12275,7 +12275,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12293,7 +12293,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i8(,, float*, , , i64, i64) define @test_vloxseg2_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12304,7 +12304,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12322,7 +12322,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i16(,, float*, , , i64, i64) define @test_vloxseg2_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12333,7 +12333,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12351,7 +12351,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i64(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i64(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f32.nxv2i64(,, float*, , , i64, i64) define @test_vloxseg2_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12362,7 +12362,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f32.nxv2i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12380,7 +12380,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i32(,,, float*, , , i64, i64) define @test_vloxseg3_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12391,7 +12391,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12411,7 +12411,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i8(,,, float*, , , i64, i64) define @test_vloxseg3_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12422,7 +12422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12442,7 +12442,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i16(,,, float*, , , i64, i64) define @test_vloxseg3_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12453,7 +12453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12473,7 +12473,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i64(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i64(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f32.nxv2i64(,,, float*, , , i64, i64) define @test_vloxseg3_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12484,7 +12484,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f32.nxv2i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12503,7 +12503,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i32(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12514,7 +12514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12536,7 +12536,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i8(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12547,7 +12547,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12569,7 +12569,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i16(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12580,7 +12580,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12602,7 +12602,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i64(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f32.nxv2i64(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12613,7 +12613,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f32.nxv2i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12634,7 +12634,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i32(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12645,7 +12645,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12668,7 +12668,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i8(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12679,7 +12679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12702,7 +12702,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i16(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12713,7 +12713,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12736,7 +12736,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i64(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f32.nxv2i64(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12747,7 +12747,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12770,7 +12770,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i32(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12781,7 +12781,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12805,7 +12805,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i8(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12816,7 +12816,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12840,7 +12840,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i16(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12851,7 +12851,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12875,7 +12875,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i64(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f32.nxv2i64(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12886,7 +12886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12910,7 +12910,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i32(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12921,7 +12921,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12946,7 +12946,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i8(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12957,7 +12957,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12982,7 +12982,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i16(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12993,7 +12993,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13018,7 +13018,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i64(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f32.nxv2i64(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -13029,7 +13029,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13054,7 +13054,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i32(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -13065,7 +13065,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13091,7 +13091,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i8(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -13102,7 +13102,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13128,7 +13128,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i16(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -13139,7 +13139,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13165,7 +13165,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i64(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f32.nxv2i64(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -13176,7 +13176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f32.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13202,7 +13202,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i64(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i64(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i64(,, half*, , , i64, i64) define @test_vloxseg2_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13213,7 +13213,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13231,7 +13231,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i32(,, half*, , , i64, i64) define @test_vloxseg2_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13242,7 +13242,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13260,7 +13260,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i16(,, half*, , , i64, i64) define @test_vloxseg2_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13271,7 +13271,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13289,7 +13289,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f16.nxv1i8(,, half*, , , i64, i64) define @test_vloxseg2_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13300,7 +13300,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f16.nxv1i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13318,7 +13318,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i64(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i64(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i64(,,, half*, , , i64, i64) define @test_vloxseg3_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13329,7 +13329,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13349,7 +13349,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i32(,,, half*, , , i64, i64) define @test_vloxseg3_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13360,7 +13360,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13380,7 +13380,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i16(,,, half*, , , i64, i64) define @test_vloxseg3_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13391,7 +13391,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13411,7 +13411,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f16.nxv1i8(,,, half*, , , i64, i64) define @test_vloxseg3_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13422,7 +13422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f16.nxv1i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13442,7 +13442,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i64(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i64(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13453,7 +13453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13475,7 +13475,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i32(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13486,7 +13486,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13508,7 +13508,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i16(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13519,7 +13519,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13541,7 +13541,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f16.nxv1i8(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13552,7 +13552,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f16.nxv1i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13574,7 +13574,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i64(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13585,7 +13585,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13608,7 +13608,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i32(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13619,7 +13619,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13642,7 +13642,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i16(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13653,7 +13653,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13676,7 +13676,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f16.nxv1i8(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13687,7 +13687,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13710,7 +13710,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i64(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13721,7 +13721,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13745,7 +13745,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i32(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13756,7 +13756,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13780,7 +13780,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i16(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13791,7 +13791,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13815,7 +13815,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f16.nxv1i8(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13826,7 +13826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13850,7 +13850,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i64(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13861,7 +13861,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13886,7 +13886,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i32(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13897,7 +13897,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13922,7 +13922,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i16(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13933,7 +13933,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13958,7 +13958,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f16.nxv1i8(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13969,7 +13969,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13994,7 +13994,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i64(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -14005,7 +14005,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14031,7 +14031,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i32(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -14042,7 +14042,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14068,7 +14068,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i16(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -14079,7 +14079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14105,7 +14105,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f16.nxv1i8(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -14116,7 +14116,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14142,7 +14142,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i64(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i64(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i64(,, float*, , , i64, i64) define @test_vloxseg2_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14153,7 +14153,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14171,7 +14171,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i32(,, float*, , , i64, i64) define @test_vloxseg2_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14182,7 +14182,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14200,7 +14200,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i16(,, float*, , , i64, i64) define @test_vloxseg2_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14211,7 +14211,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14229,7 +14229,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv1f32.nxv1i8(,, float*, , , i64, i64) define @test_vloxseg2_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14240,7 +14240,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv1f32.nxv1i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14258,7 +14258,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i64(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i64(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i64(,,, float*, , , i64, i64) define @test_vloxseg3_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14269,7 +14269,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14289,7 +14289,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i32(,,, float*, , , i64, i64) define @test_vloxseg3_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14300,7 +14300,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14320,7 +14320,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i16(,,, float*, , , i64, i64) define @test_vloxseg3_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14331,7 +14331,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14351,7 +14351,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv1f32.nxv1i8(,,, float*, , , i64, i64) define @test_vloxseg3_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14362,7 +14362,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv1f32.nxv1i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14382,7 +14382,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i64(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i64(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14393,7 +14393,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14415,7 +14415,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i32(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14426,7 +14426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14448,7 +14448,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i16(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14459,7 +14459,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14481,7 +14481,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv1f32.nxv1i8(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14492,7 +14492,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv1f32.nxv1i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14514,7 +14514,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i64(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i64(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14525,7 +14525,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14548,7 +14548,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i32(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14559,7 +14559,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14582,7 +14582,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i16(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14593,7 +14593,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14616,7 +14616,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv1f32.nxv1i8(,,,,, float*, , , i64, i64) define @test_vloxseg5_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14627,7 +14627,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14650,7 +14650,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i64(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i64(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14661,7 +14661,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14685,7 +14685,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i32(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14696,7 +14696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14720,7 +14720,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i16(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14731,7 +14731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14755,7 +14755,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv1f32.nxv1i8(,,,,,, float*, , , i64, i64) define @test_vloxseg6_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14766,7 +14766,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14790,7 +14790,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i64(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i64(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14801,7 +14801,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14826,7 +14826,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i32(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14837,7 +14837,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14862,7 +14862,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i16(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14873,7 +14873,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14898,7 +14898,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv1f32.nxv1i8(,,,,,,, float*, , , i64, i64) define @test_vloxseg7_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14909,7 +14909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14934,7 +14934,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i64(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i64(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14945,7 +14945,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14971,7 +14971,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i32(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14982,7 +14982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15008,7 +15008,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i16(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -15019,7 +15019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15045,7 +15045,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv1f32.nxv1i8(,,,,,,,, float*, , , i64, i64) define @test_vloxseg8_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -15056,7 +15056,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv1f32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15082,7 +15082,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i16(,, half*, , , i64, i64) define @test_vloxseg2_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15093,7 +15093,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15111,7 +15111,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i8(,, half*, , , i64, i64) define @test_vloxseg2_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15122,7 +15122,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15140,7 +15140,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i64(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i64(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i64(,, half*, , , i64, i64) define @test_vloxseg2_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15151,7 +15151,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15169,7 +15169,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f16.nxv8i32(,, half*, , , i64, i64) define @test_vloxseg2_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15180,7 +15180,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f16.nxv8i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15198,7 +15198,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i16(,,, half*, , , i64, i64) define @test_vloxseg3_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15209,7 +15209,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15229,7 +15229,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i8(,,, half*, , , i64, i64) define @test_vloxseg3_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15240,7 +15240,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15260,7 +15260,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i64(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i64(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i64(,,, half*, , , i64, i64) define @test_vloxseg3_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15271,7 +15271,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15290,7 +15290,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv8f16.nxv8i32(,,, half*, , , i64, i64) define @test_vloxseg3_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15301,7 +15301,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv8f16.nxv8i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15320,7 +15320,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i16(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15331,7 +15331,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15353,7 +15353,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i8(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15364,7 +15364,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15386,7 +15386,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i64(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i64(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15397,7 +15397,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15417,7 +15417,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv8f16.nxv8i32(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15428,7 +15428,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv8f16.nxv8i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15449,7 +15449,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i16(,, float*, , , i64, i64) define @test_vloxseg2_nxv8f32_nxv8i16(float* %base, %index, i64 %vl) { @@ -15460,7 +15460,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15478,7 +15478,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i8(,, float*, , , i64, i64) define @test_vloxseg2_nxv8f32_nxv8i8(float* %base, %index, i64 %vl) { @@ -15489,7 +15489,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15507,7 +15507,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i64(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i64(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i64(,, float*, , , i64, i64) define @test_vloxseg2_nxv8f32_nxv8i64(float* %base, %index, i64 %vl) { @@ -15518,7 +15518,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15536,7 +15536,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv8f32.nxv8i32(,, float*, , , i64, i64) define @test_vloxseg2_nxv8f32_nxv8i32(float* %base, %index, i64 %vl) { @@ -15547,7 +15547,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv8f32.nxv8i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15565,7 +15565,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i32(,, double*, , , i64, i64) define @test_vloxseg2_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15576,7 +15576,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15594,7 +15594,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i8(,, double*, , , i64, i64) define @test_vloxseg2_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15605,7 +15605,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15623,7 +15623,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i16(,, double*, , , i64, i64) define @test_vloxseg2_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15634,7 +15634,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15652,7 +15652,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i64(double*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i64(,, double*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f64.nxv2i64(,, double*, , , i64, i64) define @test_vloxseg2_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15663,7 +15663,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f64.nxv2i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15681,7 +15681,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i32(,,, double*, , , i64, i64) define @test_vloxseg3_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15692,7 +15692,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i32( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15712,7 +15712,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i8(,,, double*, , , i64, i64) define @test_vloxseg3_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15723,7 +15723,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i8( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15743,7 +15743,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i16(,,, double*, , , i64, i64) define @test_vloxseg3_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15754,7 +15754,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i16( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15774,7 +15774,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i64(double*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i64(,,, double*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f64.nxv2i64(,,, double*, , , i64, i64) define @test_vloxseg3_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15785,7 +15785,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f64.nxv2i64( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15805,7 +15805,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i32(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15816,7 +15816,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i32( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15838,7 +15838,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i8(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15849,7 +15849,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i8( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15871,7 +15871,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i16(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15882,7 +15882,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i16( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15904,7 +15904,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i64(double*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i64(,,,, double*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f64.nxv2i64(,,,, double*, , , i64, i64) define @test_vloxseg4_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15915,7 +15915,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f64.nxv2i64( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15937,7 +15937,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i32(,, half*, , , i64, i64) define @test_vloxseg2_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -15948,7 +15948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15966,7 +15966,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i8(,, half*, , , i64, i64) define @test_vloxseg2_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -15977,7 +15977,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15995,7 +15995,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i64(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i64(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i64(,, half*, , , i64, i64) define @test_vloxseg2_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16006,7 +16006,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16024,7 +16024,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f16.nxv4i16(,, half*, , , i64, i64) define @test_vloxseg2_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16035,7 +16035,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f16.nxv4i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16053,7 +16053,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i32(,,, half*, , , i64, i64) define @test_vloxseg3_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16064,7 +16064,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16083,7 +16083,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i8(,,, half*, , , i64, i64) define @test_vloxseg3_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16094,7 +16094,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16114,7 +16114,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i64(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i64(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i64(,,, half*, , , i64, i64) define @test_vloxseg3_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16125,7 +16125,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16144,7 +16144,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f16.nxv4i16(,,, half*, , , i64, i64) define @test_vloxseg3_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16155,7 +16155,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f16.nxv4i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16175,7 +16175,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i32(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16186,7 +16186,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16207,7 +16207,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i8(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16218,7 +16218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16240,7 +16240,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i64(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i64(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16251,7 +16251,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16271,7 +16271,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f16.nxv4i16(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16282,7 +16282,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f16.nxv4i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16304,7 +16304,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i32(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16315,7 +16315,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16338,7 +16338,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i8(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16349,7 +16349,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16372,7 +16372,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i64(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16383,7 +16383,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16404,7 +16404,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv4f16.nxv4i16(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16415,7 +16415,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16438,7 +16438,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i32(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16449,7 +16449,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16473,7 +16473,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i8(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16484,7 +16484,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16508,7 +16508,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i64(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16519,7 +16519,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16542,7 +16542,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv4f16.nxv4i16(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16553,7 +16553,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16577,7 +16577,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i32(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16588,7 +16588,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16613,7 +16613,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i8(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16624,7 +16624,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16649,7 +16649,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i64(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16660,7 +16660,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16685,7 +16685,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv4f16.nxv4i16(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16696,7 +16696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16721,7 +16721,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i32(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16732,7 +16732,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16758,7 +16758,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i8(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16769,7 +16769,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16795,7 +16795,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i64(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16806,7 +16806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16832,7 +16832,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv4f16.nxv4i16(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16843,7 +16843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv4f16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16869,7 +16869,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i32(,, half*, , , i64, i64) define @test_vloxseg2_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -16880,7 +16880,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16898,7 +16898,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i8(,, half*, , , i64, i64) define @test_vloxseg2_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -16909,7 +16909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16927,7 +16927,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i16(,, half*, , , i64, i64) define @test_vloxseg2_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -16938,7 +16938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16956,7 +16956,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i64(half*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i64(,, half*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv2f16.nxv2i64(,, half*, , , i64, i64) define @test_vloxseg2_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -16967,7 +16967,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv2f16.nxv2i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16985,7 +16985,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i32(,,, half*, , , i64, i64) define @test_vloxseg3_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -16996,7 +16996,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17016,7 +17016,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i8(,,, half*, , , i64, i64) define @test_vloxseg3_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17027,7 +17027,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17047,7 +17047,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i16(,,, half*, , , i64, i64) define @test_vloxseg3_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17058,7 +17058,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17078,7 +17078,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i64(half*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i64(,,, half*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv2f16.nxv2i64(,,, half*, , , i64, i64) define @test_vloxseg3_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17089,7 +17089,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv2f16.nxv2i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17108,7 +17108,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i32(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17119,7 +17119,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17141,7 +17141,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i8(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17152,7 +17152,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17174,7 +17174,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i16(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17185,7 +17185,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17207,7 +17207,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i64(half*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv2f16.nxv2i64(,,,, half*, , , i64, i64) define @test_vloxseg4_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17218,7 +17218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv2f16.nxv2i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17239,7 +17239,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i32(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17250,7 +17250,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17273,7 +17273,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i8(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17284,7 +17284,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17307,7 +17307,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i16(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17318,7 +17318,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17341,7 +17341,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vloxseg5.mask.nxv2f16.nxv2i64(,,,,, half*, , , i64, i64) define @test_vloxseg5_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17352,7 +17352,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vloxseg5.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17375,7 +17375,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i32(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17386,7 +17386,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17410,7 +17410,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i8(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17421,7 +17421,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17445,7 +17445,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i16(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17456,7 +17456,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17480,7 +17480,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vloxseg6.mask.nxv2f16.nxv2i64(,,,,,, half*, , , i64, i64) define @test_vloxseg6_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17491,7 +17491,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vloxseg6.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17515,7 +17515,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i32(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17526,7 +17526,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17551,7 +17551,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i8(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17562,7 +17562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17587,7 +17587,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i16(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17598,7 +17598,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17623,7 +17623,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vloxseg7.mask.nxv2f16.nxv2i64(,,,,,,, half*, , , i64, i64) define @test_vloxseg7_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17634,7 +17634,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vloxseg7.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17659,7 +17659,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i32(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17670,7 +17670,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17696,7 +17696,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i8(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17707,7 +17707,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17733,7 +17733,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i16(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17744,7 +17744,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17770,7 +17770,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vloxseg8.mask.nxv2f16.nxv2i64(,,,,,,,, half*, , , i64, i64) define @test_vloxseg8_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17781,7 +17781,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vloxseg8.nxv2f16.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17807,7 +17807,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i32(,, float*, , , i64, i64) define @test_vloxseg2_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -17818,7 +17818,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17836,7 +17836,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i8(,, float*, , , i64, i64) define @test_vloxseg2_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -17847,7 +17847,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17865,7 +17865,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i64(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i64(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i64(,, float*, , , i64, i64) define @test_vloxseg2_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -17876,7 +17876,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17894,7 +17894,7 @@ ret %1 } -declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(float*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(,, float*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv4f32.nxv4i16(,, float*, , , i64, i64) define @test_vloxseg2_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -17905,7 +17905,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv4f32.nxv4i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17923,7 +17923,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i32(,,, float*, , , i64, i64) define @test_vloxseg3_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -17934,7 +17934,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17954,7 +17954,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i8(,,, float*, , , i64, i64) define @test_vloxseg3_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -17965,7 +17965,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17985,7 +17985,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i64(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i64(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i64(,,, float*, , , i64, i64) define @test_vloxseg3_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -17996,7 +17996,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -18015,7 +18015,7 @@ ret %1 } -declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(float*, , i64) +declare {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(,,, float*, , i64) declare {,,} @llvm.riscv.vloxseg3.mask.nxv4f32.nxv4i16(,,, float*, , , i64, i64) define @test_vloxseg3_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -18026,7 +18026,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vloxseg3.nxv4f32.nxv4i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -18046,7 +18046,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i32(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -18057,7 +18057,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18079,7 +18079,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i8(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -18090,7 +18090,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18112,7 +18112,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i64(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i64(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -18123,7 +18123,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18144,7 +18144,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(float*, , i64) +declare {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vloxseg4.mask.nxv4f32.nxv4i16(,,,, float*, , , i64, i64) define @test_vloxseg4_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -18155,7 +18155,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vloxseg4.nxv4f32.nxv4i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i32) +declare {,} @llvm.riscv.vlseg2.nxv16i16(,, i16* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv16i16(,, i16*, , i32, i32) define @test_vlseg2_nxv16i16(i16* %base, i32 %vl) { @@ -12,7 +12,7 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -26,14 +26,14 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16i16( %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1i8(,, i8*, , i32, i32) define @test_vlseg2_nxv1i8(i8* %base, i32 %vl) { @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -57,14 +57,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i8(i8* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1i8(,,, i8* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i8(,,, i8*, , i32, i32) define @test_vlseg3_nxv1i8(i8* %base, i32 %vl) { @@ -74,7 +74,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -89,14 +89,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i8( %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1i8(,,,, i8* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i8(,,,, i8*, , i32, i32) define @test_vlseg4_nxv1i8(i8* %base, i32 %vl) { @@ -106,7 +106,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -122,14 +122,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i8( %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i8(,,,,, i8* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i8(,,,,, i8*, , i32, i32) define @test_vlseg5_nxv1i8(i8* %base, i32 %vl) { @@ -139,7 +139,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -156,14 +156,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i8( %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i8(,,,,,, i8* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i8(,,,,,, i8*, , i32, i32) define @test_vlseg6_nxv1i8(i8* %base, i32 %vl) { @@ -173,7 +173,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -191,14 +191,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(,,,,,,, i8* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7_nxv1i8(i8* %base, i32 %vl) { @@ -208,7 +208,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -227,14 +227,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(,,,,,,,, i8* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8_nxv1i8(i8* %base, i32 %vl) { @@ -244,7 +244,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -264,14 +264,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv16i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv16i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv16i8(,, i8*, , i32, i32) define @test_vlseg2_nxv16i8(i8* %base, i32 %vl) { @@ -281,7 +281,7 @@ ; CHECK-NEXT: vlseg2e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -295,14 +295,14 @@ ; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv16i8(i8* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv16i8(,,, i8* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv16i8(,,, i8*, , i32, i32) define @test_vlseg3_nxv16i8(i8* %base, i32 %vl) { @@ -312,7 +312,7 @@ ; CHECK-NEXT: vlseg3e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -327,14 +327,14 @@ ; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv16i8( %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv16i8(,,,, i8* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv16i8(,,,, i8*, , i32, i32) define @test_vlseg4_nxv16i8(i8* %base, i32 %vl) { @@ -344,7 +344,7 @@ ; CHECK-NEXT: vlseg4e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -360,14 +360,14 @@ ; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv16i8( %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i32(i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2i32(,, i32* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2i32(,, i32*, , i32, i32) define @test_vlseg2_nxv2i32(i32* %base, i32 %vl) { @@ -377,7 +377,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -391,14 +391,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i32( %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i32(i32* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2i32(,,, i32* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i32(,,, i32*, , i32, i32) define @test_vlseg3_nxv2i32(i32* %base, i32 %vl) { @@ -408,7 +408,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -423,14 +423,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i32( %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2i32(,,,, i32* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i32(,,,, i32*, , i32, i32) define @test_vlseg4_nxv2i32(i32* %base, i32 %vl) { @@ -440,7 +440,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -456,14 +456,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i32( %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i32(,,,,, i32* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i32(,,,,, i32*, , i32, i32) define @test_vlseg5_nxv2i32(i32* %base, i32 %vl) { @@ -473,7 +473,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -490,14 +490,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i32( %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i32(,,,,,, i32* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i32(,,,,,, i32*, , i32, i32) define @test_vlseg6_nxv2i32(i32* %base, i32 %vl) { @@ -507,7 +507,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -525,14 +525,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i32( %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(,,,,,,, i32* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i32(,,,,,,, i32*, , i32, i32) define @test_vlseg7_nxv2i32(i32* %base, i32 %vl) { @@ -542,7 +542,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -561,14 +561,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(,,,,,,,, i32* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i32(,,,,,,,, i32*, , i32, i32) define @test_vlseg8_nxv2i32(i32* %base, i32 %vl) { @@ -578,7 +578,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -598,14 +598,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i16(i16* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4i16(,, i16* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4i16(,, i16*, , i32, i32) define @test_vlseg2_nxv4i16(i16* %base, i32 %vl) { @@ -615,7 +615,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -629,14 +629,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i16( %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i16(i16* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4i16(,,, i16* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i16(,,, i16*, , i32, i32) define @test_vlseg3_nxv4i16(i16* %base, i32 %vl) { @@ -646,7 +646,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -661,14 +661,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i16( %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv4i16(,,,, i16* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i16(,,,, i16*, , i32, i32) define @test_vlseg4_nxv4i16(i16* %base, i32 %vl) { @@ -678,7 +678,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -694,14 +694,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i16( %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv4i16(,,,,, i16* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4i16(,,,,, i16*, , i32, i32) define @test_vlseg5_nxv4i16(i16* %base, i32 %vl) { @@ -711,7 +711,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -728,14 +728,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4i16( %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4i16(,,,,,, i16* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i16(,,,,,, i16*, , i32, i32) define @test_vlseg6_nxv4i16(i16* %base, i32 %vl) { @@ -745,7 +745,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -763,14 +763,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(,,,,,,, i16* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7_nxv4i16(i16* %base, i32 %vl) { @@ -780,7 +780,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -799,14 +799,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(,,,,,,,, i16* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8_nxv4i16(i16* %base, i32 %vl) { @@ -816,7 +816,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -836,14 +836,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i32(i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1i32(,, i32* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1i32(,, i32*, , i32, i32) define @test_vlseg2_nxv1i32(i32* %base, i32 %vl) { @@ -853,7 +853,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -867,14 +867,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i32( %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i32(i32* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1i32(,,, i32* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i32(,,, i32*, , i32, i32) define @test_vlseg3_nxv1i32(i32* %base, i32 %vl) { @@ -884,7 +884,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -899,14 +899,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i32( %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1i32(,,,, i32* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i32(,,,, i32*, , i32, i32) define @test_vlseg4_nxv1i32(i32* %base, i32 %vl) { @@ -916,7 +916,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -932,14 +932,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i32( %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i32(,,,,, i32* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i32(,,,,, i32*, , i32, i32) define @test_vlseg5_nxv1i32(i32* %base, i32 %vl) { @@ -949,7 +949,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -966,14 +966,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i32( %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i32(,,,,,, i32* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i32(,,,,,, i32*, , i32, i32) define @test_vlseg6_nxv1i32(i32* %base, i32 %vl) { @@ -983,7 +983,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1001,14 +1001,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i32( %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(,,,,,,, i32* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i32(,,,,,,, i32*, , i32, i32) define @test_vlseg7_nxv1i32(i32* %base, i32 %vl) { @@ -1018,7 +1018,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1037,14 +1037,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(,,,,,,,, i32* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i32(,,,,,,,, i32*, , i32, i32) define @test_vlseg8_nxv1i32(i32* %base, i32 %vl) { @@ -1054,7 +1054,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1074,14 +1074,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i16(i16* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8i16(,, i16* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv8i16(,, i16*, , i32, i32) define @test_vlseg2_nxv8i16(i16* %base, i32 %vl) { @@ -1091,7 +1091,7 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1105,14 +1105,14 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i16( %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8i16(i16* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv8i16(,,, i16* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv8i16(,,, i16*, , i32, i32) define @test_vlseg3_nxv8i16(i16* %base, i32 %vl) { @@ -1122,7 +1122,7 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1137,14 +1137,14 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8i16( %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv8i16(,,,, i16* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8i16(,,,, i16*, , i32, i32) define @test_vlseg4_nxv8i16(i16* %base, i32 %vl) { @@ -1154,7 +1154,7 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1170,14 +1170,14 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8i16( %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv8i8(,, i8*, , i32, i32) define @test_vlseg2_nxv8i8(i8* %base, i32 %vl) { @@ -1187,7 +1187,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1201,14 +1201,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8i8(i8* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv8i8(,,, i8* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv8i8(,,, i8*, , i32, i32) define @test_vlseg3_nxv8i8(i8* %base, i32 %vl) { @@ -1218,7 +1218,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1233,14 +1233,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8i8( %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv8i8(,,,, i8* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8i8(,,,, i8*, , i32, i32) define @test_vlseg4_nxv8i8(i8* %base, i32 %vl) { @@ -1250,7 +1250,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1266,14 +1266,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8i8( %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv8i8(,,,,, i8* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv8i8(,,,,, i8*, , i32, i32) define @test_vlseg5_nxv8i8(i8* %base, i32 %vl) { @@ -1283,7 +1283,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1300,14 +1300,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv8i8( %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv8i8(,,,,,, i8* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv8i8(,,,,,, i8*, , i32, i32) define @test_vlseg6_nxv8i8(i8* %base, i32 %vl) { @@ -1317,7 +1317,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1335,14 +1335,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv8i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(,,,,,,, i8* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv8i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7_nxv8i8(i8* %base, i32 %vl) { @@ -1352,7 +1352,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1371,14 +1371,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(,,,,,,,, i8* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv8i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8_nxv8i8(i8* %base, i32 %vl) { @@ -1388,7 +1388,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1408,14 +1408,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i32(i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8i32(,, i32* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv8i32(,, i32*, , i32, i32) define @test_vlseg2_nxv8i32(i32* %base, i32 %vl) { @@ -1425,7 +1425,7 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1439,14 +1439,14 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i32( %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4i8(,, i8*, , i32, i32) define @test_vlseg2_nxv4i8(i8* %base, i32 %vl) { @@ -1456,7 +1456,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1470,14 +1470,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i8(i8* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4i8(,,, i8* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i8(,,, i8*, , i32, i32) define @test_vlseg3_nxv4i8(i8* %base, i32 %vl) { @@ -1487,7 +1487,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1502,14 +1502,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i8( %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv4i8(,,,, i8* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i8(,,,, i8*, , i32, i32) define @test_vlseg4_nxv4i8(i8* %base, i32 %vl) { @@ -1519,7 +1519,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1535,14 +1535,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i8( %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv4i8(,,,,, i8* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4i8(,,,,, i8*, , i32, i32) define @test_vlseg5_nxv4i8(i8* %base, i32 %vl) { @@ -1552,7 +1552,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1569,14 +1569,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4i8( %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4i8(,,,,,, i8* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i8(,,,,,, i8*, , i32, i32) define @test_vlseg6_nxv4i8(i8* %base, i32 %vl) { @@ -1586,7 +1586,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1604,14 +1604,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(,,,,,,, i8* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7_nxv4i8(i8* %base, i32 %vl) { @@ -1621,7 +1621,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1640,14 +1640,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(,,,,,,,, i8* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8_nxv4i8(i8* %base, i32 %vl) { @@ -1657,7 +1657,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1677,14 +1677,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i16(i16* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1i16(,, i16* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1i16(,, i16*, , i32, i32) define @test_vlseg2_nxv1i16(i16* %base, i32 %vl) { @@ -1694,7 +1694,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1708,14 +1708,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i16( %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i16(i16* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1i16(,,, i16* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i16(,,, i16*, , i32, i32) define @test_vlseg3_nxv1i16(i16* %base, i32 %vl) { @@ -1725,7 +1725,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1740,14 +1740,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i16( %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1i16(,,,, i16* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i16(,,,, i16*, , i32, i32) define @test_vlseg4_nxv1i16(i16* %base, i32 %vl) { @@ -1757,7 +1757,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1773,14 +1773,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i16( %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i16(,,,,, i16* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i16(,,,,, i16*, , i32, i32) define @test_vlseg5_nxv1i16(i16* %base, i32 %vl) { @@ -1790,7 +1790,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1807,14 +1807,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i16( %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i16(,,,,,, i16* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i16(,,,,,, i16*, , i32, i32) define @test_vlseg6_nxv1i16(i16* %base, i32 %vl) { @@ -1824,7 +1824,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1842,14 +1842,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(,,,,,,, i16* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7_nxv1i16(i16* %base, i32 %vl) { @@ -1859,7 +1859,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1878,14 +1878,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(,,,,,,,, i16* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8_nxv1i16(i16* %base, i32 %vl) { @@ -1895,7 +1895,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1915,14 +1915,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv32i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv32i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv32i8(,, i8*, , i32, i32) define @test_vlseg2_nxv32i8(i8* %base, i32 %vl) { @@ -1932,7 +1932,7 @@ ; CHECK-NEXT: vlseg2e8.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1946,14 +1946,14 @@ ; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv32i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i8(i8* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2i8(,, i8* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2i8(,, i8*, , i32, i32) define @test_vlseg2_nxv2i8(i8* %base, i32 %vl) { @@ -1963,7 +1963,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1977,14 +1977,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i8( %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i8(i8* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2i8(,,, i8* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i8(,,, i8*, , i32, i32) define @test_vlseg3_nxv2i8(i8* %base, i32 %vl) { @@ -1994,7 +1994,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2009,14 +2009,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i8( %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2i8(,,,, i8* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i8(,,,, i8*, , i32, i32) define @test_vlseg4_nxv2i8(i8* %base, i32 %vl) { @@ -2026,7 +2026,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2042,14 +2042,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i8( %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i8(,,,,, i8* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i8(,,,,, i8*, , i32, i32) define @test_vlseg5_nxv2i8(i8* %base, i32 %vl) { @@ -2059,7 +2059,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2076,14 +2076,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i8( %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i8(,,,,,, i8* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i8(,,,,,, i8*, , i32, i32) define @test_vlseg6_nxv2i8(i8* %base, i32 %vl) { @@ -2093,7 +2093,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2111,14 +2111,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(,,,,,,, i8* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7_nxv2i8(i8* %base, i32 %vl) { @@ -2128,7 +2128,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2147,14 +2147,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(,,,,,,,, i8* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8_nxv2i8(i8* %base, i32 %vl) { @@ -2164,7 +2164,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2184,14 +2184,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i16(i16* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2i16(,, i16* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2i16(,, i16*, , i32, i32) define @test_vlseg2_nxv2i16(i16* %base, i32 %vl) { @@ -2201,7 +2201,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2215,14 +2215,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i16( %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i16(i16* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2i16(,,, i16* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i16(,,, i16*, , i32, i32) define @test_vlseg3_nxv2i16(i16* %base, i32 %vl) { @@ -2232,7 +2232,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2247,14 +2247,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i16( %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2i16(,,,, i16* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i16(,,,, i16*, , i32, i32) define @test_vlseg4_nxv2i16(i16* %base, i32 %vl) { @@ -2264,7 +2264,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2280,14 +2280,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i16( %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i16(,,,,, i16* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i16(,,,,, i16*, , i32, i32) define @test_vlseg5_nxv2i16(i16* %base, i32 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2314,14 +2314,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i16( %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i16(,,,,,, i16* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i16(,,,,,, i16*, , i32, i32) define @test_vlseg6_nxv2i16(i16* %base, i32 %vl) { @@ -2331,7 +2331,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2349,14 +2349,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(,,,,,,, i16* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7_nxv2i16(i16* %base, i32 %vl) { @@ -2366,7 +2366,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2385,14 +2385,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(,,,,,,,, i16* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8_nxv2i16(i16* %base, i32 %vl) { @@ -2402,7 +2402,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2422,14 +2422,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i32(i32* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4i32(,, i32* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4i32(,, i32*, , i32, i32) define @test_vlseg2_nxv4i32(i32* %base, i32 %vl) { @@ -2439,7 +2439,7 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2453,14 +2453,14 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i32( %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i32(i32* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4i32(,,, i32* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i32(,,, i32*, , i32, i32) define @test_vlseg3_nxv4i32(i32* %base, i32 %vl) { @@ -2470,7 +2470,7 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2485,14 +2485,14 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i32( %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv4i32(,,,, i32* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i32(,,,, i32*, , i32, i32) define @test_vlseg4_nxv4i32(i32* %base, i32 %vl) { @@ -2502,7 +2502,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2518,14 +2518,14 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i32( %1, %1, %1, %1, i32* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv16f16(half* , i32) +declare {,} @llvm.riscv.vlseg2.nxv16f16(,, half* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv16f16(,, half*, , i32, i32) define @test_vlseg2_nxv16f16(half* %base, i32 %vl) { @@ -2535,7 +2535,7 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2549,14 +2549,14 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16f16( %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f64(double* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4f64(,, double* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4f64(,, double*, , i32, i32) define @test_vlseg2_nxv4f64(double* %base, i32 %vl) { @@ -2566,7 +2566,7 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2580,14 +2580,14 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f64( %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f64(double* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1f64(,, double* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1f64(,, double*, , i32, i32) define @test_vlseg2_nxv1f64(double* %base, i32 %vl) { @@ -2597,7 +2597,7 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2611,14 +2611,14 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f64( %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f64(double* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1f64(,,, double* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f64(,,, double*, , i32, i32) define @test_vlseg3_nxv1f64(double* %base, i32 %vl) { @@ -2628,7 +2628,7 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2643,14 +2643,14 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f64( %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f64(double* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1f64(,,,, double* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f64(,,,, double*, , i32, i32) define @test_vlseg4_nxv1f64(double* %base, i32 %vl) { @@ -2660,7 +2660,7 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2676,14 +2676,14 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f64( %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f64(,,,,, double* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f64(,,,,, double*, , i32, i32) define @test_vlseg5_nxv1f64(double* %base, i32 %vl) { @@ -2693,7 +2693,7 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2710,14 +2710,14 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f64( %1, %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f64(,,,,,, double* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f64(,,,,,, double*, , i32, i32) define @test_vlseg6_nxv1f64(double* %base, i32 %vl) { @@ -2727,7 +2727,7 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2745,14 +2745,14 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f64( %1, %1, %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(,,,,,,, double* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f64(,,,,,,, double*, , i32, i32) define @test_vlseg7_nxv1f64(double* %base, i32 %vl) { @@ -2762,7 +2762,7 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2781,14 +2781,14 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(,,,,,,,, double* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f64(,,,,,,,, double*, , i32, i32) define @test_vlseg8_nxv1f64(double* %base, i32 %vl) { @@ -2798,7 +2798,7 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2818,14 +2818,14 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f32(float* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2f32(,, float* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2f32(,, float*, , i32, i32) define @test_vlseg2_nxv2f32(float* %base, i32 %vl) { @@ -2835,7 +2835,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2849,14 +2849,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f32( %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f32(float* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2f32(,,, float* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f32(,,, float*, , i32, i32) define @test_vlseg3_nxv2f32(float* %base, i32 %vl) { @@ -2866,7 +2866,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2881,14 +2881,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f32( %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f32(float* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2f32(,,,, float* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f32(,,,, float*, , i32, i32) define @test_vlseg4_nxv2f32(float* %base, i32 %vl) { @@ -2898,7 +2898,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2914,14 +2914,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f32( %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv2f32(,,,,, float* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2f32(,,,,, float*, , i32, i32) define @test_vlseg5_nxv2f32(float* %base, i32 %vl) { @@ -2931,7 +2931,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2948,14 +2948,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2f32( %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2f32(,,,,,, float* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f32(,,,,,, float*, , i32, i32) define @test_vlseg6_nxv2f32(float* %base, i32 %vl) { @@ -2965,7 +2965,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2983,14 +2983,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f32( %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(,,,,,,, float* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f32(,,,,,,, float*, , i32, i32) define @test_vlseg7_nxv2f32(float* %base, i32 %vl) { @@ -3000,7 +3000,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3019,14 +3019,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(,,,,,,,, float* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f32(,,,,,,,, float*, , i32, i32) define @test_vlseg8_nxv2f32(float* %base, i32 %vl) { @@ -3036,7 +3036,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3056,14 +3056,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f16(half* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1f16(,, half* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1f16(,, half*, , i32, i32) define @test_vlseg2_nxv1f16(half* %base, i32 %vl) { @@ -3073,7 +3073,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3087,14 +3087,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f16( %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f16(half* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1f16(,,, half* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f16(,,, half*, , i32, i32) define @test_vlseg3_nxv1f16(half* %base, i32 %vl) { @@ -3104,7 +3104,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3119,14 +3119,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f16( %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f16(half* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1f16(,,,, half* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f16(,,,, half*, , i32, i32) define @test_vlseg4_nxv1f16(half* %base, i32 %vl) { @@ -3136,7 +3136,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3152,14 +3152,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f16( %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f16(,,,,, half* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f16(,,,,, half*, , i32, i32) define @test_vlseg5_nxv1f16(half* %base, i32 %vl) { @@ -3169,7 +3169,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3186,14 +3186,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f16( %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f16(,,,,,, half* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f16(,,,,,, half*, , i32, i32) define @test_vlseg6_nxv1f16(half* %base, i32 %vl) { @@ -3203,7 +3203,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3221,14 +3221,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(,,,,,,, half* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f16(,,,,,,, half*, , i32, i32) define @test_vlseg7_nxv1f16(half* %base, i32 %vl) { @@ -3238,7 +3238,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3257,14 +3257,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(,,,,,,,, half* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8_nxv1f16(half* %base, i32 %vl) { @@ -3274,7 +3274,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3294,14 +3294,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f32(float* , i32) +declare {,} @llvm.riscv.vlseg2.nxv1f32(,, float* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv1f32(,, float*, , i32, i32) define @test_vlseg2_nxv1f32(float* %base, i32 %vl) { @@ -3311,7 +3311,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3325,14 +3325,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f32( %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f32(float* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv1f32(,,, float* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f32(,,, float*, , i32, i32) define @test_vlseg3_nxv1f32(float* %base, i32 %vl) { @@ -3342,7 +3342,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3357,14 +3357,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f32( %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f32(float* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv1f32(,,,, float* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f32(,,,, float*, , i32, i32) define @test_vlseg4_nxv1f32(float* %base, i32 %vl) { @@ -3374,7 +3374,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3390,14 +3390,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f32( %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f32(,,,,, float* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f32(,,,,, float*, , i32, i32) define @test_vlseg5_nxv1f32(float* %base, i32 %vl) { @@ -3407,7 +3407,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3424,14 +3424,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f32( %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f32(,,,,,, float* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f32(,,,,,, float*, , i32, i32) define @test_vlseg6_nxv1f32(float* %base, i32 %vl) { @@ -3441,7 +3441,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3459,14 +3459,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f32( %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(,,,,,,, float* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f32(,,,,,,, float*, , i32, i32) define @test_vlseg7_nxv1f32(float* %base, i32 %vl) { @@ -3476,7 +3476,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3495,14 +3495,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(,,,,,,,, float* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f32(,,,,,,,, float*, , i32, i32) define @test_vlseg8_nxv1f32(float* %base, i32 %vl) { @@ -3512,7 +3512,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3532,14 +3532,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8f16(half* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8f16(,, half* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv8f16(,, half*, , i32, i32) define @test_vlseg2_nxv8f16(half* %base, i32 %vl) { @@ -3549,7 +3549,7 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3563,14 +3563,14 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8f16( %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8f16(half* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv8f16(,,, half* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv8f16(,,, half*, , i32, i32) define @test_vlseg3_nxv8f16(half* %base, i32 %vl) { @@ -3580,7 +3580,7 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3595,14 +3595,14 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8f16( %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8f16(half* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv8f16(,,,, half* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8f16(,,,, half*, , i32, i32) define @test_vlseg4_nxv8f16(half* %base, i32 %vl) { @@ -3612,7 +3612,7 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3628,14 +3628,14 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8f16( %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8f32(float* , i32) +declare {,} @llvm.riscv.vlseg2.nxv8f32(,, float* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv8f32(,, float*, , i32, i32) define @test_vlseg2_nxv8f32(float* %base, i32 %vl) { @@ -3645,7 +3645,7 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3659,14 +3659,14 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8f32( %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f64(double* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2f64(,, double* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2f64(,, double*, , i32, i32) define @test_vlseg2_nxv2f64(double* %base, i32 %vl) { @@ -3676,7 +3676,7 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3690,14 +3690,14 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f64( %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f64(double* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2f64(,,, double* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f64(,,, double*, , i32, i32) define @test_vlseg3_nxv2f64(double* %base, i32 %vl) { @@ -3707,7 +3707,7 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3722,14 +3722,14 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f64( %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f64(double* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2f64(,,,, double* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f64(,,,, double*, , i32, i32) define @test_vlseg4_nxv2f64(double* %base, i32 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3755,14 +3755,14 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f64( %1, %1, %1, %1, double* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f16(half* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4f16(,, half* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4f16(,, half*, , i32, i32) define @test_vlseg2_nxv4f16(half* %base, i32 %vl) { @@ -3772,7 +3772,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3786,14 +3786,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f16( %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4f16(half* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4f16(,,, half* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv4f16(,,, half*, , i32, i32) define @test_vlseg3_nxv4f16(half* %base, i32 %vl) { @@ -3803,7 +3803,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3818,14 +3818,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4f16( %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4f16(half* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv4f16(,,,, half* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4f16(,,,, half*, , i32, i32) define @test_vlseg4_nxv4f16(half* %base, i32 %vl) { @@ -3835,7 +3835,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3851,14 +3851,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4f16( %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv4f16(,,,,, half* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4f16(,,,,, half*, , i32, i32) define @test_vlseg5_nxv4f16(half* %base, i32 %vl) { @@ -3868,7 +3868,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3885,14 +3885,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4f16( %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4f16(,,,,,, half* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4f16(,,,,,, half*, , i32, i32) define @test_vlseg6_nxv4f16(half* %base, i32 %vl) { @@ -3902,7 +3902,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3920,14 +3920,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(,,,,,,, half* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4f16(,,,,,,, half*, , i32, i32) define @test_vlseg7_nxv4f16(half* %base, i32 %vl) { @@ -3937,7 +3937,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3956,14 +3956,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(,,,,,,,, half* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8_nxv4f16(half* %base, i32 %vl) { @@ -3973,7 +3973,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3993,14 +3993,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f16(half* , i32) +declare {,} @llvm.riscv.vlseg2.nxv2f16(,, half* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv2f16(,, half*, , i32, i32) define @test_vlseg2_nxv2f16(half* %base, i32 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4024,14 +4024,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f16( %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f16(half* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv2f16(,,, half* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f16(,,, half*, , i32, i32) define @test_vlseg3_nxv2f16(half* %base, i32 %vl) { @@ -4041,7 +4041,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4056,14 +4056,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f16( %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f16(half* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv2f16(,,,, half* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f16(,,,, half*, , i32, i32) define @test_vlseg4_nxv2f16(half* %base, i32 %vl) { @@ -4073,7 +4073,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4089,14 +4089,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f16( %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* , i32) +declare {,,,,} @llvm.riscv.vlseg5.nxv2f16(,,,,, half* , i32) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2f16(,,,,, half*, , i32, i32) define @test_vlseg5_nxv2f16(half* %base, i32 %vl) { @@ -4106,7 +4106,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4123,14 +4123,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2f16( %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* , i32) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2f16(,,,,,, half* , i32) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f16(,,,,,, half*, , i32, i32) define @test_vlseg6_nxv2f16(half* %base, i32 %vl) { @@ -4140,7 +4140,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4158,14 +4158,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* , i32) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(,,,,,,, half* , i32) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f16(,,,,,,, half*, , i32, i32) define @test_vlseg7_nxv2f16(half* %base, i32 %vl) { @@ -4175,7 +4175,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4194,14 +4194,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* , i32) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(,,,,,,,, half* , i32) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8_nxv2f16(half* %base, i32 %vl) { @@ -4211,7 +4211,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4231,14 +4231,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f32(float* , i32) +declare {,} @llvm.riscv.vlseg2.nxv4f32(,, float* , i32) declare {,} @llvm.riscv.vlseg2.mask.nxv4f32(,, float*, , i32, i32) define @test_vlseg2_nxv4f32(float* %base, i32 %vl) { @@ -4248,7 +4248,7 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4262,14 +4262,14 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f32( %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4f32(float* , i32) +declare {,,} @llvm.riscv.vlseg3.nxv4f32(,,, float* , i32) declare {,,} @llvm.riscv.vlseg3.mask.nxv4f32(,,, float*, , i32, i32) define @test_vlseg3_nxv4f32(float* %base, i32 %vl) { @@ -4279,7 +4279,7 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4294,14 +4294,14 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4f32( %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4f32(float* , i32) +declare {,,,} @llvm.riscv.vlseg4.nxv4f32(,,,, float* , i32) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4f32(,,,, float*, , i32, i32) define @test_vlseg4_nxv4f32(float* %base, i32 %vl) { @@ -4311,7 +4311,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4327,7 +4327,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4f32( %1, %1, %1, %1, float* %base, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv16i16(,, i16* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv16i16(,, i16*, , i64, i64) define @test_vlseg2_nxv16i16(i16* %base, i64 %vl) { @@ -12,7 +12,7 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -26,14 +26,14 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16i16( %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i32(i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4i32(,, i32* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4i32(,, i32*, , i64, i64) define @test_vlseg2_nxv4i32(i32* %base, i64 %vl) { @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -57,14 +57,14 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i32( %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i32(i32* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4i32(,,, i32* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i32(,,, i32*, , i64, i64) define @test_vlseg3_nxv4i32(i32* %base, i64 %vl) { @@ -74,7 +74,7 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -89,14 +89,14 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i32( %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv4i32(,,,, i32* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i32(,,,, i32*, , i64, i64) define @test_vlseg4_nxv4i32(i32* %base, i64 %vl) { @@ -106,7 +106,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -122,14 +122,14 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i32( %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv16i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv16i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv16i8(,, i8*, , i64, i64) define @test_vlseg2_nxv16i8(i8* %base, i64 %vl) { @@ -139,7 +139,7 @@ ; CHECK-NEXT: vlseg2e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -153,14 +153,14 @@ ; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv16i8(i8* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv16i8(,,, i8* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv16i8(,,, i8*, , i64, i64) define @test_vlseg3_nxv16i8(i8* %base, i64 %vl) { @@ -170,7 +170,7 @@ ; CHECK-NEXT: vlseg3e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -185,14 +185,14 @@ ; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv16i8( %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv16i8(,,,, i8* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv16i8(,,,, i8*, , i64, i64) define @test_vlseg4_nxv16i8(i8* %base, i64 %vl) { @@ -202,7 +202,7 @@ ; CHECK-NEXT: vlseg4e8.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -218,14 +218,14 @@ ; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv16i8( %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i64(i64* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1i64(,, i64* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1i64(,, i64*, , i64, i64) define @test_vlseg2_nxv1i64(i64* %base, i64 %vl) { @@ -235,7 +235,7 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -249,14 +249,14 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i64( %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i64(i64* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1i64(,,, i64* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i64(,,, i64*, , i64, i64) define @test_vlseg3_nxv1i64(i64* %base, i64 %vl) { @@ -266,7 +266,7 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -281,14 +281,14 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i64( %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i64(i64* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1i64(,,,, i64* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i64(,,,, i64*, , i64, i64) define @test_vlseg4_nxv1i64(i64* %base, i64 %vl) { @@ -298,7 +298,7 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -314,14 +314,14 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i64( %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i64(i64* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i64(,,,,, i64* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i64(,,,,, i64*, , i64, i64) define @test_vlseg5_nxv1i64(i64* %base, i64 %vl) { @@ -331,7 +331,7 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64( undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -348,14 +348,14 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64( undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i64( %1, %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i64(i64* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i64(,,,,,, i64* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i64(,,,,,, i64*, , i64, i64) define @test_vlseg6_nxv1i64(i64* %base, i64 %vl) { @@ -365,7 +365,7 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -383,14 +383,14 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i64( %1, %1, %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(i64* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(,,,,,,, i64* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i64(,,,,,,, i64*, , i64, i64) define @test_vlseg7_nxv1i64(i64* %base, i64 %vl) { @@ -400,7 +400,7 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -419,14 +419,14 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i64( %1, %1, %1, %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(i64* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(,,,,,,,, i64* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i64(,,,,,,,, i64*, , i64, i64) define @test_vlseg8_nxv1i64(i64* %base, i64 %vl) { @@ -436,7 +436,7 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -456,14 +456,14 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i64( %1, %1, %1, %1, %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i32(i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1i32(,, i32* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1i32(,, i32*, , i64, i64) define @test_vlseg2_nxv1i32(i32* %base, i64 %vl) { @@ -473,7 +473,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -487,14 +487,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i32( %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i32(i32* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1i32(,,, i32* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i32(,,, i32*, , i64, i64) define @test_vlseg3_nxv1i32(i32* %base, i64 %vl) { @@ -504,7 +504,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -519,14 +519,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i32( %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1i32(,,,, i32* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i32(,,,, i32*, , i64, i64) define @test_vlseg4_nxv1i32(i32* %base, i64 %vl) { @@ -536,7 +536,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -552,14 +552,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i32( %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i32(,,,,, i32* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i32(,,,,, i32*, , i64, i64) define @test_vlseg5_nxv1i32(i32* %base, i64 %vl) { @@ -569,7 +569,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -586,14 +586,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i32( %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i32(,,,,,, i32* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i32(,,,,,, i32*, , i64, i64) define @test_vlseg6_nxv1i32(i32* %base, i64 %vl) { @@ -603,7 +603,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -621,14 +621,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i32( %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(,,,,,,, i32* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i32(,,,,,,, i32*, , i64, i64) define @test_vlseg7_nxv1i32(i32* %base, i64 %vl) { @@ -638,7 +638,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -657,14 +657,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(,,,,,,,, i32* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i32(,,,,,,,, i32*, , i64, i64) define @test_vlseg8_nxv1i32(i32* %base, i64 %vl) { @@ -674,7 +674,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -694,14 +694,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8i16(,, i16* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv8i16(,, i16*, , i64, i64) define @test_vlseg2_nxv8i16(i16* %base, i64 %vl) { @@ -711,7 +711,7 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -725,14 +725,14 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i16( %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8i16(i16* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv8i16(,,, i16* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv8i16(,,, i16*, , i64, i64) define @test_vlseg3_nxv8i16(i16* %base, i64 %vl) { @@ -742,7 +742,7 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -757,14 +757,14 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8i16( %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv8i16(,,,, i16* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8i16(,,,, i16*, , i64, i64) define @test_vlseg4_nxv8i16(i16* %base, i64 %vl) { @@ -774,7 +774,7 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -790,14 +790,14 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8i16( %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4i8(,, i8*, , i64, i64) define @test_vlseg2_nxv4i8(i8* %base, i64 %vl) { @@ -807,7 +807,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -821,14 +821,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i8(i8* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4i8(,,, i8* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i8(,,, i8*, , i64, i64) define @test_vlseg3_nxv4i8(i8* %base, i64 %vl) { @@ -838,7 +838,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -853,14 +853,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i8( %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv4i8(,,,, i8* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i8(,,,, i8*, , i64, i64) define @test_vlseg4_nxv4i8(i8* %base, i64 %vl) { @@ -870,7 +870,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -886,14 +886,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i8( %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv4i8(,,,,, i8* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4i8(,,,,, i8*, , i64, i64) define @test_vlseg5_nxv4i8(i8* %base, i64 %vl) { @@ -903,7 +903,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -920,14 +920,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4i8( %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4i8(,,,,,, i8* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i8(,,,,,, i8*, , i64, i64) define @test_vlseg6_nxv4i8(i8* %base, i64 %vl) { @@ -937,7 +937,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -955,14 +955,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(,,,,,,, i8* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7_nxv4i8(i8* %base, i64 %vl) { @@ -972,7 +972,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -991,14 +991,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(,,,,,,,, i8* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8_nxv4i8(i8* %base, i64 %vl) { @@ -1008,7 +1008,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1028,14 +1028,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1i16(,, i16* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1i16(,, i16*, , i64, i64) define @test_vlseg2_nxv1i16(i16* %base, i64 %vl) { @@ -1045,7 +1045,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1059,14 +1059,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i16( %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i16(i16* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1i16(,,, i16* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i16(,,, i16*, , i64, i64) define @test_vlseg3_nxv1i16(i16* %base, i64 %vl) { @@ -1076,7 +1076,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1091,14 +1091,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i16( %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1i16(,,,, i16* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i16(,,,, i16*, , i64, i64) define @test_vlseg4_nxv1i16(i16* %base, i64 %vl) { @@ -1108,7 +1108,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1124,14 +1124,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i16( %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i16(,,,,, i16* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i16(,,,,, i16*, , i64, i64) define @test_vlseg5_nxv1i16(i16* %base, i64 %vl) { @@ -1141,7 +1141,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1158,14 +1158,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i16( %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i16(,,,,,, i16* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i16(,,,,,, i16*, , i64, i64) define @test_vlseg6_nxv1i16(i16* %base, i64 %vl) { @@ -1175,7 +1175,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1193,14 +1193,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(,,,,,,, i16* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7_nxv1i16(i16* %base, i64 %vl) { @@ -1210,7 +1210,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1229,14 +1229,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(,,,,,,,, i16* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8_nxv1i16(i16* %base, i64 %vl) { @@ -1246,7 +1246,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1266,14 +1266,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i32(i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2i32(,, i32* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2i32(,, i32*, , i64, i64) define @test_vlseg2_nxv2i32(i32* %base, i64 %vl) { @@ -1283,7 +1283,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1297,14 +1297,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i32( %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i32(i32* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2i32(,,, i32* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i32(,,, i32*, , i64, i64) define @test_vlseg3_nxv2i32(i32* %base, i64 %vl) { @@ -1314,7 +1314,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1329,14 +1329,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i32( %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2i32(,,,, i32* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i32(,,,, i32*, , i64, i64) define @test_vlseg4_nxv2i32(i32* %base, i64 %vl) { @@ -1346,7 +1346,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1362,14 +1362,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i32( %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i32(,,,,, i32* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i32(,,,,, i32*, , i64, i64) define @test_vlseg5_nxv2i32(i32* %base, i64 %vl) { @@ -1379,7 +1379,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1396,14 +1396,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i32( %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i32(,,,,,, i32* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i32(,,,,,, i32*, , i64, i64) define @test_vlseg6_nxv2i32(i32* %base, i64 %vl) { @@ -1413,7 +1413,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1431,14 +1431,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i32( %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(,,,,,,, i32* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i32(,,,,,,, i32*, , i64, i64) define @test_vlseg7_nxv2i32(i32* %base, i64 %vl) { @@ -1448,7 +1448,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1467,14 +1467,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(,,,,,,,, i32* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i32(,,,,,,,, i32*, , i64, i64) define @test_vlseg8_nxv2i32(i32* %base, i64 %vl) { @@ -1484,7 +1484,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1504,14 +1504,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv8i8(,, i8*, , i64, i64) define @test_vlseg2_nxv8i8(i8* %base, i64 %vl) { @@ -1521,7 +1521,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1535,14 +1535,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8i8(i8* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv8i8(,,, i8* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv8i8(,,, i8*, , i64, i64) define @test_vlseg3_nxv8i8(i8* %base, i64 %vl) { @@ -1552,7 +1552,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1567,14 +1567,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8i8( %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv8i8(,,,, i8* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8i8(,,,, i8*, , i64, i64) define @test_vlseg4_nxv8i8(i8* %base, i64 %vl) { @@ -1584,7 +1584,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1600,14 +1600,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8i8( %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv8i8(,,,,, i8* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv8i8(,,,,, i8*, , i64, i64) define @test_vlseg5_nxv8i8(i8* %base, i64 %vl) { @@ -1617,7 +1617,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1634,14 +1634,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv8i8( %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv8i8(,,,,,, i8* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv8i8(,,,,,, i8*, , i64, i64) define @test_vlseg6_nxv8i8(i8* %base, i64 %vl) { @@ -1651,7 +1651,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1669,14 +1669,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv8i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(,,,,,,, i8* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv8i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7_nxv8i8(i8* %base, i64 %vl) { @@ -1686,7 +1686,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1705,14 +1705,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(,,,,,,,, i8* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv8i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8_nxv8i8(i8* %base, i64 %vl) { @@ -1722,7 +1722,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1742,14 +1742,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i64(i64* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4i64(,, i64* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4i64(,, i64*, , i64, i64) define @test_vlseg2_nxv4i64(i64* %base, i64 %vl) { @@ -1759,7 +1759,7 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1773,14 +1773,14 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i64( %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4i16(,, i16* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4i16(,, i16*, , i64, i64) define @test_vlseg2_nxv4i16(i16* %base, i64 %vl) { @@ -1790,7 +1790,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1804,14 +1804,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4i16( %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4i16(i16* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4i16(,,, i16* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv4i16(,,, i16*, , i64, i64) define @test_vlseg3_nxv4i16(i16* %base, i64 %vl) { @@ -1821,7 +1821,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1836,14 +1836,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4i16( %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv4i16(,,,, i16* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4i16(,,,, i16*, , i64, i64) define @test_vlseg4_nxv4i16(i16* %base, i64 %vl) { @@ -1853,7 +1853,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1869,14 +1869,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4i16( %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv4i16(,,,,, i16* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4i16(,,,,, i16*, , i64, i64) define @test_vlseg5_nxv4i16(i16* %base, i64 %vl) { @@ -1886,7 +1886,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1903,14 +1903,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4i16( %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4i16(,,,,,, i16* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i16(,,,,,, i16*, , i64, i64) define @test_vlseg6_nxv4i16(i16* %base, i64 %vl) { @@ -1920,7 +1920,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1938,14 +1938,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(,,,,,,, i16* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7_nxv4i16(i16* %base, i64 %vl) { @@ -1955,7 +1955,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1974,14 +1974,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(,,,,,,,, i16* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8_nxv4i16(i16* %base, i64 %vl) { @@ -1991,7 +1991,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2011,14 +2011,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1i8(,, i8*, , i64, i64) define @test_vlseg2_nxv1i8(i8* %base, i64 %vl) { @@ -2028,7 +2028,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2042,14 +2042,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1i8(i8* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1i8(,,, i8* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1i8(,,, i8*, , i64, i64) define @test_vlseg3_nxv1i8(i8* %base, i64 %vl) { @@ -2059,7 +2059,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2074,14 +2074,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1i8( %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1i8(,,,, i8* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1i8(,,,, i8*, , i64, i64) define @test_vlseg4_nxv1i8(i8* %base, i64 %vl) { @@ -2091,7 +2091,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2107,14 +2107,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1i8( %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1i8(,,,,, i8* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1i8(,,,,, i8*, , i64, i64) define @test_vlseg5_nxv1i8(i8* %base, i64 %vl) { @@ -2124,7 +2124,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2141,14 +2141,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1i8( %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1i8(,,,,,, i8* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i8(,,,,,, i8*, , i64, i64) define @test_vlseg6_nxv1i8(i8* %base, i64 %vl) { @@ -2158,7 +2158,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2176,14 +2176,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(,,,,,,, i8* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7_nxv1i8(i8* %base, i64 %vl) { @@ -2193,7 +2193,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2212,14 +2212,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(,,,,,,,, i8* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8_nxv1i8(i8* %base, i64 %vl) { @@ -2229,7 +2229,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2249,14 +2249,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2i8(,, i8*, , i64, i64) define @test_vlseg2_nxv2i8(i8* %base, i64 %vl) { @@ -2266,7 +2266,7 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2280,14 +2280,14 @@ ; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i8(i8* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2i8(,,, i8* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i8(,,, i8*, , i64, i64) define @test_vlseg3_nxv2i8(i8* %base, i64 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2312,14 +2312,14 @@ ; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i8( %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2i8(,,,, i8* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i8(,,,, i8*, , i64, i64) define @test_vlseg4_nxv2i8(i8* %base, i64 %vl) { @@ -2329,7 +2329,7 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2345,14 +2345,14 @@ ; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i8( %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i8(,,,,, i8* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i8(,,,,, i8*, , i64, i64) define @test_vlseg5_nxv2i8(i8* %base, i64 %vl) { @@ -2362,7 +2362,7 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2379,14 +2379,14 @@ ; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i8( %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i8(,,,,,, i8* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i8(,,,,,, i8*, , i64, i64) define @test_vlseg6_nxv2i8(i8* %base, i64 %vl) { @@ -2396,7 +2396,7 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2414,14 +2414,14 @@ ; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i8( %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(,,,,,,, i8* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7_nxv2i8(i8* %base, i64 %vl) { @@ -2431,7 +2431,7 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2450,14 +2450,14 @@ ; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(,,,,,,,, i8* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8_nxv2i8(i8* %base, i64 %vl) { @@ -2467,7 +2467,7 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2487,14 +2487,14 @@ ; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8i32(i32* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8i32(,, i32* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv8i32(,, i32*, , i64, i64) define @test_vlseg2_nxv8i32(i32* %base, i64 %vl) { @@ -2504,7 +2504,7 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2518,14 +2518,14 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8i32( %1, %1, i32* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv32i8(i8* , i64) +declare {,} @llvm.riscv.vlseg2.nxv32i8(,, i8* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv32i8(,, i8*, , i64, i64) define @test_vlseg2_nxv32i8(i8* %base, i64 %vl) { @@ -2535,7 +2535,7 @@ ; CHECK-NEXT: vlseg2e8.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2549,14 +2549,14 @@ ; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv32i8( %1, %1, i8* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2i16(,, i16* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2i16(,, i16*, , i64, i64) define @test_vlseg2_nxv2i16(i16* %base, i64 %vl) { @@ -2566,7 +2566,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2580,14 +2580,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i16( %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i16(i16* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2i16(,,, i16* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i16(,,, i16*, , i64, i64) define @test_vlseg3_nxv2i16(i16* %base, i64 %vl) { @@ -2597,7 +2597,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2612,14 +2612,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i16( %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2i16(,,,, i16* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i16(,,,, i16*, , i64, i64) define @test_vlseg4_nxv2i16(i16* %base, i64 %vl) { @@ -2629,7 +2629,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2645,14 +2645,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i16( %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv2i16(,,,,, i16* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2i16(,,,,, i16*, , i64, i64) define @test_vlseg5_nxv2i16(i16* %base, i64 %vl) { @@ -2662,7 +2662,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2679,14 +2679,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2i16( %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2i16(,,,,,, i16* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i16(,,,,,, i16*, , i64, i64) define @test_vlseg6_nxv2i16(i16* %base, i64 %vl) { @@ -2696,7 +2696,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2714,14 +2714,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2i16( %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(,,,,,,, i16* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7_nxv2i16(i16* %base, i64 %vl) { @@ -2731,7 +2731,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2750,14 +2750,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(,,,,,,,, i16* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8_nxv2i16(i16* %base, i64 %vl) { @@ -2767,7 +2767,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2787,14 +2787,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2i64(i64* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2i64(,, i64* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2i64(,, i64*, , i64, i64) define @test_vlseg2_nxv2i64(i64* %base, i64 %vl) { @@ -2804,7 +2804,7 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2818,14 +2818,14 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2i64( %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2i64(i64* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2i64(,,, i64* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2i64(,,, i64*, , i64, i64) define @test_vlseg3_nxv2i64(i64* %base, i64 %vl) { @@ -2835,7 +2835,7 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2850,14 +2850,14 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2i64( %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2i64(i64* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2i64(,,,, i64* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2i64(,,,, i64*, , i64, i64) define @test_vlseg4_nxv2i64(i64* %base, i64 %vl) { @@ -2867,7 +2867,7 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2883,14 +2883,14 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2i64( %1, %1, %1, %1, i64* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv16f16(half* , i64) +declare {,} @llvm.riscv.vlseg2.nxv16f16(,, half* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv16f16(,, half*, , i64, i64) define @test_vlseg2_nxv16f16(half* %base, i64 %vl) { @@ -2900,7 +2900,7 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2914,14 +2914,14 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16f16( %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f64(double* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4f64(,, double* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4f64(,, double*, , i64, i64) define @test_vlseg2_nxv4f64(double* %base, i64 %vl) { @@ -2931,7 +2931,7 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2945,14 +2945,14 @@ ; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f64( %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f64(double* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1f64(,, double* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1f64(,, double*, , i64, i64) define @test_vlseg2_nxv1f64(double* %base, i64 %vl) { @@ -2962,7 +2962,7 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2976,14 +2976,14 @@ ; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f64( %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f64(double* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1f64(,,, double* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f64(,,, double*, , i64, i64) define @test_vlseg3_nxv1f64(double* %base, i64 %vl) { @@ -2993,7 +2993,7 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3008,14 +3008,14 @@ ; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f64( %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f64(double* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1f64(,,,, double* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f64(,,,, double*, , i64, i64) define @test_vlseg4_nxv1f64(double* %base, i64 %vl) { @@ -3025,7 +3025,7 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3041,14 +3041,14 @@ ; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f64( %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f64(,,,,, double* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f64(,,,,, double*, , i64, i64) define @test_vlseg5_nxv1f64(double* %base, i64 %vl) { @@ -3058,7 +3058,7 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3075,14 +3075,14 @@ ; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f64( %1, %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f64(,,,,,, double* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f64(,,,,,, double*, , i64, i64) define @test_vlseg6_nxv1f64(double* %base, i64 %vl) { @@ -3092,7 +3092,7 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3110,14 +3110,14 @@ ; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f64( %1, %1, %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(,,,,,,, double* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f64(,,,,,,, double*, , i64, i64) define @test_vlseg7_nxv1f64(double* %base, i64 %vl) { @@ -3127,7 +3127,7 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3146,14 +3146,14 @@ ; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(,,,,,,,, double* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f64(,,,,,,,, double*, , i64, i64) define @test_vlseg8_nxv1f64(double* %base, i64 %vl) { @@ -3163,7 +3163,7 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3183,14 +3183,14 @@ ; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f32(float* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2f32(,, float* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2f32(,, float*, , i64, i64) define @test_vlseg2_nxv2f32(float* %base, i64 %vl) { @@ -3200,7 +3200,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3214,14 +3214,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f32( %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f32(float* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2f32(,,, float* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f32(,,, float*, , i64, i64) define @test_vlseg3_nxv2f32(float* %base, i64 %vl) { @@ -3231,7 +3231,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3246,14 +3246,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f32( %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f32(float* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2f32(,,,, float* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f32(,,,, float*, , i64, i64) define @test_vlseg4_nxv2f32(float* %base, i64 %vl) { @@ -3263,7 +3263,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3279,14 +3279,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f32( %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv2f32(,,,,, float* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2f32(,,,,, float*, , i64, i64) define @test_vlseg5_nxv2f32(float* %base, i64 %vl) { @@ -3296,7 +3296,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3313,14 +3313,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2f32( %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2f32(,,,,,, float* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f32(,,,,,, float*, , i64, i64) define @test_vlseg6_nxv2f32(float* %base, i64 %vl) { @@ -3330,7 +3330,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3348,14 +3348,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f32( %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(,,,,,,, float* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f32(,,,,,,, float*, , i64, i64) define @test_vlseg7_nxv2f32(float* %base, i64 %vl) { @@ -3365,7 +3365,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3384,14 +3384,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(,,,,,,,, float* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f32(,,,,,,,, float*, , i64, i64) define @test_vlseg8_nxv2f32(float* %base, i64 %vl) { @@ -3401,7 +3401,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3421,14 +3421,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f16(half* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1f16(,, half* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1f16(,, half*, , i64, i64) define @test_vlseg2_nxv1f16(half* %base, i64 %vl) { @@ -3438,7 +3438,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3452,14 +3452,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f16( %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f16(half* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1f16(,,, half* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f16(,,, half*, , i64, i64) define @test_vlseg3_nxv1f16(half* %base, i64 %vl) { @@ -3469,7 +3469,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3484,14 +3484,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f16( %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f16(half* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1f16(,,,, half* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f16(,,,, half*, , i64, i64) define @test_vlseg4_nxv1f16(half* %base, i64 %vl) { @@ -3501,7 +3501,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3517,14 +3517,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f16( %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f16(,,,,, half* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f16(,,,,, half*, , i64, i64) define @test_vlseg5_nxv1f16(half* %base, i64 %vl) { @@ -3534,7 +3534,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3551,14 +3551,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f16( %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f16(,,,,,, half* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f16(,,,,,, half*, , i64, i64) define @test_vlseg6_nxv1f16(half* %base, i64 %vl) { @@ -3568,7 +3568,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3586,14 +3586,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(,,,,,,, half* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f16(,,,,,,, half*, , i64, i64) define @test_vlseg7_nxv1f16(half* %base, i64 %vl) { @@ -3603,7 +3603,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3622,14 +3622,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(,,,,,,,, half* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8_nxv1f16(half* %base, i64 %vl) { @@ -3639,7 +3639,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3659,14 +3659,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv1f32(float* , i64) +declare {,} @llvm.riscv.vlseg2.nxv1f32(,, float* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv1f32(,, float*, , i64, i64) define @test_vlseg2_nxv1f32(float* %base, i64 %vl) { @@ -3676,7 +3676,7 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3690,14 +3690,14 @@ ; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv1f32( %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv1f32(float* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv1f32(,,, float* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv1f32(,,, float*, , i64, i64) define @test_vlseg3_nxv1f32(float* %base, i64 %vl) { @@ -3707,7 +3707,7 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3722,14 +3722,14 @@ ; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv1f32( %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv1f32(float* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv1f32(,,,, float* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv1f32(,,,, float*, , i64, i64) define @test_vlseg4_nxv1f32(float* %base, i64 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3755,14 +3755,14 @@ ; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv1f32( %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv1f32(,,,,, float* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv1f32(,,,,, float*, , i64, i64) define @test_vlseg5_nxv1f32(float* %base, i64 %vl) { @@ -3772,7 +3772,7 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3789,14 +3789,14 @@ ; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv1f32( %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv1f32(,,,,,, float* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f32(,,,,,, float*, , i64, i64) define @test_vlseg6_nxv1f32(float* %base, i64 %vl) { @@ -3806,7 +3806,7 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3824,14 +3824,14 @@ ; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv1f32( %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(,,,,,,, float* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f32(,,,,,,, float*, , i64, i64) define @test_vlseg7_nxv1f32(float* %base, i64 %vl) { @@ -3841,7 +3841,7 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3860,14 +3860,14 @@ ; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(,,,,,,,, float* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f32(,,,,,,,, float*, , i64, i64) define @test_vlseg8_nxv1f32(float* %base, i64 %vl) { @@ -3877,7 +3877,7 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3897,14 +3897,14 @@ ; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8f16(half* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8f16(,, half* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv8f16(,, half*, , i64, i64) define @test_vlseg2_nxv8f16(half* %base, i64 %vl) { @@ -3914,7 +3914,7 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3928,14 +3928,14 @@ ; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8f16( %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv8f16(half* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv8f16(,,, half* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv8f16(,,, half*, , i64, i64) define @test_vlseg3_nxv8f16(half* %base, i64 %vl) { @@ -3945,7 +3945,7 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3960,14 +3960,14 @@ ; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv8f16( %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv8f16(half* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv8f16(,,,, half* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv8f16(,,,, half*, , i64, i64) define @test_vlseg4_nxv8f16(half* %base, i64 %vl) { @@ -3977,7 +3977,7 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3993,14 +3993,14 @@ ; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv8f16( %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv8f32(float* , i64) +declare {,} @llvm.riscv.vlseg2.nxv8f32(,, float* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv8f32(,, float*, , i64, i64) define @test_vlseg2_nxv8f32(float* %base, i64 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4024,14 +4024,14 @@ ; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv8f32( %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f64(double* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2f64(,, double* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2f64(,, double*, , i64, i64) define @test_vlseg2_nxv2f64(double* %base, i64 %vl) { @@ -4041,7 +4041,7 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4055,14 +4055,14 @@ ; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f64( %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f64(double* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2f64(,,, double* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f64(,,, double*, , i64, i64) define @test_vlseg3_nxv2f64(double* %base, i64 %vl) { @@ -4072,7 +4072,7 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4087,14 +4087,14 @@ ; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f64( %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f64(double* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2f64(,,,, double* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f64(,,,, double*, , i64, i64) define @test_vlseg4_nxv2f64(double* %base, i64 %vl) { @@ -4104,7 +4104,7 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4120,14 +4120,14 @@ ; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f64( %1, %1, %1, %1, double* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f16(half* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4f16(,, half* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4f16(,, half*, , i64, i64) define @test_vlseg2_nxv4f16(half* %base, i64 %vl) { @@ -4137,7 +4137,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4151,14 +4151,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f16( %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4f16(half* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4f16(,,, half* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv4f16(,,, half*, , i64, i64) define @test_vlseg3_nxv4f16(half* %base, i64 %vl) { @@ -4168,7 +4168,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4183,14 +4183,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4f16( %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4f16(half* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv4f16(,,,, half* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4f16(,,,, half*, , i64, i64) define @test_vlseg4_nxv4f16(half* %base, i64 %vl) { @@ -4200,7 +4200,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4216,14 +4216,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4f16( %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv4f16(,,,,, half* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv4f16(,,,,, half*, , i64, i64) define @test_vlseg5_nxv4f16(half* %base, i64 %vl) { @@ -4233,7 +4233,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4250,14 +4250,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv4f16( %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv4f16(,,,,,, half* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv4f16(,,,,,, half*, , i64, i64) define @test_vlseg6_nxv4f16(half* %base, i64 %vl) { @@ -4267,7 +4267,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4285,14 +4285,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv4f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(,,,,,,, half* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4f16(,,,,,,, half*, , i64, i64) define @test_vlseg7_nxv4f16(half* %base, i64 %vl) { @@ -4302,7 +4302,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4321,14 +4321,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(,,,,,,,, half* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8_nxv4f16(half* %base, i64 %vl) { @@ -4338,7 +4338,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4358,14 +4358,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv2f16(half* , i64) +declare {,} @llvm.riscv.vlseg2.nxv2f16(,, half* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv2f16(,, half*, , i64, i64) define @test_vlseg2_nxv2f16(half* %base, i64 %vl) { @@ -4375,7 +4375,7 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4389,14 +4389,14 @@ ; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv2f16( %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv2f16(half* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv2f16(,,, half* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv2f16(,,, half*, , i64, i64) define @test_vlseg3_nxv2f16(half* %base, i64 %vl) { @@ -4406,7 +4406,7 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4421,14 +4421,14 @@ ; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv2f16( %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv2f16(half* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv2f16(,,,, half* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv2f16(,,,, half*, , i64, i64) define @test_vlseg4_nxv2f16(half* %base, i64 %vl) { @@ -4438,7 +4438,7 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4454,14 +4454,14 @@ ; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv2f16( %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* , i64) +declare {,,,,} @llvm.riscv.vlseg5.nxv2f16(,,,,, half* , i64) declare {,,,,} @llvm.riscv.vlseg5.mask.nxv2f16(,,,,, half*, , i64, i64) define @test_vlseg5_nxv2f16(half* %base, i64 %vl) { @@ -4471,7 +4471,7 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4488,14 +4488,14 @@ ; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlseg5.mask.nxv2f16( %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* , i64) +declare {,,,,,} @llvm.riscv.vlseg6.nxv2f16(,,,,,, half* , i64) declare {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f16(,,,,,, half*, , i64, i64) define @test_vlseg6_nxv2f16(half* %base, i64 %vl) { @@ -4505,7 +4505,7 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4523,14 +4523,14 @@ ; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlseg6.mask.nxv2f16( %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* , i64) +declare {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(,,,,,,, half* , i64) declare {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f16(,,,,,,, half*, , i64, i64) define @test_vlseg7_nxv2f16(half* %base, i64 %vl) { @@ -4540,7 +4540,7 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4559,14 +4559,14 @@ ; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlseg7.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* , i64) +declare {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(,,,,,,,, half* , i64) declare {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8_nxv2f16(half* %base, i64 %vl) { @@ -4576,7 +4576,7 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4596,14 +4596,14 @@ ; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlseg8.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlseg2.nxv4f32(float* , i64) +declare {,} @llvm.riscv.vlseg2.nxv4f32(,, float* , i64) declare {,} @llvm.riscv.vlseg2.mask.nxv4f32(,, float*, , i64, i64) define @test_vlseg2_nxv4f32(float* %base, i64 %vl) { @@ -4613,7 +4613,7 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4627,14 +4627,14 @@ ; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv4f32( %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlseg3.nxv4f32(float* , i64) +declare {,,} @llvm.riscv.vlseg3.nxv4f32(,,, float* , i64) declare {,,} @llvm.riscv.vlseg3.mask.nxv4f32(,,, float*, , i64, i64) define @test_vlseg3_nxv4f32(float* %base, i64 %vl) { @@ -4644,7 +4644,7 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4659,14 +4659,14 @@ ; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlseg3.mask.nxv4f32( %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlseg4.nxv4f32(float* , i64) +declare {,,,} @llvm.riscv.vlseg4.nxv4f32(,,,, float* , i64) declare {,,,} @llvm.riscv.vlseg4.mask.nxv4f32(,,,, float*, , i64, i64) define @test_vlseg4_nxv4f32(float* %base, i64 %vl) { @@ -4676,7 +4676,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4692,7 +4692,7 @@ ; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlseg4.mask.nxv4f32( %1, %1, %1, %1, float* %base, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll @@ -1,41 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -stop-after=finalize-isel < %s \ ; RUN: -target-abi=ilp32d | FileCheck %s -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(,, i32*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i64(i64* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i64(,, i64* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i64(,, i64*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(,, i32*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(,, i16*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(,, i16*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(,, i32*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i64(i64* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i64(,, i64* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i64(,, i64*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(,, i16*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(,, i32*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(,, i8*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(,, i16*, , i32, i32) -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i64(i64* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i64(,, i64* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i64(,, i64*, , i32, i32) define void @test_vlseg2ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -51,7 +51,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -114,7 +114,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -177,7 +177,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv32i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -240,7 +240,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -303,7 +303,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -366,7 +366,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -429,7 +429,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -492,7 +492,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -555,7 +555,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i64(i64* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i64( undef, undef, i64* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -618,7 +618,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i64(i64* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i64( undef, undef, i64* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void @@ -681,7 +681,7 @@ ; CHECK-NEXT: SW killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s32) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i64(i64* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i64( undef, undef, i64* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store volatile i32 %1, i32* %outvl ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll @@ -1,41 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel < %s \ ; RUN: -target-abi=lp64d | FileCheck %s -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(,, i32*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(,, i64*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(,, i32*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(,, i16*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(,, i16*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(,, i32*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(,, i64*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(,, i16*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(,, i32*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(,, i8*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(,, i16*, , i64, i64) -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(,, i64*, , i64, i64) define void @test_vlseg2ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -51,7 +51,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -114,7 +114,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -177,7 +177,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv32i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -240,7 +240,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -303,7 +303,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -366,7 +366,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -429,7 +429,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -492,7 +492,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -555,7 +555,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -618,7 +618,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void @@ -681,7 +681,7 @@ ; CHECK-NEXT: SD killed [[PseudoReadVL]], [[COPY]], 0 :: (volatile store (s64) into %ir.outvl) ; CHECK-NEXT: PseudoRET entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store volatile i64 %1, i64* %outvl ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i32, i32) define void @test_vlseg2ff_dead_value(i16* %base, i32 %vl, i32* %outvl) { @@ -14,7 +14,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 2 store i32 %1, i32* %outvl ret void @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlseg2e16ff.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 ret %1 } @@ -68,7 +68,7 @@ ; CHECK-NEXT: vlseg2e16ff.v v8, (a0) ; CHECK-NEXT: ret entry: - tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl) + tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i32 %vl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i32, i32) define @test_vlseg2ff_nxv16i16(i16* %base, i32 %vl, i32* %outvl) { @@ -14,7 +14,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -38,7 +38,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -50,7 +50,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -74,7 +74,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i8(i8* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i8(,,, i8* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(,,, i8*, , i32, i32) define @test_vlseg3ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -86,7 +86,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -111,7 +111,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i8(i8* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i8(,,,, i8* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(,,,, i8*, , i32, i32) define @test_vlseg4ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -123,7 +123,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -149,7 +149,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i8(i8* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i8(,,,,, i8* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(,,,,, i8*, , i32, i32) define @test_vlseg5ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -161,7 +161,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -188,7 +188,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i8(i8* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i8(,,,,,, i8* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(,,,,,, i8*, , i32, i32) define @test_vlseg6ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -200,7 +200,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -228,7 +228,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i8(i8* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i8(,,,,,,, i8* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -240,7 +240,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -269,7 +269,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i8(i8* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i8(,,,,,,,, i8* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) { @@ -281,7 +281,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -311,7 +311,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) { @@ -323,7 +323,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -347,7 +347,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv16i8(i8* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv16i8(,,, i8* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(,,, i8*, , i32, i32) define @test_vlseg3ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) { @@ -359,7 +359,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv16i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -384,7 +384,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv16i8(i8* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv16i8(,,,, i8* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(,,,, i8*, , i32, i32) define @test_vlseg4ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) { @@ -396,7 +396,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv16i8(i8* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv16i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -422,7 +422,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(,, i32*, , i32, i32) define @test_vlseg2ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -434,7 +434,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -458,7 +458,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i32(i32* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i32(,,, i32* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(,,, i32*, , i32, i32) define @test_vlseg3ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -470,7 +470,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -495,7 +495,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i32(i32* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i32(,,,, i32* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(,,,, i32*, , i32, i32) define @test_vlseg4ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -507,7 +507,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -533,7 +533,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i32(i32* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i32(,,,,, i32* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(,,,,, i32*, , i32, i32) define @test_vlseg5ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -545,7 +545,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -572,7 +572,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i32(i32* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i32(,,,,,, i32* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(,,,,,, i32*, , i32, i32) define @test_vlseg6ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -584,7 +584,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -612,7 +612,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i32(i32* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i32(,,,,,,, i32* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(,,,,,,, i32*, , i32, i32) define @test_vlseg7ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -624,7 +624,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -653,7 +653,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i32(i32* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i32(,,,,,,,, i32* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(,,,,,,,, i32*, , i32, i32) define @test_vlseg8ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) { @@ -665,7 +665,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -695,7 +695,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(,, i16*, , i32, i32) define @test_vlseg2ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -707,7 +707,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -731,7 +731,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i16(i16* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i16(,,, i16* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(,,, i16*, , i32, i32) define @test_vlseg3ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -743,7 +743,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -768,7 +768,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i16(i16* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i16(,,,, i16* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(,,,, i16*, , i32, i32) define @test_vlseg4ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -780,7 +780,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -806,7 +806,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i16(i16* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i16(,,,,, i16* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(,,,,, i16*, , i32, i32) define @test_vlseg5ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -818,7 +818,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -845,7 +845,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i16(i16* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i16(,,,,,, i16* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(,,,,,, i16*, , i32, i32) define @test_vlseg6ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -857,7 +857,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -885,7 +885,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i16(i16* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i16(,,,,,,, i16* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -897,7 +897,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -926,7 +926,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i16(i16* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i16(,,,,,,,, i16* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) { @@ -938,7 +938,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -968,7 +968,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(,, i32*, , i32, i32) define @test_vlseg2ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -980,7 +980,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1004,7 +1004,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i32(i32* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i32(,,, i32* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(,,, i32*, , i32, i32) define @test_vlseg3ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1016,7 +1016,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -1041,7 +1041,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i32(i32* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i32(,,,, i32* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(,,,, i32*, , i32, i32) define @test_vlseg4ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1053,7 +1053,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -1079,7 +1079,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i32(i32* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i32(,,,,, i32* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(,,,,, i32*, , i32, i32) define @test_vlseg5ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1091,7 +1091,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -1118,7 +1118,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i32(i32* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i32(,,,,,, i32* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(,,,,,, i32*, , i32, i32) define @test_vlseg6ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1130,7 +1130,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -1158,7 +1158,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i32(i32* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i32(,,,,,,, i32* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(,,,,,,, i32*, , i32, i32) define @test_vlseg7ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1170,7 +1170,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -1199,7 +1199,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i32(i32* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i32(,,,,,,,, i32* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(,,,,,,,, i32*, , i32, i32) define @test_vlseg8ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1211,7 +1211,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i32(i32* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -1241,7 +1241,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(,, i16*, , i32, i32) define @test_vlseg2ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) { @@ -1253,7 +1253,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1277,7 +1277,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8i16(i16* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8i16(,,, i16* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(,,, i16*, , i32, i32) define @test_vlseg3ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) { @@ -1289,7 +1289,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -1314,7 +1314,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i16(i16* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i16(,,,, i16* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(,,,, i16*, , i32, i32) define @test_vlseg4ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) { @@ -1326,7 +1326,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i16(i16* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -1352,7 +1352,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1364,7 +1364,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1388,7 +1388,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8i8(i8* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8i8(,,, i8* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(,,, i8*, , i32, i32) define @test_vlseg3ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1400,7 +1400,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -1425,7 +1425,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i8(i8* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i8(,,,, i8* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(,,,, i8*, , i32, i32) define @test_vlseg4ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1437,7 +1437,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -1463,7 +1463,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv8i8(i8* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv8i8(,,,,, i8* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(,,,,, i8*, , i32, i32) define @test_vlseg5ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1475,7 +1475,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -1502,7 +1502,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv8i8(i8* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv8i8(,,,,,, i8* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(,,,,,, i8*, , i32, i32) define @test_vlseg6ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1514,7 +1514,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -1542,7 +1542,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv8i8(i8* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv8i8(,,,,,,, i8* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1554,7 +1554,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -1583,7 +1583,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv8i8(i8* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv8i8(,,,,,,,, i8* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1595,7 +1595,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv8i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -1625,7 +1625,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(,, i32*, , i32, i32) define @test_vlseg2ff_nxv8i32(i32* %base, i32 %vl, i32* %outvl) { @@ -1637,7 +1637,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1661,7 +1661,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1673,7 +1673,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1697,7 +1697,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i8(i8* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i8(,,, i8* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(,,, i8*, , i32, i32) define @test_vlseg3ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1709,7 +1709,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -1734,7 +1734,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i8(i8* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i8(,,,, i8* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(,,,, i8*, , i32, i32) define @test_vlseg4ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1746,7 +1746,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -1772,7 +1772,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i8(i8* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i8(,,,,, i8* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(,,,,, i8*, , i32, i32) define @test_vlseg5ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1784,7 +1784,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -1811,7 +1811,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i8(i8* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i8(,,,,,, i8* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(,,,,,, i8*, , i32, i32) define @test_vlseg6ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1823,7 +1823,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -1851,7 +1851,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i8(i8* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i8(,,,,,,, i8* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1863,7 +1863,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -1892,7 +1892,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i8(i8* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i8(,,,,,,,, i8* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) { @@ -1904,7 +1904,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -1934,7 +1934,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(,, i16*, , i32, i32) define @test_vlseg2ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -1946,7 +1946,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -1970,7 +1970,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i16(i16* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1i16(,,, i16* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(,,, i16*, , i32, i32) define @test_vlseg3ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -1982,7 +1982,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -2007,7 +2007,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i16(i16* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i16(,,,, i16* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(,,,, i16*, , i32, i32) define @test_vlseg4ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2019,7 +2019,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -2045,7 +2045,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i16(i16* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i16(,,,,, i16* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(,,,,, i16*, , i32, i32) define @test_vlseg5ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2057,7 +2057,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -2084,7 +2084,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i16(i16* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i16(,,,,,, i16* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(,,,,,, i16*, , i32, i32) define @test_vlseg6ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2096,7 +2096,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -2124,7 +2124,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i16(i16* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i16(,,,,,,, i16* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2136,7 +2136,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -2165,7 +2165,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i16(i16* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i16(,,,,,,,, i16* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2177,7 +2177,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -2207,7 +2207,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv32i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2219,7 +2219,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv32i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2243,7 +2243,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i8(,, i8* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(,, i8*, , i32, i32) define @test_vlseg2ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2255,7 +2255,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i8( undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2279,7 +2279,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i8(i8* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i8(,,, i8* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(,,, i8*, , i32, i32) define @test_vlseg3ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2291,7 +2291,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i8( undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -2316,7 +2316,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i8(i8* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i8(,,,, i8* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(,,,, i8*, , i32, i32) define @test_vlseg4ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2328,7 +2328,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i8( undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -2354,7 +2354,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i8(i8* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i8(,,,,, i8* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(,,,,, i8*, , i32, i32) define @test_vlseg5ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2366,7 +2366,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -2393,7 +2393,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i8(i8* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i8(,,,,,, i8* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(,,,,,, i8*, , i32, i32) define @test_vlseg6ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2405,7 +2405,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -2433,7 +2433,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i8(i8* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i8(,,,,,,, i8* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(,,,,,,, i8*, , i32, i32) define @test_vlseg7ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2445,7 +2445,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -2474,7 +2474,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i8(i8* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i8(,,,,,,,, i8* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(,,,,,,,, i8*, , i32, i32) define @test_vlseg8ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) { @@ -2486,7 +2486,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i8(i8* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -2516,7 +2516,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2i16(,, i16* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(,, i16*, , i32, i32) define @test_vlseg2ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2528,7 +2528,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2i16( undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2552,7 +2552,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i16(i16* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2i16(,,, i16* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(,,, i16*, , i32, i32) define @test_vlseg3ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2564,7 +2564,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2i16( undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -2589,7 +2589,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i16(i16* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i16(,,,, i16* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(,,,, i16*, , i32, i32) define @test_vlseg4ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2601,7 +2601,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2i16( undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -2627,7 +2627,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i16(i16* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i16(,,,,, i16* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(,,,,, i16*, , i32, i32) define @test_vlseg5ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2639,7 +2639,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -2666,7 +2666,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i16(i16* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i16(,,,,,, i16* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(,,,,,, i16*, , i32, i32) define @test_vlseg6ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2678,7 +2678,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -2706,7 +2706,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i16(i16* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i16(,,,,,,, i16* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(,,,,,,, i16*, , i32, i32) define @test_vlseg7ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2718,7 +2718,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -2747,7 +2747,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i16(i16* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i16(,,,,,,,, i16* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(,,,,,,,, i16*, , i32, i32) define @test_vlseg8ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) { @@ -2759,7 +2759,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i16(i16* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -2789,7 +2789,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(,, i32* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(,, i32*, , i32, i32) define @test_vlseg2ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) { @@ -2801,7 +2801,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4i32( undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2825,7 +2825,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i32(i32* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4i32(,,, i32* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(,,, i32*, , i32, i32) define @test_vlseg3ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) { @@ -2837,7 +2837,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4i32( undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -2862,7 +2862,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i32(i32* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i32(,,,, i32* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(,,,, i32*, , i32, i32) define @test_vlseg4ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) { @@ -2874,7 +2874,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i32(i32* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4i32( undef, undef, undef, undef, i32* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -2900,7 +2900,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv16f16(half* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv16f16(,, half* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(,, half*, , i32, i32) define @test_vlseg2ff_nxv16f16(half* %base, i32 %vl, i32* %outvl) { @@ -2912,7 +2912,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16f16(half* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv16f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2936,7 +2936,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f64(double* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f64(,, double* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(,, double*, , i32, i32) define @test_vlseg2ff_nxv4f64(double* %base, i32 %vl, i32* %outvl) { @@ -2948,7 +2948,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f64(double* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -2972,7 +2972,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f64(double* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f64(,, double* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(,, double*, , i32, i32) define @test_vlseg2ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -2984,7 +2984,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -3008,7 +3008,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f64(double* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f64(,,, double* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(,,, double*, , i32, i32) define @test_vlseg3ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3020,7 +3020,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -3045,7 +3045,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f64(double* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f64(,,,, double* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(,,,, double*, , i32, i32) define @test_vlseg4ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3057,7 +3057,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -3083,7 +3083,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f64(double* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f64(,,,,, double* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(,,,,, double*, , i32, i32) define @test_vlseg5ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3095,7 +3095,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f64( undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -3122,7 +3122,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f64(double* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f64(,,,,,, double* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(,,,,,, double*, , i32, i32) define @test_vlseg6ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3134,7 +3134,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -3162,7 +3162,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f64(double* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f64(,,,,,,, double* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(,,,,,,, double*, , i32, i32) define @test_vlseg7ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3174,7 +3174,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -3203,7 +3203,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f64(double* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f64(,,,,,,,, double* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(,,,,,,,, double*, , i32, i32) define @test_vlseg8ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) { @@ -3215,7 +3215,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f64(double* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -3245,7 +3245,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f32(float* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f32(,, float* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(,, float*, , i32, i32) define @test_vlseg2ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3257,7 +3257,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -3281,7 +3281,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f32(float* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f32(,,, float* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(,,, float*, , i32, i32) define @test_vlseg3ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3293,7 +3293,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -3318,7 +3318,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f32(float* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f32(,,,, float* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(,,,, float*, , i32, i32) define @test_vlseg4ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3330,7 +3330,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -3356,7 +3356,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f32(float* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f32(,,,,, float* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(,,,,, float*, , i32, i32) define @test_vlseg5ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3368,7 +3368,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -3395,7 +3395,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f32(float* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f32(,,,,,, float* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(,,,,,, float*, , i32, i32) define @test_vlseg6ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3407,7 +3407,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -3435,7 +3435,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f32(float* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f32(,,,,,,, float* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(,,,,,,, float*, , i32, i32) define @test_vlseg7ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3447,7 +3447,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -3476,7 +3476,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f32(float* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f32(,,,,,,,, float* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(,,,,,,,, float*, , i32, i32) define @test_vlseg8ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) { @@ -3488,7 +3488,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -3518,7 +3518,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f16(half* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f16(,, half* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(,, half*, , i32, i32) define @test_vlseg2ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3530,7 +3530,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -3554,7 +3554,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f16(half* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f16(,,, half* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(,,, half*, , i32, i32) define @test_vlseg3ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3566,7 +3566,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -3591,7 +3591,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f16(half* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f16(,,,, half* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(,,,, half*, , i32, i32) define @test_vlseg4ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3603,7 +3603,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -3629,7 +3629,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f16(half* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f16(,,,,, half* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(,,,,, half*, , i32, i32) define @test_vlseg5ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3641,7 +3641,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -3668,7 +3668,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f16(half* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f16(,,,,,, half* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(,,,,,, half*, , i32, i32) define @test_vlseg6ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3680,7 +3680,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -3708,7 +3708,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f16(half* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f16(,,,,,,, half* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(,,,,,,, half*, , i32, i32) define @test_vlseg7ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3720,7 +3720,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -3749,7 +3749,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f16(half* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f16(,,,,,,,, half* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) { @@ -3761,7 +3761,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -3791,7 +3791,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f32(float* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv1f32(,, float* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(,, float*, , i32, i32) define @test_vlseg2ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3803,7 +3803,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv1f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -3827,7 +3827,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f32(float* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv1f32(,,, float* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(,,, float*, , i32, i32) define @test_vlseg3ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3839,7 +3839,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv1f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -3864,7 +3864,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f32(float* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f32(,,,, float* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(,,,, float*, , i32, i32) define @test_vlseg4ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3876,7 +3876,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv1f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -3902,7 +3902,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f32(float* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f32(,,,,, float* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(,,,,, float*, , i32, i32) define @test_vlseg5ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3914,7 +3914,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv1f32( undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -3941,7 +3941,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f32(float* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f32(,,,,,, float* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(,,,,,, float*, , i32, i32) define @test_vlseg6ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3953,7 +3953,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -3981,7 +3981,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f32(float* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f32(,,,,,,, float* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(,,,,,,, float*, , i32, i32) define @test_vlseg7ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -3993,7 +3993,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -4022,7 +4022,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f32(float* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f32(,,,,,,,, float* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(,,,,,,,, float*, , i32, i32) define @test_vlseg8ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) { @@ -4034,7 +4034,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f32(float* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -4064,7 +4064,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8f16(half* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8f16(,, half* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(,, half*, , i32, i32) define @test_vlseg2ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) { @@ -4076,7 +4076,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4100,7 +4100,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8f16(half* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv8f16(,,, half* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(,,, half*, , i32, i32) define @test_vlseg3ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) { @@ -4112,7 +4112,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv8f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -4137,7 +4137,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8f16(half* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv8f16(,,,, half* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(,,,, half*, , i32, i32) define @test_vlseg4ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) { @@ -4149,7 +4149,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8f16(half* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv8f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -4175,7 +4175,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv8f32(float* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv8f32(,, float* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(,, float*, , i32, i32) define @test_vlseg2ff_nxv8f32(float* %base, i32 %vl, i32* %outvl) { @@ -4187,7 +4187,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8f32(float* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv8f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4211,7 +4211,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f64(double* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f64(,, double* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(,, double*, , i32, i32) define @test_vlseg2ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) { @@ -4223,7 +4223,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f64( undef, undef, double* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4247,7 +4247,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f64(double* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f64(,,, double* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(,,, double*, , i32, i32) define @test_vlseg3ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) { @@ -4259,7 +4259,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f64( undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -4284,7 +4284,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f64(double* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f64(,,,, double* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(,,,, double*, , i32, i32) define @test_vlseg4ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) { @@ -4296,7 +4296,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f64(double* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f64( undef, undef, undef, undef, double* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -4322,7 +4322,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f16(half* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f16(,, half* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(,, half*, , i32, i32) define @test_vlseg2ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4334,7 +4334,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4358,7 +4358,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4f16(half* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4f16(,,, half* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(,,, half*, , i32, i32) define @test_vlseg3ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4370,7 +4370,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -4395,7 +4395,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f16(half* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f16(,,,, half* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(,,,, half*, , i32, i32) define @test_vlseg4ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4407,7 +4407,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -4433,7 +4433,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4f16(half* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4f16(,,,,, half* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(,,,,, half*, , i32, i32) define @test_vlseg5ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4445,7 +4445,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv4f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -4472,7 +4472,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4f16(half* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4f16(,,,,,, half* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(,,,,,, half*, , i32, i32) define @test_vlseg6ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4484,7 +4484,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -4512,7 +4512,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4f16(half* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4f16(,,,,,,, half* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(,,,,,,, half*, , i32, i32) define @test_vlseg7ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4524,7 +4524,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -4553,7 +4553,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4f16(half* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4f16(,,,,,,,, half* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) { @@ -4565,7 +4565,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -4595,7 +4595,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f16(half* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv2f16(,, half* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(,, half*, , i32, i32) define @test_vlseg2ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4607,7 +4607,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv2f16( undef, undef, half* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4631,7 +4631,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f16(half* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv2f16(,,, half* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(,,, half*, , i32, i32) define @test_vlseg3ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4643,7 +4643,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv2f16( undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -4668,7 +4668,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f16(half* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f16(,,,, half* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(,,,, half*, , i32, i32) define @test_vlseg4ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4680,7 +4680,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv2f16( undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl @@ -4706,7 +4706,7 @@ ret %1 } -declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f16(half* , i32) +declare {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f16(,,,,, half* , i32) declare {,,,,, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(,,,,, half*, , i32, i32) define @test_vlseg5ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4718,7 +4718,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,, i32} @llvm.riscv.vlseg5ff.nxv2f16( undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,, i32} %0, 1 %2 = extractvalue {,,,,, i32} %0, 5 store i32 %2, i32* %outvl @@ -4745,7 +4745,7 @@ ret %1 } -declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f16(half* , i32) +declare {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f16(,,,,,, half* , i32) declare {,,,,,, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(,,,,,, half*, , i32, i32) define @test_vlseg6ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4757,7 +4757,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,, i32} @llvm.riscv.vlseg6ff.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,, i32} %0, 6 store i32 %2, i32* %outvl @@ -4785,7 +4785,7 @@ ret %1 } -declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f16(half* , i32) +declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f16(,,,,,,, half* , i32) declare {,,,,,,, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(,,,,,,, half*, , i32, i32) define @test_vlseg7ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4797,7 +4797,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,, i32} @llvm.riscv.vlseg7ff.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,, i32} %0, 7 store i32 %2, i32* %outvl @@ -4826,7 +4826,7 @@ ret %1 } -declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f16(half* , i32) +declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f16(,,,,,,,, half* , i32) declare {,,,,,,,, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(,,,,,,,, half*, , i32, i32) define @test_vlseg8ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) { @@ -4838,7 +4838,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f16(half* %base, i32 %vl) + %0 = tail call {,,,,,,,, i32} @llvm.riscv.vlseg8ff.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %vl) %1 = extractvalue {,,,,,,,, i32} %0, 1 %2 = extractvalue {,,,,,,,, i32} %0, 8 store i32 %2, i32* %outvl @@ -4868,7 +4868,7 @@ ret %1 } -declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f32(float* , i32) +declare {,, i32} @llvm.riscv.vlseg2ff.nxv4f32(,, float* , i32) declare {,, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(,, float*, , i32, i32) define @test_vlseg2ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) { @@ -4880,7 +4880,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,, i32} @llvm.riscv.vlseg2ff.nxv4f32( undef, undef, float* %base, i32 %vl) %1 = extractvalue {,, i32} %0, 1 %2 = extractvalue {,, i32} %0, 2 store i32 %2, i32* %outvl @@ -4904,7 +4904,7 @@ ret %1 } -declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4f32(float* , i32) +declare {,,, i32} @llvm.riscv.vlseg3ff.nxv4f32(,,, float* , i32) declare {,,, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(,,, float*, , i32, i32) define @test_vlseg3ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) { @@ -4916,7 +4916,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,, i32} @llvm.riscv.vlseg3ff.nxv4f32( undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,, i32} %0, 1 %2 = extractvalue {,,, i32} %0, 3 store i32 %2, i32* %outvl @@ -4941,7 +4941,7 @@ ret %1 } -declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f32(float* , i32) +declare {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f32(,,,, float* , i32) declare {,,,, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(,,,, float*, , i32, i32) define @test_vlseg4ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) { @@ -4953,7 +4953,7 @@ ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f32(float* %base, i32 %vl) + %0 = tail call {,,,, i32} @llvm.riscv.vlseg4ff.nxv4f32( undef, undef, undef, undef, float* %base, i32 %vl) %1 = extractvalue {,,,, i32} %0, 1 %2 = extractvalue {,,,, i32} %0, 4 store i32 %2, i32* %outvl diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i64, i64) define void @test_vlseg2ff_dead_value(i16* %base, i64 %vl, i64* %outvl) { @@ -14,7 +14,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 2 store i64 %1, i64* %outvl ret void @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlseg2e16ff.v v4, (a0) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 ret %1 } @@ -68,7 +68,7 @@ ; CHECK-NEXT: vlseg2e16ff.v v8, (a0) ; CHECK-NEXT: ret entry: - tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl) + tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 %vl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv16i16(i16* %base, i64 %vl, i64* %outvl) { @@ -14,7 +14,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -38,7 +38,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(,, i32*, , i64, i64) define @test_vlseg2ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) { @@ -50,7 +50,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -74,7 +74,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i32(i32* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i32(,,, i32* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(,,, i32*, , i64, i64) define @test_vlseg3ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) { @@ -86,7 +86,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -111,7 +111,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i32(i32* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i32(,,,, i32* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(,,,, i32*, , i64, i64) define @test_vlseg4ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) { @@ -123,7 +123,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i32(i32* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -149,7 +149,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) { @@ -161,7 +161,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -185,7 +185,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv16i8(i8* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv16i8(,,, i8* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(,,, i8*, , i64, i64) define @test_vlseg3ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) { @@ -197,7 +197,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv16i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -222,7 +222,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv16i8(i8* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv16i8(,,,, i8* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(,,,, i8*, , i64, i64) define @test_vlseg4ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) { @@ -234,7 +234,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv16i8(i8* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv16i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -260,7 +260,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(,, i64*, , i64, i64) define @test_vlseg2ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -272,7 +272,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -296,7 +296,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i64(i64* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i64(,,, i64* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(,,, i64*, , i64, i64) define @test_vlseg3ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -308,7 +308,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -333,7 +333,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i64(i64* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i64(,,,, i64* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(,,,, i64*, , i64, i64) define @test_vlseg4ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -345,7 +345,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -371,7 +371,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i64(i64* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i64(,,,,, i64* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(,,,,, i64*, , i64, i64) define @test_vlseg5ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -383,7 +383,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i64( undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -410,7 +410,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i64(i64* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i64(,,,,,, i64* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(,,,,,, i64*, , i64, i64) define @test_vlseg6ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -422,7 +422,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -450,7 +450,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i64(i64* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i64(,,,,,,, i64* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(,,,,,,, i64*, , i64, i64) define @test_vlseg7ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -462,7 +462,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -491,7 +491,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i64(i64* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i64(,,,,,,,, i64* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(,,,,,,,, i64*, , i64, i64) define @test_vlseg8ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) { @@ -503,7 +503,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i64(i64* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -533,7 +533,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(,, i32*, , i64, i64) define @test_vlseg2ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -545,7 +545,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -569,7 +569,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i32(i32* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i32(,,, i32* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(,,, i32*, , i64, i64) define @test_vlseg3ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -581,7 +581,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -606,7 +606,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i32(i32* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i32(,,,, i32* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(,,,, i32*, , i64, i64) define @test_vlseg4ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -618,7 +618,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -644,7 +644,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i32(i32* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i32(,,,,, i32* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(,,,,, i32*, , i64, i64) define @test_vlseg5ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -656,7 +656,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -683,7 +683,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i32(i32* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i32(,,,,,, i32* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(,,,,,, i32*, , i64, i64) define @test_vlseg6ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -695,7 +695,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -723,7 +723,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i32(i32* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i32(,,,,,,, i32* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(,,,,,,, i32*, , i64, i64) define @test_vlseg7ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -735,7 +735,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -764,7 +764,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i32(i32* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i32(,,,,,,,, i32* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(,,,,,,,, i32*, , i64, i64) define @test_vlseg8ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) { @@ -776,7 +776,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -806,7 +806,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) { @@ -818,7 +818,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -842,7 +842,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8i16(i16* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8i16(,,, i16* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(,,, i16*, , i64, i64) define @test_vlseg3ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) { @@ -854,7 +854,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -879,7 +879,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i16(i16* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i16(,,,, i16* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(,,,, i16*, , i64, i64) define @test_vlseg4ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) { @@ -891,7 +891,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i16(i16* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -917,7 +917,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -929,7 +929,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -953,7 +953,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i8(i8* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i8(,,, i8* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(,,, i8*, , i64, i64) define @test_vlseg3ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -965,7 +965,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -990,7 +990,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i8(i8* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i8(,,,, i8* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(,,,, i8*, , i64, i64) define @test_vlseg4ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1002,7 +1002,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -1028,7 +1028,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i8(i8* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i8(,,,,, i8* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(,,,,, i8*, , i64, i64) define @test_vlseg5ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1040,7 +1040,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -1067,7 +1067,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i8(i8* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i8(,,,,,, i8* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(,,,,,, i8*, , i64, i64) define @test_vlseg6ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1079,7 +1079,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -1107,7 +1107,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i8(i8* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i8(,,,,,,, i8* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1119,7 +1119,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -1148,7 +1148,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i8(i8* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i8(,,,,,,,, i8* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1160,7 +1160,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -1190,7 +1190,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1202,7 +1202,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -1226,7 +1226,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i16(i16* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i16(,,, i16* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(,,, i16*, , i64, i64) define @test_vlseg3ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1238,7 +1238,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -1263,7 +1263,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i16(i16* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i16(,,,, i16* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(,,,, i16*, , i64, i64) define @test_vlseg4ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1275,7 +1275,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -1301,7 +1301,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i16(i16* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i16(,,,,, i16* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(,,,,, i16*, , i64, i64) define @test_vlseg5ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1313,7 +1313,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -1340,7 +1340,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i16(i16* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i16(,,,,,, i16* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(,,,,,, i16*, , i64, i64) define @test_vlseg6ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1352,7 +1352,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -1380,7 +1380,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i16(i16* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i16(,,,,,,, i16* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1392,7 +1392,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -1421,7 +1421,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i16(i16* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i16(,,,,,,,, i16* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) { @@ -1433,7 +1433,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -1463,7 +1463,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(,, i32*, , i64, i64) define @test_vlseg2ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1475,7 +1475,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -1499,7 +1499,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i32(i32* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i32(,,, i32* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(,,, i32*, , i64, i64) define @test_vlseg3ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1511,7 +1511,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i32( undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -1536,7 +1536,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i32(i32* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i32(,,,, i32* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(,,,, i32*, , i64, i64) define @test_vlseg4ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1548,7 +1548,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i32( undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -1574,7 +1574,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i32(i32* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i32(,,,,, i32* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(,,,,, i32*, , i64, i64) define @test_vlseg5ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1586,7 +1586,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -1613,7 +1613,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i32(i32* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i32(,,,,,, i32* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(,,,,,, i32*, , i64, i64) define @test_vlseg6ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1625,7 +1625,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -1653,7 +1653,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i32(i32* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i32(,,,,,,, i32* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(,,,,,,, i32*, , i64, i64) define @test_vlseg7ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1665,7 +1665,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -1694,7 +1694,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i32(i32* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i32(,,,,,,,, i32* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(,,,,,,,, i32*, , i64, i64) define @test_vlseg8ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) { @@ -1706,7 +1706,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i32(i32* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -1736,7 +1736,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1748,7 +1748,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -1772,7 +1772,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8i8(i8* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8i8(,,, i8* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(,,, i8*, , i64, i64) define @test_vlseg3ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1784,7 +1784,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -1809,7 +1809,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i8(i8* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i8(,,,, i8* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(,,,, i8*, , i64, i64) define @test_vlseg4ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1821,7 +1821,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -1847,7 +1847,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv8i8(i8* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv8i8(,,,,, i8* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(,,,,, i8*, , i64, i64) define @test_vlseg5ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1859,7 +1859,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -1886,7 +1886,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv8i8(i8* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv8i8(,,,,,, i8* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(,,,,,, i8*, , i64, i64) define @test_vlseg6ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1898,7 +1898,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -1926,7 +1926,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv8i8(i8* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv8i8(,,,,,,, i8* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1938,7 +1938,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -1967,7 +1967,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv8i8(i8* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv8i8(,,,,,,,, i8* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) { @@ -1979,7 +1979,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv8i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -2009,7 +2009,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(,, i64*, , i64, i64) define @test_vlseg2ff_nxv4i64(i64* %base, i64 %vl, i64* %outvl) { @@ -2021,7 +2021,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2045,7 +2045,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2057,7 +2057,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2081,7 +2081,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i16(i16* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4i16(,,, i16* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(,,, i16*, , i64, i64) define @test_vlseg3ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2093,7 +2093,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -2118,7 +2118,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i16(i16* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i16(,,,, i16* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(,,,, i16*, , i64, i64) define @test_vlseg4ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2130,7 +2130,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -2156,7 +2156,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i16(i16* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i16(,,,,, i16* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(,,,,, i16*, , i64, i64) define @test_vlseg5ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2168,7 +2168,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -2195,7 +2195,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i16(i16* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i16(,,,,,, i16* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(,,,,,, i16*, , i64, i64) define @test_vlseg6ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2207,7 +2207,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -2235,7 +2235,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i16(i16* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i16(,,,,,,, i16* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2247,7 +2247,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -2276,7 +2276,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i16(i16* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i16(,,,,,,,, i16* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2288,7 +2288,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -2318,7 +2318,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2330,7 +2330,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2354,7 +2354,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i8(i8* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1i8(,,, i8* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(,,, i8*, , i64, i64) define @test_vlseg3ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2366,7 +2366,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -2391,7 +2391,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i8(i8* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i8(,,,, i8* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(,,,, i8*, , i64, i64) define @test_vlseg4ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2403,7 +2403,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -2429,7 +2429,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i8(i8* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i8(,,,,, i8* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(,,,,, i8*, , i64, i64) define @test_vlseg5ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2441,7 +2441,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -2468,7 +2468,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i8(i8* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i8(,,,,,, i8* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(,,,,,, i8*, , i64, i64) define @test_vlseg6ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2480,7 +2480,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -2508,7 +2508,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i8(i8* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i8(,,,,,,, i8* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2520,7 +2520,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -2549,7 +2549,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i8(i8* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i8(,,,,,,,, i8* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2561,7 +2561,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -2591,7 +2591,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2603,7 +2603,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2627,7 +2627,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i8(i8* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i8(,,, i8* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(,,, i8*, , i64, i64) define @test_vlseg3ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2639,7 +2639,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i8( undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -2664,7 +2664,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i8(i8* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i8(,,,, i8* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(,,,, i8*, , i64, i64) define @test_vlseg4ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2676,7 +2676,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i8( undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -2702,7 +2702,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i8(i8* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i8(,,,,, i8* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(,,,,, i8*, , i64, i64) define @test_vlseg5ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2714,7 +2714,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -2741,7 +2741,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i8(i8* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i8(,,,,,, i8* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(,,,,,, i8*, , i64, i64) define @test_vlseg6ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2753,7 +2753,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -2781,7 +2781,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i8(i8* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i8(,,,,,,, i8* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(,,,,,,, i8*, , i64, i64) define @test_vlseg7ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2793,7 +2793,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -2822,7 +2822,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i8(i8* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i8(,,,,,,,, i8* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(,,,,,,,, i8*, , i64, i64) define @test_vlseg8ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2834,7 +2834,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i8(i8* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -2864,7 +2864,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8i32(,, i32* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(,, i32*, , i64, i64) define @test_vlseg2ff_nxv8i32(i32* %base, i64 %vl, i64* %outvl) { @@ -2876,7 +2876,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i32(i32* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8i32( undef, undef, i32* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2900,7 +2900,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(,, i8* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(,, i8*, , i64, i64) define @test_vlseg2ff_nxv32i8(i8* %base, i64 %vl, i64* %outvl) { @@ -2912,7 +2912,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv32i8( undef, undef, i8* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2936,7 +2936,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2948,7 +2948,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i16( undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -2972,7 +2972,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i16(i16* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i16(,,, i16* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(,,, i16*, , i64, i64) define @test_vlseg3ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -2984,7 +2984,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i16( undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -3009,7 +3009,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i16(i16* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i16(,,,, i16* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(,,,, i16*, , i64, i64) define @test_vlseg4ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -3021,7 +3021,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i16( undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -3047,7 +3047,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i16(i16* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i16(,,,,, i16* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(,,,,, i16*, , i64, i64) define @test_vlseg5ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -3059,7 +3059,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -3086,7 +3086,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i16(i16* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i16(,,,,,, i16* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(,,,,,, i16*, , i64, i64) define @test_vlseg6ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -3098,7 +3098,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -3126,7 +3126,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i16(i16* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i16(,,,,,,, i16* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(,,,,,,, i16*, , i64, i64) define @test_vlseg7ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -3138,7 +3138,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -3167,7 +3167,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i16(i16* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i16(,,,,,,,, i16* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(,,,,,,,, i16*, , i64, i64) define @test_vlseg8ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) { @@ -3179,7 +3179,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i16(i16* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -3209,7 +3209,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(,, i64* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(,, i64*, , i64, i64) define @test_vlseg2ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) { @@ -3221,7 +3221,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2i64( undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3245,7 +3245,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i64(i64* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2i64(,,, i64* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(,,, i64*, , i64, i64) define @test_vlseg3ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) { @@ -3257,7 +3257,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2i64( undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -3282,7 +3282,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i64(i64* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i64(,,,, i64* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(,,,, i64*, , i64, i64) define @test_vlseg4ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) { @@ -3294,7 +3294,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i64(i64* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2i64( undef, undef, undef, undef, i64* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -3320,7 +3320,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16f16(half* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16f16(,, half* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(,, half*, , i64, i64) define @test_vlseg2ff_nxv16f16(half* %base, i64 %vl, i64* %outvl) { @@ -3332,7 +3332,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16f16(half* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3356,7 +3356,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f64(double* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f64(,, double* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(,, double*, , i64, i64) define @test_vlseg2ff_nxv4f64(double* %base, i64 %vl, i64* %outvl) { @@ -3368,7 +3368,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f64(double* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3392,7 +3392,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f64(double* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f64(,, double* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(,, double*, , i64, i64) define @test_vlseg2ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3404,7 +3404,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3428,7 +3428,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f64(double* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f64(,,, double* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(,,, double*, , i64, i64) define @test_vlseg3ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3440,7 +3440,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -3465,7 +3465,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f64(double* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f64(,,,, double* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(,,,, double*, , i64, i64) define @test_vlseg4ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3477,7 +3477,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -3503,7 +3503,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f64(double* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f64(,,,,, double* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(,,,,, double*, , i64, i64) define @test_vlseg5ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3515,7 +3515,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f64( undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -3542,7 +3542,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f64(double* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f64(,,,,,, double* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(,,,,,, double*, , i64, i64) define @test_vlseg6ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3554,7 +3554,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -3582,7 +3582,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f64(double* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f64(,,,,,,, double* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(,,,,,,, double*, , i64, i64) define @test_vlseg7ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3594,7 +3594,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -3623,7 +3623,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f64(double* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f64(,,,,,,,, double* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(,,,,,,,, double*, , i64, i64) define @test_vlseg8ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) { @@ -3635,7 +3635,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f64(double* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -3665,7 +3665,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f32(float* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f32(,, float* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(,, float*, , i64, i64) define @test_vlseg2ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3677,7 +3677,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3701,7 +3701,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f32(float* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f32(,,, float* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(,,, float*, , i64, i64) define @test_vlseg3ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3713,7 +3713,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -3738,7 +3738,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f32(float* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f32(,,,, float* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(,,,, float*, , i64, i64) define @test_vlseg4ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3750,7 +3750,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -3776,7 +3776,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f32(float* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f32(,,,,, float* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(,,,,, float*, , i64, i64) define @test_vlseg5ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3788,7 +3788,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -3815,7 +3815,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f32(float* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f32(,,,,,, float* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(,,,,,, float*, , i64, i64) define @test_vlseg6ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3827,7 +3827,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -3855,7 +3855,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f32(float* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f32(,,,,,,, float* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(,,,,,,, float*, , i64, i64) define @test_vlseg7ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3867,7 +3867,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -3896,7 +3896,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f32(float* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f32(,,,,,,,, float* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(,,,,,,,, float*, , i64, i64) define @test_vlseg8ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) { @@ -3908,7 +3908,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -3938,7 +3938,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f16(half* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f16(,, half* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(,, half*, , i64, i64) define @test_vlseg2ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -3950,7 +3950,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -3974,7 +3974,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f16(half* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f16(,,, half* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(,,, half*, , i64, i64) define @test_vlseg3ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -3986,7 +3986,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -4011,7 +4011,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f16(half* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f16(,,,, half* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(,,,, half*, , i64, i64) define @test_vlseg4ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -4023,7 +4023,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -4049,7 +4049,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f16(half* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f16(,,,,, half* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(,,,,, half*, , i64, i64) define @test_vlseg5ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -4061,7 +4061,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -4088,7 +4088,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f16(half* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f16(,,,,,, half* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(,,,,,, half*, , i64, i64) define @test_vlseg6ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -4100,7 +4100,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -4128,7 +4128,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f16(half* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f16(,,,,,,, half* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(,,,,,,, half*, , i64, i64) define @test_vlseg7ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -4140,7 +4140,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -4169,7 +4169,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f16(half* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f16(,,,,,,,, half* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) { @@ -4181,7 +4181,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -4211,7 +4211,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f32(float* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv1f32(,, float* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(,, float*, , i64, i64) define @test_vlseg2ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4223,7 +4223,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv1f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -4247,7 +4247,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f32(float* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv1f32(,,, float* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(,,, float*, , i64, i64) define @test_vlseg3ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4259,7 +4259,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv1f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -4284,7 +4284,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f32(float* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f32(,,,, float* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(,,,, float*, , i64, i64) define @test_vlseg4ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4296,7 +4296,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv1f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -4322,7 +4322,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f32(float* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f32(,,,,, float* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(,,,,, float*, , i64, i64) define @test_vlseg5ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4334,7 +4334,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv1f32( undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -4361,7 +4361,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f32(float* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f32(,,,,,, float* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(,,,,,, float*, , i64, i64) define @test_vlseg6ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4373,7 +4373,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -4401,7 +4401,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f32(float* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f32(,,,,,,, float* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(,,,,,,, float*, , i64, i64) define @test_vlseg7ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4413,7 +4413,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -4442,7 +4442,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f32(float* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f32(,,,,,,,, float* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(,,,,,,,, float*, , i64, i64) define @test_vlseg8ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) { @@ -4454,7 +4454,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f32(float* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -4484,7 +4484,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8f16(half* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8f16(,, half* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(,, half*, , i64, i64) define @test_vlseg2ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) { @@ -4496,7 +4496,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -4520,7 +4520,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8f16(half* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv8f16(,,, half* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(,,, half*, , i64, i64) define @test_vlseg3ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) { @@ -4532,7 +4532,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv8f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -4557,7 +4557,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8f16(half* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv8f16(,,,, half* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(,,,, half*, , i64, i64) define @test_vlseg4ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) { @@ -4569,7 +4569,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8f16(half* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv8f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -4595,7 +4595,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv8f32(float* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv8f32(,, float* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(,, float*, , i64, i64) define @test_vlseg2ff_nxv8f32(float* %base, i64 %vl, i64* %outvl) { @@ -4607,7 +4607,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8f32(float* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv8f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -4631,7 +4631,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f64(double* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f64(,, double* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(,, double*, , i64, i64) define @test_vlseg2ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) { @@ -4643,7 +4643,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f64( undef, undef, double* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -4667,7 +4667,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f64(double* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f64(,,, double* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(,,, double*, , i64, i64) define @test_vlseg3ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) { @@ -4679,7 +4679,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f64( undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -4704,7 +4704,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f64(double* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f64(,,,, double* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(,,,, double*, , i64, i64) define @test_vlseg4ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) { @@ -4716,7 +4716,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f64(double* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f64( undef, undef, undef, undef, double* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -4742,7 +4742,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f16(half* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f16(,, half* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(,, half*, , i64, i64) define @test_vlseg2ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4754,7 +4754,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -4778,7 +4778,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4f16(half* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4f16(,,, half* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(,,, half*, , i64, i64) define @test_vlseg3ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4790,7 +4790,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -4815,7 +4815,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f16(half* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f16(,,,, half* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(,,,, half*, , i64, i64) define @test_vlseg4ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4827,7 +4827,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -4853,7 +4853,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4f16(half* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4f16(,,,,, half* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(,,,,, half*, , i64, i64) define @test_vlseg5ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4865,7 +4865,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv4f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -4892,7 +4892,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4f16(half* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4f16(,,,,,, half* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(,,,,,, half*, , i64, i64) define @test_vlseg6ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4904,7 +4904,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -4932,7 +4932,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4f16(half* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4f16(,,,,,,, half* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(,,,,,,, half*, , i64, i64) define @test_vlseg7ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4944,7 +4944,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -4973,7 +4973,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4f16(half* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4f16(,,,,,,,, half* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) { @@ -4985,7 +4985,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -5015,7 +5015,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f16(half* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv2f16(,, half* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(,, half*, , i64, i64) define @test_vlseg2ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5027,7 +5027,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv2f16( undef, undef, half* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -5051,7 +5051,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f16(half* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv2f16(,,, half* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(,,, half*, , i64, i64) define @test_vlseg3ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5063,7 +5063,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv2f16( undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -5088,7 +5088,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f16(half* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f16(,,,, half* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(,,,, half*, , i64, i64) define @test_vlseg4ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5100,7 +5100,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv2f16( undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl @@ -5126,7 +5126,7 @@ ret %1 } -declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f16(half* , i64) +declare {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f16(,,,,, half* , i64) declare {,,,,, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(,,,,, half*, , i64, i64) define @test_vlseg5ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5138,7 +5138,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,, i64} @llvm.riscv.vlseg5ff.nxv2f16( undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,, i64} %0, 1 %2 = extractvalue {,,,,, i64} %0, 5 store i64 %2, i64* %outvl @@ -5165,7 +5165,7 @@ ret %1 } -declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f16(half* , i64) +declare {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f16(,,,,,, half* , i64) declare {,,,,,, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(,,,,,, half*, , i64, i64) define @test_vlseg6ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5177,7 +5177,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,, i64} @llvm.riscv.vlseg6ff.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,, i64} %0, 6 store i64 %2, i64* %outvl @@ -5205,7 +5205,7 @@ ret %1 } -declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f16(half* , i64) +declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f16(,,,,,,, half* , i64) declare {,,,,,,, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(,,,,,,, half*, , i64, i64) define @test_vlseg7ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5217,7 +5217,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,, i64} @llvm.riscv.vlseg7ff.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,, i64} %0, 7 store i64 %2, i64* %outvl @@ -5246,7 +5246,7 @@ ret %1 } -declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f16(half* , i64) +declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f16(,,,,,,,, half* , i64) declare {,,,,,,,, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(,,,,,,,, half*, , i64, i64) define @test_vlseg8ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) { @@ -5258,7 +5258,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f16(half* %base, i64 %vl) + %0 = tail call {,,,,,,,, i64} @llvm.riscv.vlseg8ff.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %vl) %1 = extractvalue {,,,,,,,, i64} %0, 1 %2 = extractvalue {,,,,,,,, i64} %0, 8 store i64 %2, i64* %outvl @@ -5288,7 +5288,7 @@ ret %1 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f32(float* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv4f32(,, float* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(,, float*, , i64, i64) define @test_vlseg2ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) { @@ -5300,7 +5300,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv4f32( undef, undef, float* %base, i64 %vl) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl @@ -5324,7 +5324,7 @@ ret %1 } -declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4f32(float* , i64) +declare {,,, i64} @llvm.riscv.vlseg3ff.nxv4f32(,,, float* , i64) declare {,,, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(,,, float*, , i64, i64) define @test_vlseg3ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) { @@ -5336,7 +5336,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,, i64} @llvm.riscv.vlseg3ff.nxv4f32( undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,, i64} %0, 1 %2 = extractvalue {,,, i64} %0, 3 store i64 %2, i64* %outvl @@ -5361,7 +5361,7 @@ ret %1 } -declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f32(float* , i64) +declare {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f32(,,,, float* , i64) declare {,,,, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(,,,, float*, , i64, i64) define @test_vlseg4ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) { @@ -5373,7 +5373,7 @@ ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret entry: - %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f32(float* %base, i64 %vl) + %0 = tail call {,,,, i64} @llvm.riscv.vlseg4ff.nxv4f32( undef, undef, undef, undef, float* %base, i64 %vl) %1 = extractvalue {,,,, i64} %0, 1 %2 = extractvalue {,,,, i64} %0, 4 store i64 %2, i64* %outvl diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv16i16(,, i16*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv16i16(,, i16*, i32, , i32, i32) define @test_vlsseg2_nxv16i16(i16* %base, i32 %offset, i32 %vl) { @@ -12,7 +12,7 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -26,14 +26,14 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16i16( %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -57,14 +57,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i8(i8*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1i8(,,, i8*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i8(,,, i8*, i32, , i32, i32) define @test_vlsseg3_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -74,7 +74,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -89,14 +89,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i8( %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i8(,,,, i8*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i8(,,,, i8*, i32, , i32, i32) define @test_vlsseg4_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -106,7 +106,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -122,14 +122,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i8( %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i8(,,,,, i8*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i8(,,,,, i8*, i32, , i32, i32) define @test_vlsseg5_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -139,7 +139,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -156,14 +156,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i8( %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(,,,,,, i8*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i8(,,,,,, i8*, i32, , i32, i32) define @test_vlsseg6_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -173,7 +173,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -191,14 +191,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i8( %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(,,,,,,, i8*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i8(,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg7_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -208,7 +208,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -227,14 +227,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(,,,,,,,, i8*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i8(,,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg8_nxv1i8(i8* %base, i32 %offset, i32 %vl) { @@ -244,7 +244,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -264,14 +264,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv16i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv16i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv16i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv16i8(i8* %base, i32 %offset, i32 %vl) { @@ -281,7 +281,7 @@ ; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -295,14 +295,14 @@ ; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv16i8(i8*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv16i8(,,, i8*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv16i8(,,, i8*, i32, , i32, i32) define @test_vlsseg3_nxv16i8(i8* %base, i32 %offset, i32 %vl) { @@ -312,7 +312,7 @@ ; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -327,14 +327,14 @@ ; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv16i8( %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv16i8(,,,, i8*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv16i8(,,,, i8*, i32, , i32, i32) define @test_vlsseg4_nxv16i8(i8* %base, i32 %offset, i32 %vl) { @@ -344,7 +344,7 @@ ; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -360,14 +360,14 @@ ; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv16i8( %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i32(i32*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2i32(,, i32*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i32(,, i32*, i32, , i32, i32) define @test_vlsseg2_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -377,7 +377,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -391,14 +391,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i32( %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i32(i32*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2i32(,,, i32*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i32(,,, i32*, i32, , i32, i32) define @test_vlsseg3_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -408,7 +408,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -423,14 +423,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i32( %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i32(,,,, i32*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i32(,,,, i32*, i32, , i32, i32) define @test_vlsseg4_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -440,7 +440,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -456,14 +456,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i32( %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i32(,,,,, i32*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i32(,,,,, i32*, i32, , i32, i32) define @test_vlsseg5_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -473,7 +473,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -490,14 +490,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i32( %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(,,,,,, i32*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i32(,,,,,, i32*, i32, , i32, i32) define @test_vlsseg6_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -507,7 +507,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -525,14 +525,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i32( %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(,,,,,,, i32*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i32(,,,,,,, i32*, i32, , i32, i32) define @test_vlsseg7_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -542,7 +542,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -561,14 +561,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(,,,,,,,, i32*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i32(,,,,,,,, i32*, i32, , i32, i32) define @test_vlsseg8_nxv2i32(i32* %base, i32 %offset, i32 %vl) { @@ -578,7 +578,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -598,14 +598,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i16(i16*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4i16(,, i16*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i16(,, i16*, i32, , i32, i32) define @test_vlsseg2_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -615,7 +615,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -629,14 +629,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i16( %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i16(i16*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv4i16(,,, i16*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i16(,,, i16*, i32, , i32, i32) define @test_vlsseg3_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -646,7 +646,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -661,14 +661,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i16( %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i16(,,,, i16*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i16(,,,, i16*, i32, , i32, i32) define @test_vlsseg4_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -678,7 +678,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -694,14 +694,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i16( %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4i16(,,,,, i16*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i16(,,,,, i16*, i32, , i32, i32) define @test_vlsseg5_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -711,7 +711,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -728,14 +728,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i16( %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(,,,,,, i16*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i16(,,,,,, i16*, i32, , i32, i32) define @test_vlsseg6_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -745,7 +745,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -763,14 +763,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i16( %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(,,,,,,, i16*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i16(,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg7_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -780,7 +780,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -799,14 +799,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(,,,,,,,, i16*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i16(,,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg8_nxv4i16(i16* %base, i32 %offset, i32 %vl) { @@ -816,7 +816,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -836,14 +836,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i32(i32*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1i32(,, i32*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i32(,, i32*, i32, , i32, i32) define @test_vlsseg2_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -853,7 +853,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -867,14 +867,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i32( %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i32(i32*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1i32(,,, i32*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i32(,,, i32*, i32, , i32, i32) define @test_vlsseg3_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -884,7 +884,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -899,14 +899,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i32( %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i32(,,,, i32*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i32(,,,, i32*, i32, , i32, i32) define @test_vlsseg4_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -916,7 +916,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -932,14 +932,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i32( %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i32(,,,,, i32*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i32(,,,,, i32*, i32, , i32, i32) define @test_vlsseg5_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -949,7 +949,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -966,14 +966,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i32( %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(,,,,,, i32*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i32(,,,,,, i32*, i32, , i32, i32) define @test_vlsseg6_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -983,7 +983,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1001,14 +1001,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i32( %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(,,,,,,, i32*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i32(,,,,,,, i32*, i32, , i32, i32) define @test_vlsseg7_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -1018,7 +1018,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1037,14 +1037,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(,,,,,,,, i32*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i32(,,,,,,,, i32*, i32, , i32, i32) define @test_vlsseg8_nxv1i32(i32* %base, i32 %offset, i32 %vl) { @@ -1054,7 +1054,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1074,14 +1074,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i16(i16*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv8i16(,, i16*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i16(,, i16*, i32, , i32, i32) define @test_vlsseg2_nxv8i16(i16* %base, i32 %offset, i32 %vl) { @@ -1091,7 +1091,7 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1105,14 +1105,14 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i16( %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8i16(i16*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv8i16(,,, i16*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8i16(,,, i16*, i32, , i32, i32) define @test_vlsseg3_nxv8i16(i16* %base, i32 %offset, i32 %vl) { @@ -1122,7 +1122,7 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1137,14 +1137,14 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8i16( %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv8i16(,,,, i16*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8i16(,,,, i16*, i32, , i32, i32) define @test_vlsseg4_nxv8i16(i16* %base, i32 %offset, i32 %vl) { @@ -1154,7 +1154,7 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1170,14 +1170,14 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8i16( %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv8i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1187,7 +1187,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1201,14 +1201,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8i8(i8*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv8i8(,,, i8*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8i8(,,, i8*, i32, , i32, i32) define @test_vlsseg3_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1218,7 +1218,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1233,14 +1233,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8i8( %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv8i8(,,,, i8*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8i8(,,,, i8*, i32, , i32, i32) define @test_vlsseg4_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1250,7 +1250,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1266,14 +1266,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8i8( %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv8i8(,,,,, i8*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv8i8(,,,,, i8*, i32, , i32, i32) define @test_vlsseg5_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1283,7 +1283,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1300,14 +1300,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv8i8( %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(,,,,,, i8*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv8i8(,,,,,, i8*, i32, , i32, i32) define @test_vlsseg6_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1317,7 +1317,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1335,14 +1335,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv8i8( %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(,,,,,,, i8*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv8i8(,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg7_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1352,7 +1352,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1371,14 +1371,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(,,,,,,,, i8*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv8i8(,,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg8_nxv8i8(i8* %base, i32 %offset, i32 %vl) { @@ -1388,7 +1388,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1408,14 +1408,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i32(i32*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv8i32(,, i32*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i32(,, i32*, i32, , i32, i32) define @test_vlsseg2_nxv8i32(i32* %base, i32 %offset, i32 %vl) { @@ -1425,7 +1425,7 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1439,14 +1439,14 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i32( %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1456,7 +1456,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1470,14 +1470,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i8(i8*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv4i8(,,, i8*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i8(,,, i8*, i32, , i32, i32) define @test_vlsseg3_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1487,7 +1487,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1502,14 +1502,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i8( %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i8(,,,, i8*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i8(,,,, i8*, i32, , i32, i32) define @test_vlsseg4_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1519,7 +1519,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1535,14 +1535,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i8( %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4i8(,,,,, i8*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i8(,,,,, i8*, i32, , i32, i32) define @test_vlsseg5_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1552,7 +1552,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1569,14 +1569,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i8( %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(,,,,,, i8*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i8(,,,,,, i8*, i32, , i32, i32) define @test_vlsseg6_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1586,7 +1586,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1604,14 +1604,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i8( %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(,,,,,,, i8*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i8(,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg7_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1621,7 +1621,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1640,14 +1640,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(,,,,,,,, i8*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i8(,,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg8_nxv4i8(i8* %base, i32 %offset, i32 %vl) { @@ -1657,7 +1657,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1677,14 +1677,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i16(i16*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1i16(,, i16*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i16(,, i16*, i32, , i32, i32) define @test_vlsseg2_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1694,7 +1694,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1708,14 +1708,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i16( %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i16(i16*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1i16(,,, i16*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i16(,,, i16*, i32, , i32, i32) define @test_vlsseg3_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1725,7 +1725,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1740,14 +1740,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i16( %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i16(,,,, i16*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i16(,,,, i16*, i32, , i32, i32) define @test_vlsseg4_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1757,7 +1757,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1773,14 +1773,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i16( %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i16(,,,,, i16*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i16(,,,,, i16*, i32, , i32, i32) define @test_vlsseg5_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1790,7 +1790,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1807,14 +1807,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i16( %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(,,,,,, i16*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i16(,,,,,, i16*, i32, , i32, i32) define @test_vlsseg6_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1824,7 +1824,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1842,14 +1842,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i16( %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(,,,,,,, i16*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i16(,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg7_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1859,7 +1859,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1878,14 +1878,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(,,,,,,,, i16*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i16(,,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg8_nxv1i16(i16* %base, i32 %offset, i32 %vl) { @@ -1895,7 +1895,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1915,14 +1915,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv32i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv32i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv32i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv32i8(i8* %base, i32 %offset, i32 %vl) { @@ -1932,7 +1932,7 @@ ; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1946,14 +1946,14 @@ ; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv32i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i8(i8*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2i8(,, i8*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i8(,, i8*, i32, , i32, i32) define @test_vlsseg2_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -1963,7 +1963,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1977,14 +1977,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8( undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i8( %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i8(i8*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2i8(,,, i8*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i8(,,, i8*, i32, , i32, i32) define @test_vlsseg3_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -1994,7 +1994,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2009,14 +2009,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8( undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i8( %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i8(,,,, i8*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i8(,,,, i8*, i32, , i32, i32) define @test_vlsseg4_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -2026,7 +2026,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2042,14 +2042,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i8( %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i8(,,,,, i8*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i8(,,,,, i8*, i32, , i32, i32) define @test_vlsseg5_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -2059,7 +2059,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2076,14 +2076,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i8( %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(,,,,,, i8*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i8(,,,,,, i8*, i32, , i32, i32) define @test_vlsseg6_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -2093,7 +2093,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2111,14 +2111,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i8( %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(,,,,,,, i8*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i8(,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg7_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -2128,7 +2128,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2147,14 +2147,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(,,,,,,,, i8*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i8(,,,,,,,, i8*, i32, , i32, i32) define @test_vlsseg8_nxv2i8(i8* %base, i32 %offset, i32 %vl) { @@ -2164,7 +2164,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2184,14 +2184,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i16(i16*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2i16(,, i16*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i16(,, i16*, i32, , i32, i32) define @test_vlsseg2_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2201,7 +2201,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2215,14 +2215,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16( undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i16( %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i16(i16*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2i16(,,, i16*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i16(,,, i16*, i32, , i32, i32) define @test_vlsseg3_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2232,7 +2232,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2247,14 +2247,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16( undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i16( %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i16(,,,, i16*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i16(,,,, i16*, i32, , i32, i32) define @test_vlsseg4_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2264,7 +2264,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2280,14 +2280,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i16( %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i16(,,,,, i16*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i16(,,,,, i16*, i32, , i32, i32) define @test_vlsseg5_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2314,14 +2314,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i16( %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(,,,,,, i16*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i16(,,,,,, i16*, i32, , i32, i32) define @test_vlsseg6_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2331,7 +2331,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2349,14 +2349,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i16( %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(,,,,,,, i16*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i16(,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg7_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2366,7 +2366,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2385,14 +2385,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(,,,,,,,, i16*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i16(,,,,,,,, i16*, i32, , i32, i32) define @test_vlsseg8_nxv2i16(i16* %base, i32 %offset, i32 %vl) { @@ -2402,7 +2402,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2422,14 +2422,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i32(i32*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4i32(,, i32*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i32(,, i32*, i32, , i32, i32) define @test_vlsseg2_nxv4i32(i32* %base, i32 %offset, i32 %vl) { @@ -2439,7 +2439,7 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2453,14 +2453,14 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32( undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i32( %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i32(i32*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv4i32(,,, i32*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i32(,,, i32*, i32, , i32, i32) define @test_vlsseg3_nxv4i32(i32* %base, i32 %offset, i32 %vl) { @@ -2470,7 +2470,7 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2485,14 +2485,14 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32( undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i32( %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i32(,,,, i32*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i32(,,,, i32*, i32, , i32, i32) define @test_vlsseg4_nxv4i32(i32* %base, i32 %offset, i32 %vl) { @@ -2502,7 +2502,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2518,14 +2518,14 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i32( %1, %1, %1, %1, i32* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv16f16(half*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv16f16(,, half*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv16f16(,, half*, i32, , i32, i32) define @test_vlsseg2_nxv16f16(half* %base, i32 %offset, i32 %vl) { @@ -2535,7 +2535,7 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2549,14 +2549,14 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16f16( %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f64(double*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4f64(,, double*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f64(,, double*, i32, , i32, i32) define @test_vlsseg2_nxv4f64(double* %base, i32 %offset, i32 %vl) { @@ -2566,7 +2566,7 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2580,14 +2580,14 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f64( %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f64(double*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1f64(,, double*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f64(,, double*, i32, , i32, i32) define @test_vlsseg2_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2597,7 +2597,7 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2611,14 +2611,14 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f64( %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f64(double*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1f64(,,, double*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f64(,,, double*, i32, , i32, i32) define @test_vlsseg3_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2628,7 +2628,7 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64( undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2643,14 +2643,14 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64( undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f64( %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f64(double*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f64(,,,, double*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f64(,,,, double*, i32, , i32, i32) define @test_vlsseg4_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2660,7 +2660,7 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64( undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2676,14 +2676,14 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64( undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f64( %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f64(,,,,, double*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f64(,,,,, double*, i32, , i32, i32) define @test_vlsseg5_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2693,7 +2693,7 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2710,14 +2710,14 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f64( %1, %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(,,,,,, double*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f64(,,,,,, double*, i32, , i32, i32) define @test_vlsseg6_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2727,7 +2727,7 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2745,14 +2745,14 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f64( %1, %1, %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(,,,,,,, double*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f64(,,,,,,, double*, i32, , i32, i32) define @test_vlsseg7_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2762,7 +2762,7 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2781,14 +2781,14 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(,,,,,,,, double*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f64(,,,,,,,, double*, i32, , i32, i32) define @test_vlsseg8_nxv1f64(double* %base, i32 %offset, i32 %vl) { @@ -2798,7 +2798,7 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2818,14 +2818,14 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f32(float*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2f32(,, float*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f32(,, float*, i32, , i32, i32) define @test_vlsseg2_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -2835,7 +2835,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2849,14 +2849,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f32( %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f32(float*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2f32(,,, float*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f32(,,, float*, i32, , i32, i32) define @test_vlsseg3_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -2866,7 +2866,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2881,14 +2881,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f32( %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f32(float*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f32(,,,, float*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f32(,,,, float*, i32, , i32, i32) define @test_vlsseg4_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -2898,7 +2898,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2914,14 +2914,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f32( %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2f32(,,,,, float*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f32(,,,,, float*, i32, , i32, i32) define @test_vlsseg5_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -2931,7 +2931,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2948,14 +2948,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f32( %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(,,,,,, float*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f32(,,,,,, float*, i32, , i32, i32) define @test_vlsseg6_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -2965,7 +2965,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2983,14 +2983,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f32( %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(,,,,,,, float*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f32(,,,,,,, float*, i32, , i32, i32) define @test_vlsseg7_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -3000,7 +3000,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3019,14 +3019,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(,,,,,,,, float*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f32(,,,,,,,, float*, i32, , i32, i32) define @test_vlsseg8_nxv2f32(float* %base, i32 %offset, i32 %vl) { @@ -3036,7 +3036,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3056,14 +3056,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f16(half*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1f16(,, half*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f16(,, half*, i32, , i32, i32) define @test_vlsseg2_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3073,7 +3073,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3087,14 +3087,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f16( %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f16(half*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1f16(,,, half*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f16(,,, half*, i32, , i32, i32) define @test_vlsseg3_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3104,7 +3104,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3119,14 +3119,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f16( %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f16(half*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f16(,,,, half*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f16(,,,, half*, i32, , i32, i32) define @test_vlsseg4_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3136,7 +3136,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3152,14 +3152,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f16( %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f16(,,,,, half*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f16(,,,,, half*, i32, , i32, i32) define @test_vlsseg5_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3169,7 +3169,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3186,14 +3186,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f16( %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(,,,,,, half*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f16(,,,,,, half*, i32, , i32, i32) define @test_vlsseg6_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3203,7 +3203,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3221,14 +3221,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f16( %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(,,,,,,, half*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f16(,,,,,,, half*, i32, , i32, i32) define @test_vlsseg7_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3238,7 +3238,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3257,14 +3257,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(,,,,,,,, half*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f16(,,,,,,,, half*, i32, , i32, i32) define @test_vlsseg8_nxv1f16(half* %base, i32 %offset, i32 %vl) { @@ -3274,7 +3274,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3294,14 +3294,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f32(float*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv1f32(,, float*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f32(,, float*, i32, , i32, i32) define @test_vlsseg2_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3311,7 +3311,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3325,14 +3325,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f32( %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f32(float*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv1f32(,,, float*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f32(,,, float*, i32, , i32, i32) define @test_vlsseg3_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3342,7 +3342,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3357,14 +3357,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f32( %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f32(float*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f32(,,,, float*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f32(,,,, float*, i32, , i32, i32) define @test_vlsseg4_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3374,7 +3374,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3390,14 +3390,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f32( %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f32(,,,,, float*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f32(,,,,, float*, i32, , i32, i32) define @test_vlsseg5_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3407,7 +3407,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3424,14 +3424,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f32( %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(,,,,,, float*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f32(,,,,,, float*, i32, , i32, i32) define @test_vlsseg6_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3441,7 +3441,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3459,14 +3459,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f32( %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(,,,,,,, float*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f32(,,,,,,, float*, i32, , i32, i32) define @test_vlsseg7_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3476,7 +3476,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3495,14 +3495,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(,,,,,,,, float*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f32(,,,,,,,, float*, i32, , i32, i32) define @test_vlsseg8_nxv1f32(float* %base, i32 %offset, i32 %vl) { @@ -3512,7 +3512,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3532,14 +3532,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8f16(half*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv8f16(,, half*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv8f16(,, half*, i32, , i32, i32) define @test_vlsseg2_nxv8f16(half* %base, i32 %offset, i32 %vl) { @@ -3549,7 +3549,7 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3563,14 +3563,14 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8f16( %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8f16(half*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv8f16(,,, half*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8f16(,,, half*, i32, , i32, i32) define @test_vlsseg3_nxv8f16(half* %base, i32 %offset, i32 %vl) { @@ -3580,7 +3580,7 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3595,14 +3595,14 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8f16( %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8f16(half*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv8f16(,,,, half*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8f16(,,,, half*, i32, , i32, i32) define @test_vlsseg4_nxv8f16(half* %base, i32 %offset, i32 %vl) { @@ -3612,7 +3612,7 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3628,14 +3628,14 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8f16( %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8f32(float*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv8f32(,, float*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv8f32(,, float*, i32, , i32, i32) define @test_vlsseg2_nxv8f32(float* %base, i32 %offset, i32 %vl) { @@ -3645,7 +3645,7 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3659,14 +3659,14 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8f32( %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f64(double*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2f64(,, double*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f64(,, double*, i32, , i32, i32) define @test_vlsseg2_nxv2f64(double* %base, i32 %offset, i32 %vl) { @@ -3676,7 +3676,7 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3690,14 +3690,14 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64( undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f64( %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f64(double*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2f64(,,, double*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f64(,,, double*, i32, , i32, i32) define @test_vlsseg3_nxv2f64(double* %base, i32 %offset, i32 %vl) { @@ -3707,7 +3707,7 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64( undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3722,14 +3722,14 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64( undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f64( %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f64(double*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f64(,,,, double*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f64(,,,, double*, i32, , i32, i32) define @test_vlsseg4_nxv2f64(double* %base, i32 %offset, i32 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64( undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3755,14 +3755,14 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64( undef, undef, undef, undef, double* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f64( %1, %1, %1, %1, double* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f16(half*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4f16(,, half*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f16(,, half*, i32, , i32, i32) define @test_vlsseg2_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3772,7 +3772,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3786,14 +3786,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f16( %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4f16(half*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv4f16(,,, half*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4f16(,,, half*, i32, , i32, i32) define @test_vlsseg3_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3803,7 +3803,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3818,14 +3818,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4f16( %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4f16(half*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv4f16(,,,, half*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4f16(,,,, half*, i32, , i32, i32) define @test_vlsseg4_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3835,7 +3835,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3851,14 +3851,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4f16( %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4f16(,,,,, half*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4f16(,,,,, half*, i32, , i32, i32) define @test_vlsseg5_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3868,7 +3868,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3885,14 +3885,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4f16( %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(,,,,,, half*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4f16(,,,,,, half*, i32, , i32, i32) define @test_vlsseg6_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3902,7 +3902,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3920,14 +3920,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4f16( %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(,,,,,,, half*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4f16(,,,,,,, half*, i32, , i32, i32) define @test_vlsseg7_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3937,7 +3937,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3956,14 +3956,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(,,,,,,,, half*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4f16(,,,,,,,, half*, i32, , i32, i32) define @test_vlsseg8_nxv4f16(half* %base, i32 %offset, i32 %vl) { @@ -3973,7 +3973,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3993,14 +3993,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f16(half*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv2f16(,, half*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f16(,, half*, i32, , i32, i32) define @test_vlsseg2_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4024,14 +4024,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16( undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f16( %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f16(half*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv2f16(,,, half*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f16(,,, half*, i32, , i32, i32) define @test_vlsseg3_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4041,7 +4041,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4056,14 +4056,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16( undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f16( %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f16(half*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f16(,,,, half*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f16(,,,, half*, i32, , i32, i32) define @test_vlsseg4_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4073,7 +4073,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4089,14 +4089,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16( undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f16( %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half*, i32, i32) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2f16(,,,,, half*, i32, i32) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f16(,,,,, half*, i32, , i32, i32) define @test_vlsseg5_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4106,7 +4106,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4123,14 +4123,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f16( %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half*, i32, i32) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(,,,,,, half*, i32, i32) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f16(,,,,,, half*, i32, , i32, i32) define @test_vlsseg6_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4140,7 +4140,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4158,14 +4158,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f16( %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half*, i32, i32) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(,,,,,,, half*, i32, i32) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f16(,,,,,,, half*, i32, , i32, i32) define @test_vlsseg7_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4175,7 +4175,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4194,14 +4194,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half*, i32, i32) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(,,,,,,,, half*, i32, i32) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f16(,,,,,,,, half*, i32, , i32, i32) define @test_vlsseg8_nxv2f16(half* %base, i32 %offset, i32 %vl) { @@ -4211,7 +4211,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4231,14 +4231,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f32(float*, i32, i32) +declare {,} @llvm.riscv.vlsseg2.nxv4f32(,, float*, i32, i32) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f32(,, float*, i32, , i32, i32) define @test_vlsseg2_nxv4f32(float* %base, i32 %offset, i32 %vl) { @@ -4248,7 +4248,7 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4262,14 +4262,14 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32( undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f32( %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4f32(float*, i32, i32) +declare {,,} @llvm.riscv.vlsseg3.nxv4f32(,,, float*, i32, i32) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4f32(,,, float*, i32, , i32, i32) define @test_vlsseg3_nxv4f32(float* %base, i32 %offset, i32 %vl) { @@ -4279,7 +4279,7 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4294,14 +4294,14 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32( undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4f32( %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4f32(float*, i32, i32) +declare {,,,} @llvm.riscv.vlsseg4.nxv4f32(,,,, float*, i32, i32) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4f32(,,,, float*, i32, , i32, i32) define @test_vlsseg4_nxv4f32(float* %base, i32 %offset, i32 %vl) { @@ -4311,7 +4311,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4327,7 +4327,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i32 %offset, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32( undef, undef, undef, undef, float* %base, i32 %offset, i32 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4f32( %1, %1, %1, %1, float* %base, i32 %offset, %mask, i32 %vl, i32 1) %3 = extractvalue {,,,} %2, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv16i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv16i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_nxv16i16(i16* %base, i64 %offset, i64 %vl) { @@ -12,7 +12,7 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -26,14 +26,14 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16i16( %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i32(i32*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4i32(,, i32*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i32(,, i32*, i64, , i64, i64) define @test_vlsseg2_nxv4i32(i32* %base, i64 %offset, i64 %vl) { @@ -43,7 +43,7 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -57,14 +57,14 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i32( %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i32(i32*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv4i32(,,, i32*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i32(,,, i32*, i64, , i64, i64) define @test_vlsseg3_nxv4i32(i32* %base, i64 %offset, i64 %vl) { @@ -74,7 +74,7 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -89,14 +89,14 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i32( %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i32(,,,, i32*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i32(,,,, i32*, i64, , i64, i64) define @test_vlsseg4_nxv4i32(i32* %base, i64 %offset, i64 %vl) { @@ -106,7 +106,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -122,14 +122,14 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i32( %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv16i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv16i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv16i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv16i8(i8* %base, i64 %offset, i64 %vl) { @@ -139,7 +139,7 @@ ; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -153,14 +153,14 @@ ; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv16i8(i8*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv16i8(,,, i8*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv16i8(,,, i8*, i64, , i64, i64) define @test_vlsseg3_nxv16i8(i8* %base, i64 %offset, i64 %vl) { @@ -170,7 +170,7 @@ ; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -185,14 +185,14 @@ ; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv16i8( %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv16i8(,,,, i8*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv16i8(,,,, i8*, i64, , i64, i64) define @test_vlsseg4_nxv16i8(i8* %base, i64 %offset, i64 %vl) { @@ -202,7 +202,7 @@ ; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -218,14 +218,14 @@ ; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv16i8( %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i64(i64*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1i64(,, i64*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i64(,, i64*, i64, , i64, i64) define @test_vlsseg2_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -235,7 +235,7 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -249,14 +249,14 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i64( %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i64(i64*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1i64(,,, i64*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i64(,,, i64*, i64, , i64, i64) define @test_vlsseg3_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -266,7 +266,7 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64( undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -281,14 +281,14 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64( undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i64( %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i64(i64*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i64(,,,, i64*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i64(,,,, i64*, i64, , i64, i64) define @test_vlsseg4_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -298,7 +298,7 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64( undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -314,14 +314,14 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64( undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i64( %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i64(i64*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i64(,,,,, i64*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i64(,,,,, i64*, i64, , i64, i64) define @test_vlsseg5_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -331,7 +331,7 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64( undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -348,14 +348,14 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64( undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i64( %1, %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(i64*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(,,,,,, i64*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i64(,,,,,, i64*, i64, , i64, i64) define @test_vlsseg6_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -365,7 +365,7 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -383,14 +383,14 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i64( %1, %1, %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(i64*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(,,,,,,, i64*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i64(,,,,,,, i64*, i64, , i64, i64) define @test_vlsseg7_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -400,7 +400,7 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -419,14 +419,14 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i64( %1, %1, %1, %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(i64*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(,,,,,,,, i64*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i64(,,,,,,,, i64*, i64, , i64, i64) define @test_vlsseg8_nxv1i64(i64* %base, i64 %offset, i64 %vl) { @@ -436,7 +436,7 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -456,14 +456,14 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i64( %1, %1, %1, %1, %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i32(i32*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1i32(,, i32*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i32(,, i32*, i64, , i64, i64) define @test_vlsseg2_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -473,7 +473,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -487,14 +487,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i32( %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i32(i32*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1i32(,,, i32*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i32(,,, i32*, i64, , i64, i64) define @test_vlsseg3_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -504,7 +504,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -519,14 +519,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i32( %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i32(,,,, i32*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i32(,,,, i32*, i64, , i64, i64) define @test_vlsseg4_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -536,7 +536,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -552,14 +552,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i32( %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i32(,,,,, i32*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i32(,,,,, i32*, i64, , i64, i64) define @test_vlsseg5_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -569,7 +569,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -586,14 +586,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32( undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i32( %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(,,,,,, i32*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i32(,,,,,, i32*, i64, , i64, i64) define @test_vlsseg6_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -603,7 +603,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -621,14 +621,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i32( %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(,,,,,,, i32*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i32(,,,,,,, i32*, i64, , i64, i64) define @test_vlsseg7_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -638,7 +638,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -657,14 +657,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(,,,,,,,, i32*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i32(,,,,,,,, i32*, i64, , i64, i64) define @test_vlsseg8_nxv1i32(i32* %base, i64 %offset, i64 %vl) { @@ -674,7 +674,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -694,14 +694,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv8i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_nxv8i16(i16* %base, i64 %offset, i64 %vl) { @@ -711,7 +711,7 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -725,14 +725,14 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i16( %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8i16(i16*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv8i16(,,, i16*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8i16(,,, i16*, i64, , i64, i64) define @test_vlsseg3_nxv8i16(i16* %base, i64 %offset, i64 %vl) { @@ -742,7 +742,7 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -757,14 +757,14 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8i16( %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv8i16(,,,, i16*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8i16(,,,, i16*, i64, , i64, i64) define @test_vlsseg4_nxv8i16(i16* %base, i64 %offset, i64 %vl) { @@ -774,7 +774,7 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -790,14 +790,14 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8i16( %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -807,7 +807,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -821,14 +821,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i8(i8*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv4i8(,,, i8*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i8(,,, i8*, i64, , i64, i64) define @test_vlsseg3_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -838,7 +838,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -853,14 +853,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i8( %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i8(,,,, i8*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i8(,,,, i8*, i64, , i64, i64) define @test_vlsseg4_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -870,7 +870,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -886,14 +886,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i8( %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4i8(,,,,, i8*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i8(,,,,, i8*, i64, , i64, i64) define @test_vlsseg5_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -903,7 +903,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -920,14 +920,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i8( %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(,,,,,, i8*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i8(,,,,,, i8*, i64, , i64, i64) define @test_vlsseg6_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -937,7 +937,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -955,14 +955,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i8( %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(,,,,,,, i8*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i8(,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg7_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -972,7 +972,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -991,14 +991,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(,,,,,,,, i8*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i8(,,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg8_nxv4i8(i8* %base, i64 %offset, i64 %vl) { @@ -1008,7 +1008,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1028,14 +1028,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1045,7 +1045,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1059,14 +1059,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i16( %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i16(i16*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1i16(,,, i16*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i16(,,, i16*, i64, , i64, i64) define @test_vlsseg3_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1076,7 +1076,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1091,14 +1091,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i16( %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i16(,,,, i16*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i16(,,,, i16*, i64, , i64, i64) define @test_vlsseg4_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1108,7 +1108,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1124,14 +1124,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i16( %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i16(,,,,, i16*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i16(,,,,, i16*, i64, , i64, i64) define @test_vlsseg5_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1141,7 +1141,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1158,14 +1158,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i16( %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(,,,,,, i16*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i16(,,,,,, i16*, i64, , i64, i64) define @test_vlsseg6_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1175,7 +1175,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1193,14 +1193,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i16( %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(,,,,,,, i16*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i16(,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg7_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1210,7 +1210,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1229,14 +1229,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(,,,,,,,, i16*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i16(,,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg8_nxv1i16(i16* %base, i64 %offset, i64 %vl) { @@ -1246,7 +1246,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1266,14 +1266,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i32(i32*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2i32(,, i32*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i32(,, i32*, i64, , i64, i64) define @test_vlsseg2_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1283,7 +1283,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1297,14 +1297,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i32( %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i32(i32*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2i32(,,, i32*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i32(,,, i32*, i64, , i64, i64) define @test_vlsseg3_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1314,7 +1314,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1329,14 +1329,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32( undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i32( %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i32(,,,, i32*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i32(,,,, i32*, i64, , i64, i64) define @test_vlsseg4_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1346,7 +1346,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1362,14 +1362,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32( undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i32( %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i32(,,,,, i32*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i32(,,,,, i32*, i64, , i64, i64) define @test_vlsseg5_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1379,7 +1379,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1396,14 +1396,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32( undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i32( %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(,,,,,, i32*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i32(,,,,,, i32*, i64, , i64, i64) define @test_vlsseg6_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1413,7 +1413,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1431,14 +1431,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i32( %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(,,,,,,, i32*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i32(,,,,,,, i32*, i64, , i64, i64) define @test_vlsseg7_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1448,7 +1448,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1467,14 +1467,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(,,,,,,,, i32*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i32(,,,,,,,, i32*, i64, , i64, i64) define @test_vlsseg8_nxv2i32(i32* %base, i64 %offset, i64 %vl) { @@ -1484,7 +1484,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1504,14 +1504,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i32( %1, %1, %1, %1, %1, %1, %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv8i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1521,7 +1521,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1535,14 +1535,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8i8(i8*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv8i8(,,, i8*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8i8(,,, i8*, i64, , i64, i64) define @test_vlsseg3_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1552,7 +1552,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1567,14 +1567,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8i8( %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv8i8(,,,, i8*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8i8(,,,, i8*, i64, , i64, i64) define @test_vlsseg4_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1584,7 +1584,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1600,14 +1600,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8i8( %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv8i8(,,,,, i8*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv8i8(,,,,, i8*, i64, , i64, i64) define @test_vlsseg5_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1617,7 +1617,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1634,14 +1634,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv8i8( %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(,,,,,, i8*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv8i8(,,,,,, i8*, i64, , i64, i64) define @test_vlsseg6_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1651,7 +1651,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1669,14 +1669,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv8i8( %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(,,,,,,, i8*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv8i8(,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg7_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1686,7 +1686,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1705,14 +1705,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(,,,,,,,, i8*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv8i8(,,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg8_nxv8i8(i8* %base, i64 %offset, i64 %vl) { @@ -1722,7 +1722,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1742,14 +1742,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv8i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i64(i64*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4i64(,, i64*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i64(,, i64*, i64, , i64, i64) define @test_vlsseg2_nxv4i64(i64* %base, i64 %offset, i64 %vl) { @@ -1759,7 +1759,7 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1773,14 +1773,14 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i64( %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1790,7 +1790,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1804,14 +1804,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4i16( %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4i16(i16*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv4i16(,,, i16*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4i16(,,, i16*, i64, , i64, i64) define @test_vlsseg3_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1821,7 +1821,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1836,14 +1836,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4i16( %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv4i16(,,,, i16*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4i16(,,,, i16*, i64, , i64, i64) define @test_vlsseg4_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1853,7 +1853,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1869,14 +1869,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4i16( %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4i16(,,,,, i16*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i16(,,,,, i16*, i64, , i64, i64) define @test_vlsseg5_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1886,7 +1886,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1903,14 +1903,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4i16( %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(,,,,,, i16*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i16(,,,,,, i16*, i64, , i64, i64) define @test_vlsseg6_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1920,7 +1920,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1938,14 +1938,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4i16( %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(,,,,,,, i16*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i16(,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg7_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1955,7 +1955,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1974,14 +1974,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(,,,,,,,, i16*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i16(,,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg8_nxv4i16(i16* %base, i64 %offset, i64 %vl) { @@ -1991,7 +1991,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2011,14 +2011,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2028,7 +2028,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2042,14 +2042,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1i8(i8*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1i8(,,, i8*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1i8(,,, i8*, i64, , i64, i64) define @test_vlsseg3_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2059,7 +2059,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2074,14 +2074,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1i8( %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1i8(,,,, i8*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1i8(,,,, i8*, i64, , i64, i64) define @test_vlsseg4_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2091,7 +2091,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2107,14 +2107,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1i8( %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1i8(,,,,, i8*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i8(,,,,, i8*, i64, , i64, i64) define @test_vlsseg5_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2124,7 +2124,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2141,14 +2141,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1i8( %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(,,,,,, i8*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i8(,,,,,, i8*, i64, , i64, i64) define @test_vlsseg6_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2158,7 +2158,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2176,14 +2176,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1i8( %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(,,,,,,, i8*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i8(,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg7_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2193,7 +2193,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2212,14 +2212,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(,,,,,,,, i8*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i8(,,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg8_nxv1i8(i8* %base, i64 %offset, i64 %vl) { @@ -2229,7 +2229,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2249,14 +2249,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2266,7 +2266,7 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2280,14 +2280,14 @@ ; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i8(i8*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2i8(,,, i8*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i8(,,, i8*, i64, , i64, i64) define @test_vlsseg3_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2312,14 +2312,14 @@ ; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8( undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i8( %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i8(,,,, i8*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i8(,,,, i8*, i64, , i64, i64) define @test_vlsseg4_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2329,7 +2329,7 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2345,14 +2345,14 @@ ; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8( undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i8( %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i8(,,,,, i8*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i8(,,,,, i8*, i64, , i64, i64) define @test_vlsseg5_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2362,7 +2362,7 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2379,14 +2379,14 @@ ; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8( undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i8( %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(,,,,,, i8*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i8(,,,,,, i8*, i64, , i64, i64) define @test_vlsseg6_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2396,7 +2396,7 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2414,14 +2414,14 @@ ; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i8( %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(,,,,,,, i8*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i8(,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg7_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2431,7 +2431,7 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2450,14 +2450,14 @@ ; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(,,,,,,,, i8*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i8(,,,,,,,, i8*, i64, , i64, i64) define @test_vlsseg8_nxv2i8(i8* %base, i64 %offset, i64 %vl) { @@ -2467,7 +2467,7 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2487,14 +2487,14 @@ ; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i8( %1, %1, %1, %1, %1, %1, %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8i32(i32*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv8i32(,, i32*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv8i32(,, i32*, i64, , i64, i64) define @test_vlsseg2_nxv8i32(i32* %base, i64 %offset, i64 %vl) { @@ -2504,7 +2504,7 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2518,14 +2518,14 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32( undef, undef, i32* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8i32( %1, %1, i32* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv32i8(i8*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv32i8(,, i8*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv32i8(,, i8*, i64, , i64, i64) define @test_vlsseg2_nxv32i8(i8* %base, i64 %offset, i64 %vl) { @@ -2535,7 +2535,7 @@ ; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2549,14 +2549,14 @@ ; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8( undef, undef, i8* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv32i8( %1, %1, i8* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2566,7 +2566,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2580,14 +2580,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16( undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i16( %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i16(i16*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2i16(,,, i16*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i16(,,, i16*, i64, , i64, i64) define @test_vlsseg3_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2597,7 +2597,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2612,14 +2612,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16( undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i16( %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i16(,,,, i16*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i16(,,,, i16*, i64, , i64, i64) define @test_vlsseg4_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2629,7 +2629,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2645,14 +2645,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16( undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i16( %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2i16(,,,,, i16*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i16(,,,,, i16*, i64, , i64, i64) define @test_vlsseg5_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2662,7 +2662,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2679,14 +2679,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16( undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2i16( %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(,,,,,, i16*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i16(,,,,,, i16*, i64, , i64, i64) define @test_vlsseg6_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2696,7 +2696,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2714,14 +2714,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2i16( %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(,,,,,,, i16*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i16(,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg7_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2731,7 +2731,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2750,14 +2750,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(,,,,,,,, i16*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i16(,,,,,,,, i16*, i64, , i64, i64) define @test_vlsseg8_nxv2i16(i16* %base, i64 %offset, i64 %vl) { @@ -2767,7 +2767,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2787,14 +2787,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2i16( %1, %1, %1, %1, %1, %1, %1, %1, i16* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2i64(i64*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2i64(,, i64*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2i64(,, i64*, i64, , i64, i64) define @test_vlsseg2_nxv2i64(i64* %base, i64 %offset, i64 %vl) { @@ -2804,7 +2804,7 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2818,14 +2818,14 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64( undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2i64( %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2i64(i64*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2i64(,,, i64*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2i64(,,, i64*, i64, , i64, i64) define @test_vlsseg3_nxv2i64(i64* %base, i64 %offset, i64 %vl) { @@ -2835,7 +2835,7 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64( undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2850,14 +2850,14 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64( undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2i64( %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2i64(i64*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2i64(,,,, i64*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2i64(,,,, i64*, i64, , i64, i64) define @test_vlsseg4_nxv2i64(i64* %base, i64 %offset, i64 %vl) { @@ -2867,7 +2867,7 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64( undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2883,14 +2883,14 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64(i64* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64( undef, undef, undef, undef, i64* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2i64( %1, %1, %1, %1, i64* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv16f16(half*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv16f16(,, half*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv16f16(,, half*, i64, , i64, i64) define @test_vlsseg2_nxv16f16(half* %base, i64 %offset, i64 %vl) { @@ -2900,7 +2900,7 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2914,14 +2914,14 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16f16( %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f64(double*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4f64(,, double*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f64(,, double*, i64, , i64, i64) define @test_vlsseg2_nxv4f64(double* %base, i64 %offset, i64 %vl) { @@ -2931,7 +2931,7 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2945,14 +2945,14 @@ ; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f64( %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f64(double*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1f64(,, double*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f64(,, double*, i64, , i64, i64) define @test_vlsseg2_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -2962,7 +2962,7 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2976,14 +2976,14 @@ ; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f64( %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f64(double*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1f64(,,, double*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f64(,,, double*, i64, , i64, i64) define @test_vlsseg3_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -2993,7 +2993,7 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64( undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3008,14 +3008,14 @@ ; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64( undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f64( %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f64(double*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f64(,,,, double*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f64(,,,, double*, i64, , i64, i64) define @test_vlsseg4_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -3025,7 +3025,7 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64( undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3041,14 +3041,14 @@ ; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64( undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f64( %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f64(,,,,, double*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f64(,,,,, double*, i64, , i64, i64) define @test_vlsseg5_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -3058,7 +3058,7 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3075,14 +3075,14 @@ ; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64( undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f64( %1, %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(,,,,,, double*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f64(,,,,,, double*, i64, , i64, i64) define @test_vlsseg6_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -3092,7 +3092,7 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3110,14 +3110,14 @@ ; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64( undef, undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f64( %1, %1, %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(,,,,,,, double*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f64(,,,,,,, double*, i64, , i64, i64) define @test_vlsseg7_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -3127,7 +3127,7 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3146,14 +3146,14 @@ ; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64( undef, undef, undef, undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(,,,,,,,, double*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f64(,,,,,,,, double*, i64, , i64, i64) define @test_vlsseg8_nxv1f64(double* %base, i64 %offset, i64 %vl) { @@ -3163,7 +3163,7 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3183,14 +3183,14 @@ ; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f64( %1, %1, %1, %1, %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f32(float*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2f32(,, float*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f32(,, float*, i64, , i64, i64) define @test_vlsseg2_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3200,7 +3200,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3214,14 +3214,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f32( %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f32(float*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2f32(,,, float*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f32(,,, float*, i64, , i64, i64) define @test_vlsseg3_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3231,7 +3231,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3246,14 +3246,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f32( %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f32(float*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f32(,,,, float*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f32(,,,, float*, i64, , i64, i64) define @test_vlsseg4_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3263,7 +3263,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3279,14 +3279,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f32( %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2f32(,,,,, float*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f32(,,,,, float*, i64, , i64, i64) define @test_vlsseg5_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3296,7 +3296,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3313,14 +3313,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32( undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f32( %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(,,,,,, float*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f32(,,,,,, float*, i64, , i64, i64) define @test_vlsseg6_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3330,7 +3330,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3348,14 +3348,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f32( %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(,,,,,,, float*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f32(,,,,,,, float*, i64, , i64, i64) define @test_vlsseg7_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3365,7 +3365,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3384,14 +3384,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(,,,,,,,, float*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f32(,,,,,,,, float*, i64, , i64, i64) define @test_vlsseg8_nxv2f32(float* %base, i64 %offset, i64 %vl) { @@ -3401,7 +3401,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3421,14 +3421,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f16(half*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1f16(,, half*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f16(,, half*, i64, , i64, i64) define @test_vlsseg2_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3438,7 +3438,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3452,14 +3452,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f16( %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f16(half*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1f16(,,, half*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f16(,,, half*, i64, , i64, i64) define @test_vlsseg3_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3469,7 +3469,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3484,14 +3484,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f16( %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f16(half*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f16(,,,, half*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f16(,,,, half*, i64, , i64, i64) define @test_vlsseg4_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3501,7 +3501,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3517,14 +3517,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f16( %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f16(,,,,, half*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f16(,,,,, half*, i64, , i64, i64) define @test_vlsseg5_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3534,7 +3534,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3551,14 +3551,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f16( %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(,,,,,, half*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f16(,,,,,, half*, i64, , i64, i64) define @test_vlsseg6_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3568,7 +3568,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3586,14 +3586,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f16( %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(,,,,,,, half*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f16(,,,,,,, half*, i64, , i64, i64) define @test_vlsseg7_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3603,7 +3603,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3622,14 +3622,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(,,,,,,,, half*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f16(,,,,,,,, half*, i64, , i64, i64) define @test_vlsseg8_nxv1f16(half* %base, i64 %offset, i64 %vl) { @@ -3639,7 +3639,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3659,14 +3659,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv1f32(float*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv1f32(,, float*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv1f32(,, float*, i64, , i64, i64) define @test_vlsseg2_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3676,7 +3676,7 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3690,14 +3690,14 @@ ; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv1f32( %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv1f32(float*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv1f32(,,, float*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv1f32(,,, float*, i64, , i64, i64) define @test_vlsseg3_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3707,7 +3707,7 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3722,14 +3722,14 @@ ; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv1f32( %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv1f32(float*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv1f32(,,,, float*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv1f32(,,,, float*, i64, , i64, i64) define @test_vlsseg4_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3755,14 +3755,14 @@ ; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv1f32( %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv1f32(,,,,, float*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f32(,,,,, float*, i64, , i64, i64) define @test_vlsseg5_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3772,7 +3772,7 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3789,14 +3789,14 @@ ; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32( undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv1f32( %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(,,,,,, float*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f32(,,,,,, float*, i64, , i64, i64) define @test_vlsseg6_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3806,7 +3806,7 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3824,14 +3824,14 @@ ; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32( undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv1f32( %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(,,,,,,, float*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f32(,,,,,,, float*, i64, , i64, i64) define @test_vlsseg7_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3841,7 +3841,7 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3860,14 +3860,14 @@ ; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32( undef, undef, undef, undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(,,,,,,,, float*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f32(,,,,,,,, float*, i64, , i64, i64) define @test_vlsseg8_nxv1f32(float* %base, i64 %offset, i64 %vl) { @@ -3877,7 +3877,7 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3897,14 +3897,14 @@ ; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv1f32( %1, %1, %1, %1, %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8f16(half*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv8f16(,, half*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv8f16(,, half*, i64, , i64, i64) define @test_vlsseg2_nxv8f16(half* %base, i64 %offset, i64 %vl) { @@ -3914,7 +3914,7 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3928,14 +3928,14 @@ ; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8f16( %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv8f16(half*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv8f16(,,, half*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv8f16(,,, half*, i64, , i64, i64) define @test_vlsseg3_nxv8f16(half* %base, i64 %offset, i64 %vl) { @@ -3945,7 +3945,7 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3960,14 +3960,14 @@ ; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv8f16( %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv8f16(half*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv8f16(,,,, half*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv8f16(,,,, half*, i64, , i64, i64) define @test_vlsseg4_nxv8f16(half* %base, i64 %offset, i64 %vl) { @@ -3977,7 +3977,7 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3993,14 +3993,14 @@ ; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv8f16( %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv8f32(float*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv8f32(,, float*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv8f32(,, float*, i64, , i64, i64) define @test_vlsseg2_nxv8f32(float* %base, i64 %offset, i64 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4024,14 +4024,14 @@ ; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv8f32( %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f64(double*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2f64(,, double*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f64(,, double*, i64, , i64, i64) define @test_vlsseg2_nxv2f64(double* %base, i64 %offset, i64 %vl) { @@ -4041,7 +4041,7 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4055,14 +4055,14 @@ ; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64( undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f64( %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f64(double*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2f64(,,, double*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f64(,,, double*, i64, , i64, i64) define @test_vlsseg3_nxv2f64(double* %base, i64 %offset, i64 %vl) { @@ -4072,7 +4072,7 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64( undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4087,14 +4087,14 @@ ; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64( undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f64( %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f64(double*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f64(,,,, double*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f64(,,,, double*, i64, , i64, i64) define @test_vlsseg4_nxv2f64(double* %base, i64 %offset, i64 %vl) { @@ -4104,7 +4104,7 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64( undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4120,14 +4120,14 @@ ; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64( undef, undef, undef, undef, double* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f64( %1, %1, %1, %1, double* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f16(half*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4f16(,, half*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f16(,, half*, i64, , i64, i64) define @test_vlsseg2_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4137,7 +4137,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4151,14 +4151,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f16( %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4f16(half*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv4f16(,,, half*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4f16(,,, half*, i64, , i64, i64) define @test_vlsseg3_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4168,7 +4168,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4183,14 +4183,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4f16( %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4f16(half*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv4f16(,,,, half*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4f16(,,,, half*, i64, , i64, i64) define @test_vlsseg4_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4200,7 +4200,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4216,14 +4216,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4f16( %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv4f16(,,,,, half*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv4f16(,,,,, half*, i64, , i64, i64) define @test_vlsseg5_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4233,7 +4233,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4250,14 +4250,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv4f16( %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(,,,,,, half*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4f16(,,,,,, half*, i64, , i64, i64) define @test_vlsseg6_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4267,7 +4267,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4285,14 +4285,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv4f16( %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(,,,,,,, half*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4f16(,,,,,,, half*, i64, , i64, i64) define @test_vlsseg7_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4302,7 +4302,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4321,14 +4321,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(,,,,,,,, half*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4f16(,,,,,,,, half*, i64, , i64, i64) define @test_vlsseg8_nxv4f16(half* %base, i64 %offset, i64 %vl) { @@ -4338,7 +4338,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4358,14 +4358,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv4f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv2f16(half*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv2f16(,, half*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv2f16(,, half*, i64, , i64, i64) define @test_vlsseg2_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4375,7 +4375,7 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4389,14 +4389,14 @@ ; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16( undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv2f16( %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv2f16(half*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv2f16(,,, half*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv2f16(,,, half*, i64, , i64, i64) define @test_vlsseg3_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4406,7 +4406,7 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4421,14 +4421,14 @@ ; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16( undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv2f16( %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv2f16(half*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv2f16(,,,, half*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv2f16(,,,, half*, i64, , i64, i64) define @test_vlsseg4_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4438,7 +4438,7 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4454,14 +4454,14 @@ ; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16( undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv2f16( %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 ret %3 } -declare {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half*, i64, i64) +declare {,,,,} @llvm.riscv.vlsseg5.nxv2f16(,,,,, half*, i64, i64) declare {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f16(,,,,, half*, i64, , i64, i64) define @test_vlsseg5_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4471,7 +4471,7 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4488,14 +4488,14 @@ ; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16( undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,} %0, 0 %2 = tail call {,,,,} @llvm.riscv.vlsseg5.mask.nxv2f16( %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,} %2, 1 ret %3 } -declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half*, i64, i64) +declare {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(,,,,,, half*, i64, i64) declare {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f16(,,,,,, half*, i64, , i64, i64) define @test_vlsseg6_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4505,7 +4505,7 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4523,14 +4523,14 @@ ; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16( undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,} %0, 0 %2 = tail call {,,,,,} @llvm.riscv.vlsseg6.mask.nxv2f16( %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,} %2, 1 ret %3 } -declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half*, i64, i64) +declare {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(,,,,,,, half*, i64, i64) declare {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f16(,,,,,,, half*, i64, , i64, i64) define @test_vlsseg7_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4540,7 +4540,7 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4559,14 +4559,14 @@ ; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16( undef, undef, undef, undef, undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,} %0, 0 %2 = tail call {,,,,,,} @llvm.riscv.vlsseg7.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,} %2, 1 ret %3 } -declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half*, i64, i64) +declare {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(,,,,,,,, half*, i64, i64) declare {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f16(,,,,,,,, half*, i64, , i64, i64) define @test_vlsseg8_nxv2f16(half* %base, i64 %offset, i64 %vl) { @@ -4576,7 +4576,7 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4596,14 +4596,14 @@ ; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 0 %2 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.mask.nxv2f16( %1, %1, %1, %1, %1, %1, %1, %1, half* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,,,,,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv4f32(float*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv4f32(,, float*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv4f32(,, float*, i64, , i64, i64) define @test_vlsseg2_nxv4f32(float* %base, i64 %offset, i64 %vl) { @@ -4613,7 +4613,7 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4627,14 +4627,14 @@ ; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32( undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv4f32( %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,,} @llvm.riscv.vlsseg3.nxv4f32(float*, i64, i64) +declare {,,} @llvm.riscv.vlsseg3.nxv4f32(,,, float*, i64, i64) declare {,,} @llvm.riscv.vlsseg3.mask.nxv4f32(,,, float*, i64, , i64, i64) define @test_vlsseg3_nxv4f32(float* %base, i64 %offset, i64 %vl) { @@ -4644,7 +4644,7 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4659,14 +4659,14 @@ ; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32( undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,} %0, 0 %2 = tail call {,,} @llvm.riscv.vlsseg3.mask.nxv4f32( %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,} %2, 1 ret %3 } -declare {,,,} @llvm.riscv.vlsseg4.nxv4f32(float*, i64, i64) +declare {,,,} @llvm.riscv.vlsseg4.nxv4f32(,,,, float*, i64, i64) declare {,,,} @llvm.riscv.vlsseg4.mask.nxv4f32(,,,, float*, i64, , i64, i64) define @test_vlsseg4_nxv4f32(float* %base, i64 %offset, i64 %vl) { @@ -4676,7 +4676,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4692,7 +4692,7 @@ ; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i64 %offset, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32( undef, undef, undef, undef, float* %base, i64 %offset, i64 %vl) %1 = extractvalue {,,,} %0, 0 %2 = tail call {,,,} @llvm.riscv.vlsseg4.mask.nxv4f32( %1, %1, %1, %1, float* %base, i64 %offset, %mask, i64 %vl, i64 1) %3 = extractvalue {,,,} %2, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i32, i32) define @test_vluxseg2_nxv16i16_nxv16i16(i16* %base, %index, i32 %vl) { @@ -13,7 +13,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -31,7 +31,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i8(,, i16*, , , i32, i32) define @test_vluxseg2_nxv16i16_nxv16i8(i16* %base, %index, i32 %vl) { @@ -42,7 +42,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -60,7 +60,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i32(,, i16*, , , i32, i32) define @test_vluxseg2_nxv16i16_nxv16i32(i16* %base, %index, i32 %vl) { @@ -71,7 +71,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -89,7 +89,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -100,7 +100,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -118,7 +118,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i32(,, i8*, , , i32, i32) define @test_vluxseg2_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -129,7 +129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -147,7 +147,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -158,7 +158,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -176,7 +176,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i8(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -187,7 +187,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -207,7 +207,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i32(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -218,7 +218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -238,7 +238,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i16(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -249,7 +249,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -269,7 +269,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i8(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -280,7 +280,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -302,7 +302,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i32(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -313,7 +313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -335,7 +335,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i16(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -346,7 +346,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -368,7 +368,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i8(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -379,7 +379,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -402,7 +402,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i32(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -413,7 +413,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -436,7 +436,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i16(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -447,7 +447,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -470,7 +470,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i8(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -481,7 +481,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -505,7 +505,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i32(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -516,7 +516,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -540,7 +540,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i16(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -551,7 +551,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -575,7 +575,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i8(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -586,7 +586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -611,7 +611,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i32(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -622,7 +622,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -647,7 +647,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i16(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -658,7 +658,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -683,7 +683,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i8(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv1i8_nxv1i8(i8* %base, %index, i32 %vl) { @@ -694,7 +694,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -720,7 +720,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i32(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv1i8_nxv1i32(i8* %base, %index, i32 %vl) { @@ -731,7 +731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -757,7 +757,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i16(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv1i8_nxv1i16(i8* %base, %index, i32 %vl) { @@ -768,7 +768,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -794,7 +794,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -805,7 +805,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -823,7 +823,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -834,7 +834,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -852,7 +852,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i32(,, i8*, , , i32, i32) define @test_vluxseg2_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -863,7 +863,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -881,7 +881,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i16(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -892,7 +892,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -911,7 +911,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i8(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -922,7 +922,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -942,7 +942,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i32(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -953,7 +953,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -972,7 +972,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i16(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv16i8_nxv16i16(i8* %base, %index, i32 %vl) { @@ -983,7 +983,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1004,7 +1004,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i8(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv16i8_nxv16i8(i8* %base, %index, i32 %vl) { @@ -1015,7 +1015,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1037,7 +1037,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i32(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv16i8_nxv16i32(i8* %base, %index, i32 %vl) { @@ -1048,7 +1048,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1068,7 +1068,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32(,, i32*, , , i32, i32) define @test_vluxseg2_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1079,7 +1079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1097,7 +1097,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i8(,, i32*, , , i32, i32) define @test_vluxseg2_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1108,7 +1108,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1126,7 +1126,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i16(,, i32*, , , i32, i32) define @test_vluxseg2_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1137,7 +1137,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1155,7 +1155,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i32(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1166,7 +1166,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1186,7 +1186,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i8(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1197,7 +1197,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1217,7 +1217,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i16(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1228,7 +1228,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1248,7 +1248,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i32(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1259,7 +1259,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1281,7 +1281,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i8(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1292,7 +1292,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1314,7 +1314,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i16(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1325,7 +1325,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1347,7 +1347,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i32(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1358,7 +1358,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1381,7 +1381,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i8(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1392,7 +1392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1415,7 +1415,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i16(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1426,7 +1426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1449,7 +1449,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i32(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1460,7 +1460,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1484,7 +1484,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i8(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1495,7 +1495,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1519,7 +1519,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i16(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1530,7 +1530,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1554,7 +1554,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i32(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1565,7 +1565,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1590,7 +1590,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i8(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1601,7 +1601,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1626,7 +1626,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i16(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1637,7 +1637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1662,7 +1662,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i32(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv2i32_nxv2i32(i32* %base, %index, i32 %vl) { @@ -1673,7 +1673,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1699,7 +1699,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i8(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv2i32_nxv2i8(i32* %base, %index, i32 %vl) { @@ -1710,7 +1710,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1736,7 +1736,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i16(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv2i32_nxv2i16(i32* %base, %index, i32 %vl) { @@ -1747,7 +1747,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1773,7 +1773,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i16(,, i16*, , , i32, i32) define @test_vluxseg2_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1784,7 +1784,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1802,7 +1802,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i8(,, i16*, , , i32, i32) define @test_vluxseg2_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1813,7 +1813,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1831,7 +1831,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i32(,, i16*, , , i32, i32) define @test_vluxseg2_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -1842,7 +1842,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1860,7 +1860,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i16(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1871,7 +1871,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1891,7 +1891,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i8(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1902,7 +1902,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1922,7 +1922,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i32(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -1933,7 +1933,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1952,7 +1952,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i16(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -1963,7 +1963,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1985,7 +1985,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i8(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -1996,7 +1996,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2018,7 +2018,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i32(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2029,7 +2029,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2050,7 +2050,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i16(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2061,7 +2061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2084,7 +2084,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i8(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2095,7 +2095,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2118,7 +2118,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i32(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2129,7 +2129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2152,7 +2152,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i16(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2163,7 +2163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2187,7 +2187,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i8(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2198,7 +2198,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2222,7 +2222,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i32(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2233,7 +2233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2257,7 +2257,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i16(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2268,7 +2268,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2293,7 +2293,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i8(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2304,7 +2304,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2329,7 +2329,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i32(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2340,7 +2340,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2365,7 +2365,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i16(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv4i16_nxv4i16(i16* %base, %index, i32 %vl) { @@ -2376,7 +2376,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2402,7 +2402,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i8(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv4i16_nxv4i8(i16* %base, %index, i32 %vl) { @@ -2413,7 +2413,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2439,7 +2439,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i32(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv4i16_nxv4i32(i16* %base, %index, i32 %vl) { @@ -2450,7 +2450,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2476,7 +2476,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i8(,, i32*, , , i32, i32) define @test_vluxseg2_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2487,7 +2487,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2505,7 +2505,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32(,, i32*, , , i32, i32) define @test_vluxseg2_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2516,7 +2516,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2534,7 +2534,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(,, i32*, , , i32, i32) define @test_vluxseg2_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2545,7 +2545,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2563,7 +2563,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i8(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2574,7 +2574,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2594,7 +2594,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i32(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2605,7 +2605,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2625,7 +2625,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2636,7 +2636,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2656,7 +2656,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i8(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2667,7 +2667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2689,7 +2689,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i32(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2700,7 +2700,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2722,7 +2722,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2733,7 +2733,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2755,7 +2755,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i8(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2766,7 +2766,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2789,7 +2789,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i32(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2800,7 +2800,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2823,7 +2823,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(,,,,, i32*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(,,,,, i32*, , , i32, i32) define @test_vluxseg5_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2834,7 +2834,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2857,7 +2857,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i8(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2868,7 +2868,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2892,7 +2892,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i32(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -2903,7 +2903,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2927,7 +2927,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(,,,,,, i32*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(,,,,,, i32*, , , i32, i32) define @test_vluxseg6_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -2938,7 +2938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2962,7 +2962,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i8(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -2973,7 +2973,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2998,7 +2998,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i32(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -3009,7 +3009,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3034,7 +3034,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(,,,,,,, i32*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(,,,,,,, i32*, , , i32, i32) define @test_vluxseg7_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -3045,7 +3045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3070,7 +3070,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i8(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv1i32_nxv1i8(i32* %base, %index, i32 %vl) { @@ -3081,7 +3081,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3107,7 +3107,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i32(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv1i32_nxv1i32(i32* %base, %index, i32 %vl) { @@ -3118,7 +3118,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3144,7 +3144,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(i32*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(,,,,,,,, i32*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(,,,,,,,, i32*, , , i32, i32) define @test_vluxseg8_nxv1i32_nxv1i16(i32* %base, %index, i32 %vl) { @@ -3155,7 +3155,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3181,7 +3181,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i16(,, i16*, , , i32, i32) define @test_vluxseg2_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3192,7 +3192,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3210,7 +3210,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i8(,, i16*, , , i32, i32) define @test_vluxseg2_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3221,7 +3221,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3239,7 +3239,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i32(,, i16*, , , i32, i32) define @test_vluxseg2_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3250,7 +3250,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3268,7 +3268,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i16(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3279,7 +3279,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3299,7 +3299,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i8(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3310,7 +3310,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3330,7 +3330,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i32(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3341,7 +3341,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3360,7 +3360,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i16(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv8i16_nxv8i16(i16* %base, %index, i32 %vl) { @@ -3371,7 +3371,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3393,7 +3393,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i8(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv8i16_nxv8i8(i16* %base, %index, i32 %vl) { @@ -3404,7 +3404,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3426,7 +3426,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i32(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv8i16_nxv8i32(i16* %base, %index, i32 %vl) { @@ -3437,7 +3437,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3458,7 +3458,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3469,7 +3469,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3487,7 +3487,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3498,7 +3498,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3516,7 +3516,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i32(,, i8*, , , i32, i32) define @test_vluxseg2_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3527,7 +3527,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3545,7 +3545,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i16(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3556,7 +3556,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3575,7 +3575,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i8(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3586,7 +3586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3606,7 +3606,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i32(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3617,7 +3617,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3636,7 +3636,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i16(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3647,7 +3647,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3668,7 +3668,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i8(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3679,7 +3679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3701,7 +3701,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i32(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3712,7 +3712,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3732,7 +3732,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i16(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3743,7 +3743,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3766,7 +3766,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i8(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3777,7 +3777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3800,7 +3800,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i32(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3811,7 +3811,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3832,7 +3832,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i16(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3843,7 +3843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3867,7 +3867,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i8(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3878,7 +3878,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3902,7 +3902,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i32(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -3913,7 +3913,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3936,7 +3936,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i16(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -3947,7 +3947,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3972,7 +3972,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i8(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -3983,7 +3983,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4008,7 +4008,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i32(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -4019,7 +4019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4044,7 +4044,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i16(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv8i8_nxv8i16(i8* %base, %index, i32 %vl) { @@ -4055,7 +4055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4081,7 +4081,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i8(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv8i8_nxv8i8(i8* %base, %index, i32 %vl) { @@ -4092,7 +4092,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4118,7 +4118,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i32(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv8i8_nxv8i32(i8* %base, %index, i32 %vl) { @@ -4129,7 +4129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4155,7 +4155,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i16(,, i32*, , , i32, i32) define @test_vluxseg2_nxv8i32_nxv8i16(i32* %base, %index, i32 %vl) { @@ -4166,7 +4166,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4184,7 +4184,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i8(,, i32*, , , i32, i32) define @test_vluxseg2_nxv8i32_nxv8i8(i32* %base, %index, i32 %vl) { @@ -4195,7 +4195,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4213,7 +4213,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i32(,, i32*, , , i32, i32) define @test_vluxseg2_nxv8i32_nxv8i32(i32* %base, %index, i32 %vl) { @@ -4224,7 +4224,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4242,7 +4242,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4253,7 +4253,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4271,7 +4271,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4282,7 +4282,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4300,7 +4300,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i32(,, i8*, , , i32, i32) define @test_vluxseg2_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4311,7 +4311,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4329,7 +4329,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i16(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4340,7 +4340,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4360,7 +4360,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i8(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4371,7 +4371,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4391,7 +4391,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i32(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4402,7 +4402,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4421,7 +4421,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i16(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4432,7 +4432,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4454,7 +4454,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i8(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4465,7 +4465,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4487,7 +4487,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i32(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4498,7 +4498,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4519,7 +4519,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i16(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4530,7 +4530,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4553,7 +4553,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i8(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4564,7 +4564,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4587,7 +4587,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i32(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4598,7 +4598,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4621,7 +4621,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i16(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4632,7 +4632,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4656,7 +4656,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i8(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4667,7 +4667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4691,7 +4691,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i32(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4702,7 +4702,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4726,7 +4726,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i16(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4737,7 +4737,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4762,7 +4762,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i8(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4773,7 +4773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4798,7 +4798,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i32(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4809,7 +4809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4834,7 +4834,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i16(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv4i8_nxv4i16(i8* %base, %index, i32 %vl) { @@ -4845,7 +4845,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4871,7 +4871,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i8(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv4i8_nxv4i8(i8* %base, %index, i32 %vl) { @@ -4882,7 +4882,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4908,7 +4908,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i32(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv4i8_nxv4i32(i8* %base, %index, i32 %vl) { @@ -4919,7 +4919,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4945,7 +4945,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i8(,, i16*, , , i32, i32) define @test_vluxseg2_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -4956,7 +4956,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4974,7 +4974,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i32(,, i16*, , , i32, i32) define @test_vluxseg2_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -4985,7 +4985,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5003,7 +5003,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i16(,, i16*, , , i32, i32) define @test_vluxseg2_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5014,7 +5014,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5032,7 +5032,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i8(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5043,7 +5043,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5063,7 +5063,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i32(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5074,7 +5074,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5094,7 +5094,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i16(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5105,7 +5105,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5125,7 +5125,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i8(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5136,7 +5136,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5158,7 +5158,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i32(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5169,7 +5169,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5191,7 +5191,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i16(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5202,7 +5202,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5224,7 +5224,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i8(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5235,7 +5235,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5258,7 +5258,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i32(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5269,7 +5269,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5292,7 +5292,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i16(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5303,7 +5303,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5326,7 +5326,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i8(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5337,7 +5337,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5361,7 +5361,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i32(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5372,7 +5372,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5396,7 +5396,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i16(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5407,7 +5407,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5431,7 +5431,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i8(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5442,7 +5442,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5467,7 +5467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i32(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5478,7 +5478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5503,7 +5503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i16(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5514,7 +5514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5539,7 +5539,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i8(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv1i16_nxv1i8(i16* %base, %index, i32 %vl) { @@ -5550,7 +5550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5576,7 +5576,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i32(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv1i16_nxv1i32(i16* %base, %index, i32 %vl) { @@ -5587,7 +5587,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5613,7 +5613,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i16(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv1i16_nxv1i16(i16* %base, %index, i32 %vl) { @@ -5624,7 +5624,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5650,7 +5650,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv32i8.nxv32i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv32i8_nxv32i16(i8* %base, %index, i32 %vl) { @@ -5661,7 +5661,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5679,7 +5679,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv32i8.nxv32i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv32i8_nxv32i8(i8* %base, %index, i32 %vl) { @@ -5690,7 +5690,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5708,7 +5708,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i32(,, i8*, , , i32, i32) define @test_vluxseg2_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5719,7 +5719,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5737,7 +5737,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i8(,, i8*, , , i32, i32) define @test_vluxseg2_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5748,7 +5748,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5766,7 +5766,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(i8*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(,, i8*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i16(,, i8*, , , i32, i32) define @test_vluxseg2_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5777,7 +5777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16( undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5795,7 +5795,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i32(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5806,7 +5806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5826,7 +5826,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i8(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5837,7 +5837,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5857,7 +5857,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(i8*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(,,, i8*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i16(,,, i8*, , , i32, i32) define @test_vluxseg3_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5868,7 +5868,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16( undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5888,7 +5888,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i32(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5899,7 +5899,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5921,7 +5921,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i8(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -5932,7 +5932,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5954,7 +5954,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(,,,, i8*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i16(,,,, i8*, , , i32, i32) define @test_vluxseg4_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -5965,7 +5965,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16( undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5987,7 +5987,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i32(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -5998,7 +5998,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6021,7 +6021,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i8(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6032,7 +6032,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6055,7 +6055,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(,,,,, i8*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i16(,,,,, i8*, , , i32, i32) define @test_vluxseg5_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6066,7 +6066,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6089,7 +6089,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i32(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6100,7 +6100,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6124,7 +6124,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i8(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6135,7 +6135,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6159,7 +6159,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(,,,,,, i8*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i16(,,,,,, i8*, , , i32, i32) define @test_vluxseg6_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6170,7 +6170,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6194,7 +6194,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i32(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6205,7 +6205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6230,7 +6230,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i8(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6241,7 +6241,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6266,7 +6266,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(,,,,,,, i8*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i16(,,,,,,, i8*, , , i32, i32) define @test_vluxseg7_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6277,7 +6277,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6302,7 +6302,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i32(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv2i8_nxv2i32(i8* %base, %index, i32 %vl) { @@ -6313,7 +6313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6339,7 +6339,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i8(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv2i8_nxv2i8(i8* %base, %index, i32 %vl) { @@ -6350,7 +6350,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6376,7 +6376,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(i8*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(,,,,,,,, i8*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i16(,,,,,,,, i8*, , , i32, i32) define @test_vluxseg8_nxv2i8_nxv2i16(i8* %base, %index, i32 %vl) { @@ -6387,7 +6387,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(i8* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6413,7 +6413,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i32(,, i16*, , , i32, i32) define @test_vluxseg2_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6424,7 +6424,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6442,7 +6442,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i8(,, i16*, , , i32, i32) define @test_vluxseg2_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6453,7 +6453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6471,7 +6471,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(i16*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(,, i16*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i16(,, i16*, , , i32, i32) define @test_vluxseg2_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6482,7 +6482,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16( undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6500,7 +6500,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i32(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6511,7 +6511,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6531,7 +6531,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i8(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6542,7 +6542,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6562,7 +6562,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(i16*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(,,, i16*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i16(,,, i16*, , , i32, i32) define @test_vluxseg3_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6573,7 +6573,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16( undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6593,7 +6593,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i32(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6604,7 +6604,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6626,7 +6626,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i8(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6637,7 +6637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6659,7 +6659,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(,,,, i16*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i16(,,,, i16*, , , i32, i32) define @test_vluxseg4_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6670,7 +6670,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16( undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6692,7 +6692,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i32(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6703,7 +6703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6726,7 +6726,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i8(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6737,7 +6737,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6760,7 +6760,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(,,,,, i16*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i16(,,,,, i16*, , , i32, i32) define @test_vluxseg5_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6771,7 +6771,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6794,7 +6794,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i32(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6805,7 +6805,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6829,7 +6829,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i8(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6840,7 +6840,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6864,7 +6864,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(,,,,,, i16*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i16(,,,,,, i16*, , , i32, i32) define @test_vluxseg6_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6875,7 +6875,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6899,7 +6899,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i32(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -6910,7 +6910,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6935,7 +6935,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i8(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -6946,7 +6946,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6971,7 +6971,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(,,,,,,, i16*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i16(,,,,,,, i16*, , , i32, i32) define @test_vluxseg7_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -6982,7 +6982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7007,7 +7007,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i32(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv2i16_nxv2i32(i16* %base, %index, i32 %vl) { @@ -7018,7 +7018,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7044,7 +7044,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i8(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv2i16_nxv2i8(i16* %base, %index, i32 %vl) { @@ -7055,7 +7055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7081,7 +7081,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(i16*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(,,,,,,,, i16*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i16(,,,,,,,, i16*, , , i32, i32) define @test_vluxseg8_nxv2i16_nxv2i16(i16* %base, %index, i32 %vl) { @@ -7092,7 +7092,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(i16* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7118,7 +7118,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i16(,, i32*, , , i32, i32) define @test_vluxseg2_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7129,7 +7129,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7147,7 +7147,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i8(,, i32*, , , i32, i32) define @test_vluxseg2_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7158,7 +7158,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7176,7 +7176,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(,, i32*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i32(,, i32*, , , i32, i32) define @test_vluxseg2_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7187,7 +7187,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32( undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7205,7 +7205,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i16(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7216,7 +7216,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7236,7 +7236,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i8(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7247,7 +7247,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7267,7 +7267,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(,,, i32*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i32(,,, i32*, , , i32, i32) define @test_vluxseg3_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7278,7 +7278,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32( undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7298,7 +7298,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i16(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv4i32_nxv4i16(i32* %base, %index, i32 %vl) { @@ -7309,7 +7309,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7331,7 +7331,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i8(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv4i32_nxv4i8(i32* %base, %index, i32 %vl) { @@ -7342,7 +7342,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7364,7 +7364,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(,,,, i32*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i32(,,,, i32*, , , i32, i32) define @test_vluxseg4_nxv4i32_nxv4i32(i32* %base, %index, i32 %vl) { @@ -7375,7 +7375,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32( undef, undef, undef, undef, i32* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7397,7 +7397,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i16(,, half*, , , i32, i32) define @test_vluxseg2_nxv16f16_nxv16i16(half* %base, %index, i32 %vl) { @@ -7408,7 +7408,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7426,7 +7426,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i8(,, half*, , , i32, i32) define @test_vluxseg2_nxv16f16_nxv16i8(half* %base, %index, i32 %vl) { @@ -7437,7 +7437,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7455,7 +7455,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i32(,, half*, , , i32, i32) define @test_vluxseg2_nxv16f16_nxv16i32(half* %base, %index, i32 %vl) { @@ -7466,7 +7466,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7484,7 +7484,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i16(,, double*, , , i32, i32) define @test_vluxseg2_nxv4f64_nxv4i16(double* %base, %index, i32 %vl) { @@ -7495,7 +7495,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7513,7 +7513,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i8(,, double*, , , i32, i32) define @test_vluxseg2_nxv4f64_nxv4i8(double* %base, %index, i32 %vl) { @@ -7524,7 +7524,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7542,7 +7542,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i32(,, double*, , , i32, i32) define @test_vluxseg2_nxv4f64_nxv4i32(double* %base, %index, i32 %vl) { @@ -7553,7 +7553,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7571,7 +7571,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i8(,, double*, , , i32, i32) define @test_vluxseg2_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7582,7 +7582,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7600,7 +7600,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i32(,, double*, , , i32, i32) define @test_vluxseg2_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7611,7 +7611,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7629,7 +7629,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i16(,, double*, , , i32, i32) define @test_vluxseg2_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7640,7 +7640,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7658,7 +7658,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i8(,,, double*, , , i32, i32) define @test_vluxseg3_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7669,7 +7669,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7689,7 +7689,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i32(,,, double*, , , i32, i32) define @test_vluxseg3_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7700,7 +7700,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7720,7 +7720,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i16(,,, double*, , , i32, i32) define @test_vluxseg3_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7731,7 +7731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7751,7 +7751,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i8(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7762,7 +7762,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7784,7 +7784,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i32(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7795,7 +7795,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7817,7 +7817,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i16(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7828,7 +7828,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7850,7 +7850,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i8(,,,,, double*, , , i32, i32) define @test_vluxseg5_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7861,7 +7861,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7884,7 +7884,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i32(,,,,, double*, , , i32, i32) define @test_vluxseg5_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7895,7 +7895,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7918,7 +7918,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(,,,,, double*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i16(,,,,, double*, , , i32, i32) define @test_vluxseg5_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -7929,7 +7929,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7952,7 +7952,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i8(,,,,,, double*, , , i32, i32) define @test_vluxseg6_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -7963,7 +7963,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7987,7 +7987,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i32(,,,,,, double*, , , i32, i32) define @test_vluxseg6_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -7998,7 +7998,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8022,7 +8022,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(,,,,,, double*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i16(,,,,,, double*, , , i32, i32) define @test_vluxseg6_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8033,7 +8033,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8057,7 +8057,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i8(,,,,,,, double*, , , i32, i32) define @test_vluxseg7_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -8068,7 +8068,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8093,7 +8093,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i32(,,,,,,, double*, , , i32, i32) define @test_vluxseg7_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -8104,7 +8104,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8129,7 +8129,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(,,,,,,, double*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i16(,,,,,,, double*, , , i32, i32) define @test_vluxseg7_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8140,7 +8140,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8165,7 +8165,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i8(,,,,,,,, double*, , , i32, i32) define @test_vluxseg8_nxv1f64_nxv1i8(double* %base, %index, i32 %vl) { @@ -8176,7 +8176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8202,7 +8202,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i32(,,,,,,,, double*, , , i32, i32) define @test_vluxseg8_nxv1f64_nxv1i32(double* %base, %index, i32 %vl) { @@ -8213,7 +8213,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8239,7 +8239,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(double*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(,,,,,,,, double*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i16(,,,,,,,, double*, , , i32, i32) define @test_vluxseg8_nxv1f64_nxv1i16(double* %base, %index, i32 %vl) { @@ -8250,7 +8250,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8276,7 +8276,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i32(,, float*, , , i32, i32) define @test_vluxseg2_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8287,7 +8287,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8305,7 +8305,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i8(,, float*, , , i32, i32) define @test_vluxseg2_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8316,7 +8316,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8334,7 +8334,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i16(,, float*, , , i32, i32) define @test_vluxseg2_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8345,7 +8345,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8363,7 +8363,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i32(,,, float*, , , i32, i32) define @test_vluxseg3_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8374,7 +8374,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8394,7 +8394,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i8(,,, float*, , , i32, i32) define @test_vluxseg3_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8405,7 +8405,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8425,7 +8425,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i16(,,, float*, , , i32, i32) define @test_vluxseg3_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8436,7 +8436,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8456,7 +8456,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i32(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8467,7 +8467,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8489,7 +8489,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i8(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8500,7 +8500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8522,7 +8522,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i16(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8533,7 +8533,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8555,7 +8555,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i32(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8566,7 +8566,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8589,7 +8589,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i8(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8600,7 +8600,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8623,7 +8623,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i16(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8634,7 +8634,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8657,7 +8657,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i32(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8668,7 +8668,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8692,7 +8692,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i8(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8703,7 +8703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8727,7 +8727,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i16(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8738,7 +8738,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8762,7 +8762,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i32(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8773,7 +8773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8798,7 +8798,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i8(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8809,7 +8809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8834,7 +8834,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i16(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8845,7 +8845,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8870,7 +8870,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i32(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv2f32_nxv2i32(float* %base, %index, i32 %vl) { @@ -8881,7 +8881,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8907,7 +8907,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i8(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv2f32_nxv2i8(float* %base, %index, i32 %vl) { @@ -8918,7 +8918,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8944,7 +8944,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i16(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv2f32_nxv2i16(float* %base, %index, i32 %vl) { @@ -8955,7 +8955,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8981,7 +8981,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i8(,, half*, , , i32, i32) define @test_vluxseg2_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -8992,7 +8992,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9010,7 +9010,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i32(,, half*, , , i32, i32) define @test_vluxseg2_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9021,7 +9021,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9039,7 +9039,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i16(,, half*, , , i32, i32) define @test_vluxseg2_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9050,7 +9050,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9068,7 +9068,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i8(,,, half*, , , i32, i32) define @test_vluxseg3_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9079,7 +9079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9099,7 +9099,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i32(,,, half*, , , i32, i32) define @test_vluxseg3_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9110,7 +9110,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9130,7 +9130,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i16(,,, half*, , , i32, i32) define @test_vluxseg3_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9141,7 +9141,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9161,7 +9161,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i8(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9172,7 +9172,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9194,7 +9194,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i32(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9205,7 +9205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9227,7 +9227,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i16(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9238,7 +9238,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9260,7 +9260,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i8(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9271,7 +9271,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9294,7 +9294,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i32(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9305,7 +9305,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9328,7 +9328,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i16(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9339,7 +9339,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9362,7 +9362,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i8(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9373,7 +9373,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9397,7 +9397,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i32(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9408,7 +9408,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9432,7 +9432,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i16(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9443,7 +9443,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9467,7 +9467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i8(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9478,7 +9478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9503,7 +9503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i32(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9514,7 +9514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9539,7 +9539,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i16(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9550,7 +9550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9575,7 +9575,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i8(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv1f16_nxv1i8(half* %base, %index, i32 %vl) { @@ -9586,7 +9586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9612,7 +9612,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i32(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv1f16_nxv1i32(half* %base, %index, i32 %vl) { @@ -9623,7 +9623,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9649,7 +9649,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i16(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv1f16_nxv1i16(half* %base, %index, i32 %vl) { @@ -9660,7 +9660,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9686,7 +9686,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i8(,, float*, , , i32, i32) define @test_vluxseg2_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9697,7 +9697,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9715,7 +9715,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i32(,, float*, , , i32, i32) define @test_vluxseg2_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9726,7 +9726,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9744,7 +9744,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i16(,, float*, , , i32, i32) define @test_vluxseg2_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9755,7 +9755,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9773,7 +9773,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i8(,,, float*, , , i32, i32) define @test_vluxseg3_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9784,7 +9784,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9804,7 +9804,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i32(,,, float*, , , i32, i32) define @test_vluxseg3_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9815,7 +9815,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9835,7 +9835,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i16(,,, float*, , , i32, i32) define @test_vluxseg3_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9846,7 +9846,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9866,7 +9866,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i8(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9877,7 +9877,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9899,7 +9899,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i32(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -9910,7 +9910,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9932,7 +9932,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i16(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -9943,7 +9943,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9965,7 +9965,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i8(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -9976,7 +9976,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9999,7 +9999,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i32(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10010,7 +10010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10033,7 +10033,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(,,,,, float*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i16(,,,,, float*, , , i32, i32) define @test_vluxseg5_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10044,7 +10044,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10067,7 +10067,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i8(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10078,7 +10078,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10102,7 +10102,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i32(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10113,7 +10113,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10137,7 +10137,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(,,,,,, float*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i16(,,,,,, float*, , , i32, i32) define @test_vluxseg6_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10148,7 +10148,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10172,7 +10172,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i8(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10183,7 +10183,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10208,7 +10208,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i32(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10219,7 +10219,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10244,7 +10244,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(,,,,,,, float*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i16(,,,,,,, float*, , , i32, i32) define @test_vluxseg7_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10255,7 +10255,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10280,7 +10280,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i8(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv1f32_nxv1i8(float* %base, %index, i32 %vl) { @@ -10291,7 +10291,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10317,7 +10317,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i32(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv1f32_nxv1i32(float* %base, %index, i32 %vl) { @@ -10328,7 +10328,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10354,7 +10354,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(float*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(,,,,,,,, float*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i16(,,,,,,,, float*, , , i32, i32) define @test_vluxseg8_nxv1f32_nxv1i16(float* %base, %index, i32 %vl) { @@ -10365,7 +10365,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10391,7 +10391,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i16(,, half*, , , i32, i32) define @test_vluxseg2_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10402,7 +10402,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10420,7 +10420,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i8(,, half*, , , i32, i32) define @test_vluxseg2_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10431,7 +10431,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10449,7 +10449,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i32(,, half*, , , i32, i32) define @test_vluxseg2_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10460,7 +10460,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10478,7 +10478,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i16(,,, half*, , , i32, i32) define @test_vluxseg3_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10489,7 +10489,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10509,7 +10509,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i8(,,, half*, , , i32, i32) define @test_vluxseg3_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10520,7 +10520,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10540,7 +10540,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i32(,,, half*, , , i32, i32) define @test_vluxseg3_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10551,7 +10551,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10570,7 +10570,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i16(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv8f16_nxv8i16(half* %base, %index, i32 %vl) { @@ -10581,7 +10581,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10603,7 +10603,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i8(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv8f16_nxv8i8(half* %base, %index, i32 %vl) { @@ -10614,7 +10614,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10636,7 +10636,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i32(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv8f16_nxv8i32(half* %base, %index, i32 %vl) { @@ -10647,7 +10647,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10668,7 +10668,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i16(,, float*, , , i32, i32) define @test_vluxseg2_nxv8f32_nxv8i16(float* %base, %index, i32 %vl) { @@ -10679,7 +10679,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10697,7 +10697,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i8(,, float*, , , i32, i32) define @test_vluxseg2_nxv8f32_nxv8i8(float* %base, %index, i32 %vl) { @@ -10708,7 +10708,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10726,7 +10726,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i32(,, float*, , , i32, i32) define @test_vluxseg2_nxv8f32_nxv8i32(float* %base, %index, i32 %vl) { @@ -10737,7 +10737,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10755,7 +10755,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i32(,, double*, , , i32, i32) define @test_vluxseg2_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10766,7 +10766,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10784,7 +10784,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i8(,, double*, , , i32, i32) define @test_vluxseg2_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10795,7 +10795,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10813,7 +10813,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(double*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(,, double*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i16(,, double*, , , i32, i32) define @test_vluxseg2_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -10824,7 +10824,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16( undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10842,7 +10842,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i32(,,, double*, , , i32, i32) define @test_vluxseg3_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10853,7 +10853,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10873,7 +10873,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i8(,,, double*, , , i32, i32) define @test_vluxseg3_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10884,7 +10884,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10904,7 +10904,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(double*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(,,, double*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i16(,,, double*, , , i32, i32) define @test_vluxseg3_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -10915,7 +10915,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16( undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10935,7 +10935,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i32(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv2f64_nxv2i32(double* %base, %index, i32 %vl) { @@ -10946,7 +10946,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10968,7 +10968,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i8(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv2f64_nxv2i8(double* %base, %index, i32 %vl) { @@ -10979,7 +10979,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11001,7 +11001,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(double*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(,,,, double*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i16(,,,, double*, , , i32, i32) define @test_vluxseg4_nxv2f64_nxv2i16(double* %base, %index, i32 %vl) { @@ -11012,7 +11012,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(double* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16( undef, undef, undef, undef, double* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11034,7 +11034,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i16(,, half*, , , i32, i32) define @test_vluxseg2_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11045,7 +11045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11063,7 +11063,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i8(,, half*, , , i32, i32) define @test_vluxseg2_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11074,7 +11074,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11092,7 +11092,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i32(,, half*, , , i32, i32) define @test_vluxseg2_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11103,7 +11103,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11121,7 +11121,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i16(,,, half*, , , i32, i32) define @test_vluxseg3_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11132,7 +11132,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11152,7 +11152,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i8(,,, half*, , , i32, i32) define @test_vluxseg3_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11163,7 +11163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11183,7 +11183,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i32(,,, half*, , , i32, i32) define @test_vluxseg3_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11194,7 +11194,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11213,7 +11213,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i16(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11224,7 +11224,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11246,7 +11246,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i8(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11257,7 +11257,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11279,7 +11279,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i32(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11290,7 +11290,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11311,7 +11311,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i16(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11322,7 +11322,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11345,7 +11345,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i8(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11356,7 +11356,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11379,7 +11379,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i32(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11390,7 +11390,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11413,7 +11413,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i16(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11424,7 +11424,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11448,7 +11448,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i8(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11459,7 +11459,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11483,7 +11483,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i32(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11494,7 +11494,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11518,7 +11518,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i16(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11529,7 +11529,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11554,7 +11554,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i8(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11565,7 +11565,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11590,7 +11590,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i32(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11601,7 +11601,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -11626,7 +11626,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i16(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv4f16_nxv4i16(half* %base, %index, i32 %vl) { @@ -11637,7 +11637,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11663,7 +11663,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i8(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv4f16_nxv4i8(half* %base, %index, i32 %vl) { @@ -11674,7 +11674,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11700,7 +11700,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i32(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv4f16_nxv4i32(half* %base, %index, i32 %vl) { @@ -11711,7 +11711,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -11737,7 +11737,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i32(,, half*, , , i32, i32) define @test_vluxseg2_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11748,7 +11748,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11766,7 +11766,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i8(,, half*, , , i32, i32) define @test_vluxseg2_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11777,7 +11777,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11795,7 +11795,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(half*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(,, half*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i16(,, half*, , , i32, i32) define @test_vluxseg2_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11806,7 +11806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16( undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11824,7 +11824,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i32(,,, half*, , , i32, i32) define @test_vluxseg3_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11835,7 +11835,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11855,7 +11855,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i8(,,, half*, , , i32, i32) define @test_vluxseg3_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11866,7 +11866,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11886,7 +11886,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(half*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(,,, half*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i16(,,, half*, , , i32, i32) define @test_vluxseg3_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11897,7 +11897,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16( undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11917,7 +11917,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i32(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -11928,7 +11928,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11950,7 +11950,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i8(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -11961,7 +11961,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11983,7 +11983,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(half*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(,,,, half*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i16(,,,, half*, , , i32, i32) define @test_vluxseg4_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -11994,7 +11994,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16( undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12016,7 +12016,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i32(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12027,7 +12027,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12050,7 +12050,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i8(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12061,7 +12061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12084,7 +12084,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(,,,,, half*, , i32) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i16(,,,,, half*, , , i32, i32) define @test_vluxseg5_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12095,7 +12095,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12118,7 +12118,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i32(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12129,7 +12129,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12153,7 +12153,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i8(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12164,7 +12164,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12188,7 +12188,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(,,,,,, half*, , i32) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i16(,,,,,, half*, , , i32, i32) define @test_vluxseg6_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12199,7 +12199,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12223,7 +12223,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i32(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12234,7 +12234,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12259,7 +12259,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i8(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12270,7 +12270,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12295,7 +12295,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(,,,,,,, half*, , i32) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i16(,,,,,,, half*, , , i32, i32) define @test_vluxseg7_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12306,7 +12306,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12331,7 +12331,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i32(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv2f16_nxv2i32(half* %base, %index, i32 %vl) { @@ -12342,7 +12342,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12368,7 +12368,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i8(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv2f16_nxv2i8(half* %base, %index, i32 %vl) { @@ -12379,7 +12379,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12405,7 +12405,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(half*, , i32) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(,,,,,,,, half*, , i32) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i16(,,,,,,,, half*, , , i32, i32) define @test_vluxseg8_nxv2f16_nxv2i16(half* %base, %index, i32 %vl) { @@ -12416,7 +12416,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(half* %base, %index, i32 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i32 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12442,7 +12442,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i16(,, float*, , , i32, i32) define @test_vluxseg2_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12453,7 +12453,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12471,7 +12471,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i8(,, float*, , , i32, i32) define @test_vluxseg2_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12482,7 +12482,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12500,7 +12500,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(float*, , i32) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(,, float*, , i32) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i32(,, float*, , , i32, i32) define @test_vluxseg2_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12511,7 +12511,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32( undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12529,7 +12529,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i16(,,, float*, , , i32, i32) define @test_vluxseg3_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12540,7 +12540,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12560,7 +12560,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i8(,,, float*, , , i32, i32) define @test_vluxseg3_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12571,7 +12571,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12591,7 +12591,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(float*, , i32) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(,,, float*, , i32) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i32(,,, float*, , , i32, i32) define @test_vluxseg3_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12602,7 +12602,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32( undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12622,7 +12622,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i16(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv4f32_nxv4i16(float* %base, %index, i32 %vl) { @@ -12633,7 +12633,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12655,7 +12655,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i8(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv4f32_nxv4i8(float* %base, %index, i32 %vl) { @@ -12666,7 +12666,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12688,7 +12688,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(float*, , i32) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(,,,, float*, , i32) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i32(,,,, float*, , , i32, i32) define @test_vluxseg4_nxv4f32_nxv4i32(float* %base, %index, i32 %vl) { @@ -12699,7 +12699,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(float* %base, %index, i32 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32( undef, undef, undef, undef, float* %base, %index, i32 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i64, i64) define @test_vluxseg2_nxv16i16_nxv16i16(i16* %base, %index, i64 %vl) { @@ -13,7 +13,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -31,7 +31,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i8(,, i16*, , , i64, i64) define @test_vluxseg2_nxv16i16_nxv16i8(i16* %base, %index, i64 %vl) { @@ -42,7 +42,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -60,7 +60,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i32(,, i16*, , , i64, i64) define @test_vluxseg2_nxv16i16_nxv16i32(i16* %base, %index, i64 %vl) { @@ -71,7 +71,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -89,7 +89,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i32(,, i32*, , , i64, i64) define @test_vluxseg2_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -100,7 +100,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -118,7 +118,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i8(,, i32*, , , i64, i64) define @test_vluxseg2_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -129,7 +129,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -147,7 +147,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i64(,, i32*, , , i64, i64) define @test_vluxseg2_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -158,7 +158,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -176,7 +176,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i16(,, i32*, , , i64, i64) define @test_vluxseg2_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -187,7 +187,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -205,7 +205,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i32(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -216,7 +216,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -236,7 +236,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i8(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -247,7 +247,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -267,7 +267,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i64(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -278,7 +278,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -297,7 +297,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i16(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -308,7 +308,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -328,7 +328,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i32(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv4i32_nxv4i32(i32* %base, %index, i64 %vl) { @@ -339,7 +339,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -361,7 +361,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i8(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv4i32_nxv4i8(i32* %base, %index, i64 %vl) { @@ -372,7 +372,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -394,7 +394,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i64(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv4i32_nxv4i64(i32* %base, %index, i64 %vl) { @@ -405,7 +405,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -426,7 +426,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i16(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv4i32_nxv4i16(i32* %base, %index, i64 %vl) { @@ -437,7 +437,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -459,7 +459,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -470,7 +470,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -488,7 +488,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -499,7 +499,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -517,7 +517,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i32(,, i8*, , , i64, i64) define @test_vluxseg2_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -528,7 +528,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -546,7 +546,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i16(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -557,7 +557,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -576,7 +576,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i8(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -587,7 +587,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -607,7 +607,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i32(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -618,7 +618,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -637,7 +637,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i16(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv16i8_nxv16i16(i8* %base, %index, i64 %vl) { @@ -648,7 +648,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -669,7 +669,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i8(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv16i8_nxv16i8(i8* %base, %index, i64 %vl) { @@ -680,7 +680,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -702,7 +702,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i32(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv16i8_nxv16i32(i8* %base, %index, i64 %vl) { @@ -713,7 +713,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -733,7 +733,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i64(,, i64*, , , i64, i64) define @test_vluxseg2_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -744,7 +744,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -762,7 +762,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i32(,, i64*, , , i64, i64) define @test_vluxseg2_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -773,7 +773,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -791,7 +791,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i16(,, i64*, , , i64, i64) define @test_vluxseg2_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -802,7 +802,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -820,7 +820,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i8(,, i64*, , , i64, i64) define @test_vluxseg2_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -831,7 +831,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -849,7 +849,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i64(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -860,7 +860,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -880,7 +880,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i32(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -891,7 +891,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -911,7 +911,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i16(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -922,7 +922,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -942,7 +942,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i8(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -953,7 +953,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -973,7 +973,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i64(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -984,7 +984,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1006,7 +1006,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i32(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1017,7 +1017,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1039,7 +1039,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i16(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1050,7 +1050,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1072,7 +1072,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i8(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1083,7 +1083,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1105,7 +1105,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i64(,,,,, i64*, , , i64, i64) define @test_vluxseg5_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1116,7 +1116,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1139,7 +1139,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i32(,,,,, i64*, , , i64, i64) define @test_vluxseg5_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1150,7 +1150,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1173,7 +1173,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i16(,,,,, i64*, , , i64, i64) define @test_vluxseg5_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1184,7 +1184,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1207,7 +1207,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8(,,,,, i64*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i8(,,,,, i64*, , , i64, i64) define @test_vluxseg5_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1218,7 +1218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -1241,7 +1241,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i64(,,,,,, i64*, , , i64, i64) define @test_vluxseg6_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1252,7 +1252,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1276,7 +1276,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i32(,,,,,, i64*, , , i64, i64) define @test_vluxseg6_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1287,7 +1287,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1311,7 +1311,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i16(,,,,,, i64*, , , i64, i64) define @test_vluxseg6_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1322,7 +1322,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1346,7 +1346,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8(,,,,,, i64*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i8(,,,,,, i64*, , , i64, i64) define @test_vluxseg6_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1357,7 +1357,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -1381,7 +1381,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i64(,,,,,,, i64*, , , i64, i64) define @test_vluxseg7_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1392,7 +1392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1417,7 +1417,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i32(,,,,,,, i64*, , , i64, i64) define @test_vluxseg7_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1428,7 +1428,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1453,7 +1453,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i16(,,,,,,, i64*, , , i64, i64) define @test_vluxseg7_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1464,7 +1464,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1489,7 +1489,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8(,,,,,,, i64*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i8(,,,,,,, i64*, , , i64, i64) define @test_vluxseg7_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1500,7 +1500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -1525,7 +1525,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i64(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i64(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i64.nxv1i64(,,,,,,,, i64*, , , i64, i64) define @test_vluxseg8_nxv1i64_nxv1i64(i64* %base, %index, i64 %vl) { @@ -1536,7 +1536,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1562,7 +1562,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i32(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i32(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i64.nxv1i32(,,,,,,,, i64*, , , i64, i64) define @test_vluxseg8_nxv1i64_nxv1i32(i64* %base, %index, i64 %vl) { @@ -1573,7 +1573,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1599,7 +1599,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i16(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i16(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i64.nxv1i16(,,,,,,,, i64*, , , i64, i64) define @test_vluxseg8_nxv1i64_nxv1i16(i64* %base, %index, i64 %vl) { @@ -1610,7 +1610,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1636,7 +1636,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i8(i64*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i8(,,,,,,,, i64*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i64.nxv1i8(,,,,,,,, i64*, , , i64, i64) define @test_vluxseg8_nxv1i64_nxv1i8(i64* %base, %index, i64 %vl) { @@ -1647,7 +1647,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -1673,7 +1673,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i64(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i64(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i64(,, i32*, , , i64, i64) define @test_vluxseg2_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1684,7 +1684,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1702,7 +1702,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32(,, i32*, , , i64, i64) define @test_vluxseg2_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1713,7 +1713,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1731,7 +1731,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i16(,, i32*, , , i64, i64) define @test_vluxseg2_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1742,7 +1742,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1760,7 +1760,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i8(,, i32*, , , i64, i64) define @test_vluxseg2_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -1771,7 +1771,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i32.nxv1i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -1789,7 +1789,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i64(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i64(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1800,7 +1800,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1820,7 +1820,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i32(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1831,7 +1831,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1851,7 +1851,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i16(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1862,7 +1862,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1882,7 +1882,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i32.nxv1i8(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -1893,7 +1893,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i32.nxv1i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -1913,7 +1913,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i64(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -1924,7 +1924,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1946,7 +1946,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i32(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -1957,7 +1957,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -1979,7 +1979,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i16(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -1990,7 +1990,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2012,7 +2012,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i32.nxv1i8(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2023,7 +2023,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i32.nxv1i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2045,7 +2045,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i64(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i64(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2056,7 +2056,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2079,7 +2079,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i32(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2090,7 +2090,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2113,7 +2113,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i16(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2124,7 +2124,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2147,7 +2147,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i32.nxv1i8(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2158,7 +2158,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -2181,7 +2181,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i64(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i64(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2192,7 +2192,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2216,7 +2216,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i32(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2227,7 +2227,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2251,7 +2251,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i16(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2262,7 +2262,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2286,7 +2286,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i32.nxv1i8(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2297,7 +2297,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -2321,7 +2321,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i64(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i64(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2332,7 +2332,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2357,7 +2357,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i32(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2368,7 +2368,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2393,7 +2393,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i16(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2404,7 +2404,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2429,7 +2429,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i32.nxv1i8(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2440,7 +2440,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -2465,7 +2465,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i64(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i64(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i64(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv1i32_nxv1i64(i32* %base, %index, i64 %vl) { @@ -2476,7 +2476,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2502,7 +2502,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i32(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv1i32_nxv1i32(i32* %base, %index, i64 %vl) { @@ -2513,7 +2513,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2539,7 +2539,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i16(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv1i32_nxv1i16(i32* %base, %index, i64 %vl) { @@ -2550,7 +2550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2576,7 +2576,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i32.nxv1i8(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv1i32_nxv1i8(i32* %base, %index, i64 %vl) { @@ -2587,7 +2587,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -2613,7 +2613,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i16(,, i16*, , , i64, i64) define @test_vluxseg2_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2624,7 +2624,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2642,7 +2642,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i8(,, i16*, , , i64, i64) define @test_vluxseg2_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2653,7 +2653,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2671,7 +2671,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i64(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i64(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i64(,, i16*, , , i64, i64) define @test_vluxseg2_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2682,7 +2682,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2700,7 +2700,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i16.nxv8i32(,, i16*, , , i64, i64) define @test_vluxseg2_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2711,7 +2711,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i16.nxv8i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -2729,7 +2729,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i16(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2740,7 +2740,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2760,7 +2760,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i8(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2771,7 +2771,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2791,7 +2791,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i64(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i64(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2802,7 +2802,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2821,7 +2821,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i16.nxv8i32(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2832,7 +2832,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i16.nxv8i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -2851,7 +2851,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i16(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv8i16_nxv8i16(i16* %base, %index, i64 %vl) { @@ -2862,7 +2862,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2884,7 +2884,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i8(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv8i16_nxv8i8(i16* %base, %index, i64 %vl) { @@ -2895,7 +2895,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2917,7 +2917,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i64(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i64(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv8i16_nxv8i64(i16* %base, %index, i64 %vl) { @@ -2928,7 +2928,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2948,7 +2948,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i16.nxv8i32(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv8i16_nxv8i32(i16* %base, %index, i64 %vl) { @@ -2959,7 +2959,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i16.nxv8i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -2980,7 +2980,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i32(,, i8*, , , i64, i64) define @test_vluxseg2_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -2991,7 +2991,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3009,7 +3009,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3020,7 +3020,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3038,7 +3038,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i64(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i64(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i64(,, i8*, , , i64, i64) define @test_vluxseg2_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3049,7 +3049,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3067,7 +3067,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i8.nxv4i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3078,7 +3078,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i8.nxv4i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3096,7 +3096,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i32(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3107,7 +3107,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3126,7 +3126,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i8(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3137,7 +3137,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3157,7 +3157,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i64(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i64(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3168,7 +3168,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3187,7 +3187,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i8.nxv4i16(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3198,7 +3198,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i8.nxv4i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -3218,7 +3218,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i32(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3229,7 +3229,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3250,7 +3250,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i8(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3261,7 +3261,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3283,7 +3283,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i64(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3294,7 +3294,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3314,7 +3314,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i8.nxv4i16(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3325,7 +3325,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i8.nxv4i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -3347,7 +3347,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i32(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3358,7 +3358,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3381,7 +3381,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i8(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3392,7 +3392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3415,7 +3415,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i64(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3426,7 +3426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3447,7 +3447,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i8.nxv4i16(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3458,7 +3458,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -3481,7 +3481,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i32(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3492,7 +3492,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3516,7 +3516,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i8(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3527,7 +3527,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3551,7 +3551,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i64(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3562,7 +3562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3585,7 +3585,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i8.nxv4i16(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3596,7 +3596,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -3620,7 +3620,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i32(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3631,7 +3631,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3656,7 +3656,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i8(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3667,7 +3667,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3692,7 +3692,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i64(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3703,7 +3703,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3728,7 +3728,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i8.nxv4i16(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3739,7 +3739,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i8.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -3764,7 +3764,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i32(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv4i8_nxv4i32(i8* %base, %index, i64 %vl) { @@ -3775,7 +3775,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3801,7 +3801,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i8(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv4i8_nxv4i8(i8* %base, %index, i64 %vl) { @@ -3812,7 +3812,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3838,7 +3838,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i64(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv4i8_nxv4i64(i8* %base, %index, i64 %vl) { @@ -3849,7 +3849,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3875,7 +3875,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i8.nxv4i16(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv4i8_nxv4i16(i8* %base, %index, i64 %vl) { @@ -3886,7 +3886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i8.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -3912,7 +3912,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i64(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i64(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i64(,, i16*, , , i64, i64) define @test_vluxseg2_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -3923,7 +3923,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3941,7 +3941,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i32(,, i16*, , , i64, i64) define @test_vluxseg2_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -3952,7 +3952,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3970,7 +3970,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i16(,, i16*, , , i64, i64) define @test_vluxseg2_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -3981,7 +3981,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -3999,7 +3999,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i16.nxv1i8(,, i16*, , , i64, i64) define @test_vluxseg2_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4010,7 +4010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i16.nxv1i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4028,7 +4028,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i64(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i64(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4039,7 +4039,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4059,7 +4059,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i32(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4070,7 +4070,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4090,7 +4090,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i16(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4101,7 +4101,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4121,7 +4121,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i16.nxv1i8(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4132,7 +4132,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i16.nxv1i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4152,7 +4152,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i64(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4163,7 +4163,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4185,7 +4185,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i32(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4196,7 +4196,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4218,7 +4218,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i16(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4229,7 +4229,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4251,7 +4251,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i16.nxv1i8(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4262,7 +4262,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i16.nxv1i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -4284,7 +4284,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i64(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4295,7 +4295,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4318,7 +4318,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i32(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4329,7 +4329,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4352,7 +4352,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i16(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4363,7 +4363,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4386,7 +4386,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i16.nxv1i8(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4397,7 +4397,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -4420,7 +4420,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i64(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4431,7 +4431,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4455,7 +4455,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i32(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4466,7 +4466,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4490,7 +4490,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i16(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4501,7 +4501,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4525,7 +4525,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i16.nxv1i8(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4536,7 +4536,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -4560,7 +4560,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i64(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4571,7 +4571,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4596,7 +4596,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i32(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4607,7 +4607,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4632,7 +4632,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i16(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4643,7 +4643,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4668,7 +4668,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i16.nxv1i8(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4679,7 +4679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -4704,7 +4704,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i64(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv1i16_nxv1i64(i16* %base, %index, i64 %vl) { @@ -4715,7 +4715,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4741,7 +4741,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i32(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv1i16_nxv1i32(i16* %base, %index, i64 %vl) { @@ -4752,7 +4752,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4778,7 +4778,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i16(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv1i16_nxv1i16(i16* %base, %index, i64 %vl) { @@ -4789,7 +4789,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4815,7 +4815,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i16.nxv1i8(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv1i16_nxv1i8(i16* %base, %index, i64 %vl) { @@ -4826,7 +4826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -4852,7 +4852,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32(,, i32*, , , i64, i64) define @test_vluxseg2_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -4863,7 +4863,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4881,7 +4881,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i8(,, i32*, , , i64, i64) define @test_vluxseg2_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -4892,7 +4892,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4910,7 +4910,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i16(,, i32*, , , i64, i64) define @test_vluxseg2_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -4921,7 +4921,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4939,7 +4939,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i64(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i64(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i64(,, i32*, , , i64, i64) define @test_vluxseg2_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -4950,7 +4950,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i32.nxv2i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -4968,7 +4968,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i32(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -4979,7 +4979,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i32( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -4999,7 +4999,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i8(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5010,7 +5010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i8( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5030,7 +5030,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i16(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5041,7 +5041,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i16( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5061,7 +5061,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i64(i32*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i64(,,, i32*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i32.nxv2i64(,,, i32*, , , i64, i64) define @test_vluxseg3_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5072,7 +5072,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i32.nxv2i64( undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5091,7 +5091,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i32(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5102,7 +5102,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i32( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5124,7 +5124,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i8(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5135,7 +5135,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i8( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5157,7 +5157,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i16(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5168,7 +5168,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i16( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5190,7 +5190,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i64(,,,, i32*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i32.nxv2i64(,,,, i32*, , , i64, i64) define @test_vluxseg4_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5201,7 +5201,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i32.nxv2i64( undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -5222,7 +5222,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i32(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5233,7 +5233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5256,7 +5256,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i8(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5267,7 +5267,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5290,7 +5290,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i16(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5301,7 +5301,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5324,7 +5324,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i64(,,,,, i32*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i32.nxv2i64(,,,,, i32*, , , i64, i64) define @test_vluxseg5_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5335,7 +5335,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -5358,7 +5358,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i32(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5369,7 +5369,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5393,7 +5393,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i8(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5404,7 +5404,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5428,7 +5428,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i16(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5439,7 +5439,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5463,7 +5463,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i64(,,,,,, i32*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i32.nxv2i64(,,,,,, i32*, , , i64, i64) define @test_vluxseg6_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5474,7 +5474,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -5498,7 +5498,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i32(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5509,7 +5509,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5534,7 +5534,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i8(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5545,7 +5545,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5570,7 +5570,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i16(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5581,7 +5581,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5606,7 +5606,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i64(,,,,,,, i32*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i32.nxv2i64(,,,,,,, i32*, , , i64, i64) define @test_vluxseg7_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5617,7 +5617,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i32.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -5642,7 +5642,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i32(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv2i32_nxv2i32(i32* %base, %index, i64 %vl) { @@ -5653,7 +5653,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5679,7 +5679,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i8(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv2i32_nxv2i8(i32* %base, %index, i64 %vl) { @@ -5690,7 +5690,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5716,7 +5716,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i16(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv2i32_nxv2i16(i32* %base, %index, i64 %vl) { @@ -5727,7 +5727,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5753,7 +5753,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i64(i32*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i64(,,,,,,,, i32*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i32.nxv2i64(,,,,,,,, i32*, , , i64, i64) define @test_vluxseg8_nxv2i32_nxv2i64(i32* %base, %index, i64 %vl) { @@ -5764,7 +5764,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i64(i32* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i32.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -5790,7 +5790,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -5801,7 +5801,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5819,7 +5819,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -5830,7 +5830,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5848,7 +5848,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i64(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i64(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i64(,, i8*, , , i64, i64) define @test_vluxseg2_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -5859,7 +5859,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5877,7 +5877,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i8.nxv8i32(,, i8*, , , i64, i64) define @test_vluxseg2_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -5888,7 +5888,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i8.nxv8i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -5906,7 +5906,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i16(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -5917,7 +5917,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5936,7 +5936,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i8(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -5947,7 +5947,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5967,7 +5967,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i64(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i64(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -5978,7 +5978,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -5997,7 +5997,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8i8.nxv8i32(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6008,7 +6008,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8i8.nxv8i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6027,7 +6027,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i16(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6038,7 +6038,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6059,7 +6059,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i8(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6070,7 +6070,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6092,7 +6092,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i64(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6103,7 +6103,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6123,7 +6123,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8i8.nxv8i32(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6134,7 +6134,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8i8.nxv8i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -6154,7 +6154,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i16(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6165,7 +6165,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6188,7 +6188,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i8(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6199,7 +6199,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6222,7 +6222,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i64(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6233,7 +6233,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6254,7 +6254,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv8i8.nxv8i32(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6265,7 +6265,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -6286,7 +6286,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i16(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6297,7 +6297,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6321,7 +6321,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i8(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6332,7 +6332,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6356,7 +6356,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i64(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6367,7 +6367,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6389,7 +6389,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv8i8.nxv8i32(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6400,7 +6400,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -6423,7 +6423,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i16(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6434,7 +6434,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6459,7 +6459,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i8(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6470,7 +6470,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6495,7 +6495,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i64(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6506,7 +6506,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6529,7 +6529,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv8i8.nxv8i32(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6540,7 +6540,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv8i8.nxv8i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -6565,7 +6565,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i16(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv8i8_nxv8i16(i8* %base, %index, i64 %vl) { @@ -6576,7 +6576,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6602,7 +6602,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i8(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv8i8_nxv8i8(i8* %base, %index, i64 %vl) { @@ -6613,7 +6613,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6639,7 +6639,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i64(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv8i8_nxv8i64(i8* %base, %index, i64 %vl) { @@ -6650,7 +6650,7 @@ ; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6674,7 +6674,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv8i8.nxv8i32(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv8i8_nxv8i32(i8* %base, %index, i64 %vl) { @@ -6685,7 +6685,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv8i8.nxv8i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -6711,7 +6711,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i32(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i32(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i64.nxv4i32(,, i64*, , , i64, i64) define @test_vluxseg2_nxv4i64_nxv4i32(i64* %base, %index, i64 %vl) { @@ -6722,7 +6722,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6740,7 +6740,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i8(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i8(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i64.nxv4i8(,, i64*, , , i64, i64) define @test_vluxseg2_nxv4i64_nxv4i8(i64* %base, %index, i64 %vl) { @@ -6751,7 +6751,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6769,7 +6769,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i64(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i64(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i64.nxv4i64(,, i64*, , , i64, i64) define @test_vluxseg2_nxv4i64_nxv4i64(i64* %base, %index, i64 %vl) { @@ -6780,7 +6780,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6798,7 +6798,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i16(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i16(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i64.nxv4i16(,, i64*, , , i64, i64) define @test_vluxseg2_nxv4i64_nxv4i16(i64* %base, %index, i64 %vl) { @@ -6809,7 +6809,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i64.nxv4i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6827,7 +6827,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i32(,, i16*, , , i64, i64) define @test_vluxseg2_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -6838,7 +6838,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6856,7 +6856,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i8(,, i16*, , , i64, i64) define @test_vluxseg2_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -6867,7 +6867,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6885,7 +6885,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i64(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i64(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i64(,, i16*, , , i64, i64) define @test_vluxseg2_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -6896,7 +6896,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6914,7 +6914,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4i16.nxv4i16(,, i16*, , , i64, i64) define @test_vluxseg2_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -6925,7 +6925,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4i16.nxv4i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -6943,7 +6943,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i32(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -6954,7 +6954,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -6973,7 +6973,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i8(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -6984,7 +6984,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7004,7 +7004,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i64(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i64(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7015,7 +7015,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7034,7 +7034,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4i16.nxv4i16(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7045,7 +7045,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4i16.nxv4i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7065,7 +7065,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i32(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7076,7 +7076,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7097,7 +7097,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i8(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7108,7 +7108,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7130,7 +7130,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i64(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7141,7 +7141,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7161,7 +7161,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4i16.nxv4i16(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7172,7 +7172,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4i16.nxv4i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -7194,7 +7194,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i32(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7205,7 +7205,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7228,7 +7228,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i8(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7239,7 +7239,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7262,7 +7262,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i64(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7273,7 +7273,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7294,7 +7294,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4i16.nxv4i16(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7305,7 +7305,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -7328,7 +7328,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i32(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7339,7 +7339,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7363,7 +7363,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i8(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7374,7 +7374,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7398,7 +7398,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i64(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7409,7 +7409,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7432,7 +7432,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4i16.nxv4i16(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7443,7 +7443,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -7467,7 +7467,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i32(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7478,7 +7478,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7503,7 +7503,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i8(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7514,7 +7514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7539,7 +7539,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i64(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7550,7 +7550,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7575,7 +7575,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4i16.nxv4i16(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7586,7 +7586,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4i16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -7611,7 +7611,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i32(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv4i16_nxv4i32(i16* %base, %index, i64 %vl) { @@ -7622,7 +7622,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7648,7 +7648,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i8(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv4i16_nxv4i8(i16* %base, %index, i64 %vl) { @@ -7659,7 +7659,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7685,7 +7685,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i64(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv4i16_nxv4i64(i16* %base, %index, i64 %vl) { @@ -7696,7 +7696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7722,7 +7722,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4i16.nxv4i16(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv4i16_nxv4i16(i16* %base, %index, i64 %vl) { @@ -7733,7 +7733,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4i16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -7759,7 +7759,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i64(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i64(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i64(,, i8*, , , i64, i64) define @test_vluxseg2_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -7770,7 +7770,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7788,7 +7788,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i32(,, i8*, , , i64, i64) define @test_vluxseg2_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -7799,7 +7799,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7817,7 +7817,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -7828,7 +7828,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7846,7 +7846,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1i8.nxv1i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -7857,7 +7857,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1i8.nxv1i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -7875,7 +7875,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i64(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i64(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -7886,7 +7886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7906,7 +7906,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i32(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -7917,7 +7917,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7937,7 +7937,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i16(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -7948,7 +7948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7968,7 +7968,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1i8.nxv1i8(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -7979,7 +7979,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1i8.nxv1i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -7999,7 +7999,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i64(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8010,7 +8010,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8032,7 +8032,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i32(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8043,7 +8043,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8065,7 +8065,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i16(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8076,7 +8076,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8098,7 +8098,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1i8.nxv1i8(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8109,7 +8109,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1i8.nxv1i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8131,7 +8131,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i64(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8142,7 +8142,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8165,7 +8165,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i32(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8176,7 +8176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8199,7 +8199,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i16(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8210,7 +8210,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8233,7 +8233,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1i8.nxv1i8(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8244,7 +8244,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -8267,7 +8267,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i64(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8278,7 +8278,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8302,7 +8302,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i32(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8313,7 +8313,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8337,7 +8337,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i16(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8348,7 +8348,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8372,7 +8372,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1i8.nxv1i8(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8383,7 +8383,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -8407,7 +8407,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i64(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8418,7 +8418,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8443,7 +8443,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i32(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8454,7 +8454,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8479,7 +8479,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i16(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8490,7 +8490,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8515,7 +8515,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1i8.nxv1i8(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8526,7 +8526,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1i8.nxv1i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -8551,7 +8551,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i64(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv1i8_nxv1i64(i8* %base, %index, i64 %vl) { @@ -8562,7 +8562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8588,7 +8588,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i32(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv1i8_nxv1i32(i8* %base, %index, i64 %vl) { @@ -8599,7 +8599,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8625,7 +8625,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i16(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv1i8_nxv1i16(i8* %base, %index, i64 %vl) { @@ -8636,7 +8636,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8662,7 +8662,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1i8.nxv1i8(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv1i8_nxv1i8(i8* %base, %index, i64 %vl) { @@ -8673,7 +8673,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1i8.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -8699,7 +8699,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i32(,, i8*, , , i64, i64) define @test_vluxseg2_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8710,7 +8710,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i32( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8728,7 +8728,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8739,7 +8739,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8757,7 +8757,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -8768,7 +8768,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8786,7 +8786,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i64(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i64(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i8.nxv2i64(,, i8*, , , i64, i64) define @test_vluxseg2_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -8797,7 +8797,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i8.nxv2i64( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -8815,7 +8815,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i32(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8826,7 +8826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i32( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8846,7 +8846,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i8(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8857,7 +8857,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i8( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8877,7 +8877,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i16(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -8888,7 +8888,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i16( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8908,7 +8908,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i64(i8*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i64(,,, i8*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i8.nxv2i64(,,, i8*, , , i64, i64) define @test_vluxseg3_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -8919,7 +8919,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i8.nxv2i64( undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -8938,7 +8938,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i32(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -8949,7 +8949,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i32( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -8971,7 +8971,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i8(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -8982,7 +8982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i8( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9004,7 +9004,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i16(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9015,7 +9015,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i16( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9037,7 +9037,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i64(,,,, i8*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i8.nxv2i64(,,,, i8*, , , i64, i64) define @test_vluxseg4_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9048,7 +9048,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i8.nxv2i64( undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -9069,7 +9069,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i32(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9080,7 +9080,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9103,7 +9103,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i8(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9114,7 +9114,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9137,7 +9137,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i16(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9148,7 +9148,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9171,7 +9171,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i64(,,,,, i8*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i8.nxv2i64(,,,,, i8*, , , i64, i64) define @test_vluxseg5_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9182,7 +9182,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -9205,7 +9205,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i32(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9216,7 +9216,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9240,7 +9240,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i8(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9251,7 +9251,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9275,7 +9275,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i16(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9286,7 +9286,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9310,7 +9310,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i64(,,,,,, i8*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i8.nxv2i64(,,,,,, i8*, , , i64, i64) define @test_vluxseg6_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9321,7 +9321,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -9345,7 +9345,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i32(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9356,7 +9356,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9381,7 +9381,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i8(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9392,7 +9392,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9417,7 +9417,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i16(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9428,7 +9428,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9453,7 +9453,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i64(,,,,,,, i8*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i8.nxv2i64(,,,,,,, i8*, , , i64, i64) define @test_vluxseg7_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9464,7 +9464,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i8.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -9489,7 +9489,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i32(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv2i8_nxv2i32(i8* %base, %index, i64 %vl) { @@ -9500,7 +9500,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9526,7 +9526,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i8(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv2i8_nxv2i8(i8* %base, %index, i64 %vl) { @@ -9537,7 +9537,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9563,7 +9563,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i16(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv2i8_nxv2i16(i8* %base, %index, i64 %vl) { @@ -9574,7 +9574,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9600,7 +9600,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i64(i8*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i64(,,,,,,,, i8*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i8.nxv2i64(,,,,,,,, i8*, , , i64, i64) define @test_vluxseg8_nxv2i8_nxv2i64(i8* %base, %index, i64 %vl) { @@ -9611,7 +9611,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i64(i8* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i8.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -9637,7 +9637,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i16(,, i32*, , , i64, i64) define @test_vluxseg2_nxv8i32_nxv8i16(i32* %base, %index, i64 %vl) { @@ -9648,7 +9648,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i16( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9666,7 +9666,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i8(,, i32*, , , i64, i64) define @test_vluxseg2_nxv8i32_nxv8i8(i32* %base, %index, i64 %vl) { @@ -9677,7 +9677,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i8( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9695,7 +9695,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i64(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i64(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i64(,, i32*, , , i64, i64) define @test_vluxseg2_nxv8i32_nxv8i64(i32* %base, %index, i64 %vl) { @@ -9706,7 +9706,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i64(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i64( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9724,7 +9724,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(i32*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(,, i32*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8i32.nxv8i32(,, i32*, , , i64, i64) define @test_vluxseg2_nxv8i32_nxv8i32(i32* %base, %index, i64 %vl) { @@ -9735,7 +9735,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32(i32* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8i32.nxv8i32( undef, undef, i32* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9753,7 +9753,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv32i8.nxv32i16(,, i8*, , , i64, i64) define @test_vluxseg2_nxv32i8_nxv32i16(i8* %base, %index, i64 %vl) { @@ -9764,7 +9764,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i16( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9782,7 +9782,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(i8*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(,, i8*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv32i8.nxv32i8(,, i8*, , , i64, i64) define @test_vluxseg2_nxv32i8_nxv32i8(i8* %base, %index, i64 %vl) { @@ -9793,7 +9793,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8(i8* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv32i8.nxv32i8( undef, undef, i8* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9811,7 +9811,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i32(,, i16*, , , i64, i64) define @test_vluxseg2_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -9822,7 +9822,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i32( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9840,7 +9840,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i8(,, i16*, , , i64, i64) define @test_vluxseg2_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -9851,7 +9851,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i8( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9869,7 +9869,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i16(,, i16*, , , i64, i64) define @test_vluxseg2_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -9880,7 +9880,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i16( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9898,7 +9898,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i64(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i64(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i16.nxv2i64(,, i16*, , , i64, i64) define @test_vluxseg2_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -9909,7 +9909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i16.nxv2i64( undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -9927,7 +9927,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i32(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -9938,7 +9938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i32( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9958,7 +9958,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i8(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -9969,7 +9969,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i8( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -9989,7 +9989,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i16(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10000,7 +10000,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i16( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10020,7 +10020,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i64(i16*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i64(,,, i16*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i16.nxv2i64(,,, i16*, , , i64, i64) define @test_vluxseg3_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10031,7 +10031,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i16.nxv2i64( undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10050,7 +10050,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i32(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10061,7 +10061,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i32( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10083,7 +10083,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i8(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10094,7 +10094,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i8( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10116,7 +10116,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i16(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10127,7 +10127,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i16( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10149,7 +10149,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i64(,,,, i16*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i16.nxv2i64(,,,, i16*, , , i64, i64) define @test_vluxseg4_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10160,7 +10160,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i16.nxv2i64( undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -10181,7 +10181,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i32(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10192,7 +10192,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10215,7 +10215,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i8(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10226,7 +10226,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10249,7 +10249,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i16(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10260,7 +10260,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10283,7 +10283,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i64(,,,,, i16*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2i16.nxv2i64(,,,,, i16*, , , i64, i64) define @test_vluxseg5_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10294,7 +10294,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -10317,7 +10317,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i32(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10328,7 +10328,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10352,7 +10352,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i8(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10363,7 +10363,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10387,7 +10387,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i16(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10398,7 +10398,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10422,7 +10422,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i64(,,,,,, i16*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2i16.nxv2i64(,,,,,, i16*, , , i64, i64) define @test_vluxseg6_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10433,7 +10433,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -10457,7 +10457,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i32(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10468,7 +10468,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10493,7 +10493,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i8(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10504,7 +10504,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10529,7 +10529,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i16(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10540,7 +10540,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10565,7 +10565,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i64(,,,,,,, i16*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2i16.nxv2i64(,,,,,,, i16*, , , i64, i64) define @test_vluxseg7_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10576,7 +10576,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2i16.nxv2i64( undef, undef, undef, undef, undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -10601,7 +10601,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i32(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv2i16_nxv2i32(i16* %base, %index, i64 %vl) { @@ -10612,7 +10612,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10638,7 +10638,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i8(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv2i16_nxv2i8(i16* %base, %index, i64 %vl) { @@ -10649,7 +10649,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10675,7 +10675,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i16(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv2i16_nxv2i16(i16* %base, %index, i64 %vl) { @@ -10686,7 +10686,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10712,7 +10712,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i64(i16*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i64(,,,,,,,, i16*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2i16.nxv2i64(,,,,,,,, i16*, , , i64, i64) define @test_vluxseg8_nxv2i16_nxv2i64(i16* %base, %index, i64 %vl) { @@ -10723,7 +10723,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i64(i16* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2i16.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, i16* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -10749,7 +10749,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i32(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i32(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i64.nxv2i32(,, i64*, , , i64, i64) define @test_vluxseg2_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -10760,7 +10760,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i32( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10778,7 +10778,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i8(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i8(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i64.nxv2i8(,, i64*, , , i64, i64) define @test_vluxseg2_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -10789,7 +10789,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i8( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10807,7 +10807,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i16(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i16(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i64.nxv2i16(,, i64*, , , i64, i64) define @test_vluxseg2_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -10818,7 +10818,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i16( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10836,7 +10836,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i64(i64*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i64(,, i64*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2i64.nxv2i64(,, i64*, , , i64, i64) define @test_vluxseg2_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -10847,7 +10847,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2i64.nxv2i64( undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -10865,7 +10865,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i32(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i32(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i64.nxv2i32(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -10876,7 +10876,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i32( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10896,7 +10896,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i8(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i8(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i64.nxv2i8(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -10907,7 +10907,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i8( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10927,7 +10927,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i16(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i16(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i64.nxv2i16(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -10938,7 +10938,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i16( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10958,7 +10958,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i64(i64*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i64(,,, i64*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2i64.nxv2i64(,,, i64*, , , i64, i64) define @test_vluxseg3_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -10969,7 +10969,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2i64.nxv2i64( undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -10989,7 +10989,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i32(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i32(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i64.nxv2i32(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv2i64_nxv2i32(i64* %base, %index, i64 %vl) { @@ -11000,7 +11000,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i32(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i32( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11022,7 +11022,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i8(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i8(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i64.nxv2i8(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv2i64_nxv2i8(i64* %base, %index, i64 %vl) { @@ -11033,7 +11033,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i8(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i8( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11055,7 +11055,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i16(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i16(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i64.nxv2i16(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv2i64_nxv2i16(i64* %base, %index, i64 %vl) { @@ -11066,7 +11066,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i16(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i16( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11088,7 +11088,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i64(i64*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i64(,,,, i64*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2i64.nxv2i64(,,,, i64*, , , i64, i64) define @test_vluxseg4_nxv2i64_nxv2i64(i64* %base, %index, i64 %vl) { @@ -11099,7 +11099,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i64(i64* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2i64.nxv2i64( undef, undef, undef, undef, i64* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11121,7 +11121,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i16(,, half*, , , i64, i64) define @test_vluxseg2_nxv16f16_nxv16i16(half* %base, %index, i64 %vl) { @@ -11132,7 +11132,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11150,7 +11150,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i8(,, half*, , , i64, i64) define @test_vluxseg2_nxv16f16_nxv16i8(half* %base, %index, i64 %vl) { @@ -11161,7 +11161,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11179,7 +11179,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16f16.nxv16i32(,, half*, , , i64, i64) define @test_vluxseg2_nxv16f16_nxv16i32(half* %base, %index, i64 %vl) { @@ -11190,7 +11190,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16f16.nxv16i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11208,7 +11208,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i32(,, double*, , , i64, i64) define @test_vluxseg2_nxv4f64_nxv4i32(double* %base, %index, i64 %vl) { @@ -11219,7 +11219,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11237,7 +11237,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i8(,, double*, , , i64, i64) define @test_vluxseg2_nxv4f64_nxv4i8(double* %base, %index, i64 %vl) { @@ -11248,7 +11248,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11266,7 +11266,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i64(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i64(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i64(,, double*, , , i64, i64) define @test_vluxseg2_nxv4f64_nxv4i64(double* %base, %index, i64 %vl) { @@ -11277,7 +11277,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11295,7 +11295,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f64.nxv4i16(,, double*, , , i64, i64) define @test_vluxseg2_nxv4f64_nxv4i16(double* %base, %index, i64 %vl) { @@ -11306,7 +11306,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f64.nxv4i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11324,7 +11324,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i64(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i64(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i64(,, double*, , , i64, i64) define @test_vluxseg2_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11335,7 +11335,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11353,7 +11353,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i32(,, double*, , , i64, i64) define @test_vluxseg2_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11364,7 +11364,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11382,7 +11382,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i16(,, double*, , , i64, i64) define @test_vluxseg2_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11393,7 +11393,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11411,7 +11411,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f64.nxv1i8(,, double*, , , i64, i64) define @test_vluxseg2_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11422,7 +11422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f64.nxv1i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -11440,7 +11440,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i64(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i64(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i64(,,, double*, , , i64, i64) define @test_vluxseg3_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11451,7 +11451,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i64( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11471,7 +11471,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i32(,,, double*, , , i64, i64) define @test_vluxseg3_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11482,7 +11482,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i32( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11502,7 +11502,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i16(,,, double*, , , i64, i64) define @test_vluxseg3_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11513,7 +11513,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i16( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11533,7 +11533,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f64.nxv1i8(,,, double*, , , i64, i64) define @test_vluxseg3_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11544,7 +11544,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f64.nxv1i8( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -11564,7 +11564,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i64(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i64(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i64(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11575,7 +11575,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i64( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11597,7 +11597,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i32(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11608,7 +11608,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i32( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11630,7 +11630,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i16(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11641,7 +11641,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i16( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11663,7 +11663,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f64.nxv1i8(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11674,7 +11674,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f64.nxv1i8( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -11696,7 +11696,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i64(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i64(,,,,, double*, , , i64, i64) define @test_vluxseg5_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11707,7 +11707,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11730,7 +11730,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i32(,,,,, double*, , , i64, i64) define @test_vluxseg5_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11741,7 +11741,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11764,7 +11764,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i16(,,,,, double*, , , i64, i64) define @test_vluxseg5_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11775,7 +11775,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11798,7 +11798,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(,,,,, double*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f64.nxv1i8(,,,,, double*, , , i64, i64) define @test_vluxseg5_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11809,7 +11809,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -11832,7 +11832,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i64(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i64(,,,,,, double*, , , i64, i64) define @test_vluxseg6_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11843,7 +11843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11867,7 +11867,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i32(,,,,,, double*, , , i64, i64) define @test_vluxseg6_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -11878,7 +11878,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11902,7 +11902,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i16(,,,,,, double*, , , i64, i64) define @test_vluxseg6_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -11913,7 +11913,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11937,7 +11937,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(,,,,,, double*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f64.nxv1i8(,,,,,, double*, , , i64, i64) define @test_vluxseg6_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -11948,7 +11948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -11972,7 +11972,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i64(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i64(,,,,,,, double*, , , i64, i64) define @test_vluxseg7_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -11983,7 +11983,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i64( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12008,7 +12008,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i32(,,,,,,, double*, , , i64, i64) define @test_vluxseg7_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -12019,7 +12019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i32( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12044,7 +12044,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i16(,,,,,,, double*, , , i64, i64) define @test_vluxseg7_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -12055,7 +12055,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i16( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12080,7 +12080,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(,,,,,,, double*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f64.nxv1i8(,,,,,,, double*, , , i64, i64) define @test_vluxseg7_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -12091,7 +12091,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f64.nxv1i8( undef, undef, undef, undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12116,7 +12116,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i64(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i64(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i64(,,,,,,,, double*, , , i64, i64) define @test_vluxseg8_nxv1f64_nxv1i64(double* %base, %index, i64 %vl) { @@ -12127,7 +12127,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12153,7 +12153,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i32(,,,,,,,, double*, , , i64, i64) define @test_vluxseg8_nxv1f64_nxv1i32(double* %base, %index, i64 %vl) { @@ -12164,7 +12164,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12190,7 +12190,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i16(,,,,,,,, double*, , , i64, i64) define @test_vluxseg8_nxv1f64_nxv1i16(double* %base, %index, i64 %vl) { @@ -12201,7 +12201,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12227,7 +12227,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(double*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(,,,,,,,, double*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f64.nxv1i8(,,,,,,,, double*, , , i64, i64) define @test_vluxseg8_nxv1f64_nxv1i8(double* %base, %index, i64 %vl) { @@ -12238,7 +12238,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f64.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -12264,7 +12264,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i32(,, float*, , , i64, i64) define @test_vluxseg2_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12275,7 +12275,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12293,7 +12293,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i8(,, float*, , , i64, i64) define @test_vluxseg2_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12304,7 +12304,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12322,7 +12322,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i16(,, float*, , , i64, i64) define @test_vluxseg2_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12333,7 +12333,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12351,7 +12351,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i64(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i64(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f32.nxv2i64(,, float*, , , i64, i64) define @test_vluxseg2_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12362,7 +12362,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f32.nxv2i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -12380,7 +12380,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i32(,,, float*, , , i64, i64) define @test_vluxseg3_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12391,7 +12391,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12411,7 +12411,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i8(,,, float*, , , i64, i64) define @test_vluxseg3_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12422,7 +12422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12442,7 +12442,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i16(,,, float*, , , i64, i64) define @test_vluxseg3_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12453,7 +12453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12473,7 +12473,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i64(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i64(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f32.nxv2i64(,,, float*, , , i64, i64) define @test_vluxseg3_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12484,7 +12484,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f32.nxv2i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -12503,7 +12503,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i32(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12514,7 +12514,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12536,7 +12536,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i8(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12547,7 +12547,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12569,7 +12569,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i16(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12580,7 +12580,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12602,7 +12602,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i64(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f32.nxv2i64(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12613,7 +12613,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f32.nxv2i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -12634,7 +12634,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i32(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12645,7 +12645,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12668,7 +12668,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i8(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12679,7 +12679,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12702,7 +12702,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i16(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12713,7 +12713,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12736,7 +12736,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i64(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f32.nxv2i64(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12747,7 +12747,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -12770,7 +12770,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i32(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12781,7 +12781,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12805,7 +12805,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i8(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12816,7 +12816,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12840,7 +12840,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i16(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12851,7 +12851,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12875,7 +12875,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i64(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f32.nxv2i64(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -12886,7 +12886,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -12910,7 +12910,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i32(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -12921,7 +12921,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12946,7 +12946,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i8(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -12957,7 +12957,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -12982,7 +12982,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i16(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -12993,7 +12993,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13018,7 +13018,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i64(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f32.nxv2i64(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -13029,7 +13029,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f32.nxv2i64( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13054,7 +13054,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i32(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv2f32_nxv2i32(float* %base, %index, i64 %vl) { @@ -13065,7 +13065,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13091,7 +13091,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i8(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv2f32_nxv2i8(float* %base, %index, i64 %vl) { @@ -13102,7 +13102,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13128,7 +13128,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i16(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv2f32_nxv2i16(float* %base, %index, i64 %vl) { @@ -13139,7 +13139,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13165,7 +13165,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i64(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i64(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f32.nxv2i64(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv2f32_nxv2i64(float* %base, %index, i64 %vl) { @@ -13176,7 +13176,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f32.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -13202,7 +13202,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i64(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i64(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i64(,, half*, , , i64, i64) define @test_vluxseg2_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13213,7 +13213,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13231,7 +13231,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i32(,, half*, , , i64, i64) define @test_vluxseg2_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13242,7 +13242,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13260,7 +13260,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i16(,, half*, , , i64, i64) define @test_vluxseg2_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13271,7 +13271,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13289,7 +13289,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f16.nxv1i8(,, half*, , , i64, i64) define @test_vluxseg2_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13300,7 +13300,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f16.nxv1i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -13318,7 +13318,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i64(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i64(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i64(,,, half*, , , i64, i64) define @test_vluxseg3_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13329,7 +13329,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13349,7 +13349,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i32(,,, half*, , , i64, i64) define @test_vluxseg3_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13360,7 +13360,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13380,7 +13380,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i16(,,, half*, , , i64, i64) define @test_vluxseg3_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13391,7 +13391,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13411,7 +13411,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f16.nxv1i8(,,, half*, , , i64, i64) define @test_vluxseg3_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13422,7 +13422,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f16.nxv1i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -13442,7 +13442,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i64(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i64(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13453,7 +13453,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13475,7 +13475,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i32(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13486,7 +13486,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13508,7 +13508,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i16(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13519,7 +13519,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13541,7 +13541,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f16.nxv1i8(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13552,7 +13552,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f16.nxv1i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -13574,7 +13574,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i64(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13585,7 +13585,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13608,7 +13608,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i32(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13619,7 +13619,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13642,7 +13642,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i16(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13653,7 +13653,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13676,7 +13676,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f16.nxv1i8(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13687,7 +13687,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -13710,7 +13710,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i64(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13721,7 +13721,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13745,7 +13745,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i32(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13756,7 +13756,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13780,7 +13780,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i16(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13791,7 +13791,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13815,7 +13815,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f16.nxv1i8(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13826,7 +13826,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -13850,7 +13850,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i64(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -13861,7 +13861,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13886,7 +13886,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i32(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -13897,7 +13897,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13922,7 +13922,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i16(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -13933,7 +13933,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13958,7 +13958,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f16.nxv1i8(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -13969,7 +13969,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f16.nxv1i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -13994,7 +13994,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i64(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv1f16_nxv1i64(half* %base, %index, i64 %vl) { @@ -14005,7 +14005,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14031,7 +14031,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i32(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv1f16_nxv1i32(half* %base, %index, i64 %vl) { @@ -14042,7 +14042,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14068,7 +14068,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i16(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv1f16_nxv1i16(half* %base, %index, i64 %vl) { @@ -14079,7 +14079,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14105,7 +14105,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f16.nxv1i8(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv1f16_nxv1i8(half* %base, %index, i64 %vl) { @@ -14116,7 +14116,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f16.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14142,7 +14142,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i64(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i64(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i64(,, float*, , , i64, i64) define @test_vluxseg2_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14153,7 +14153,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14171,7 +14171,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i32(,, float*, , , i64, i64) define @test_vluxseg2_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14182,7 +14182,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14200,7 +14200,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i16(,, float*, , , i64, i64) define @test_vluxseg2_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14211,7 +14211,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14229,7 +14229,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv1f32.nxv1i8(,, float*, , , i64, i64) define @test_vluxseg2_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14240,7 +14240,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv1f32.nxv1i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -14258,7 +14258,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i64(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i64(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i64(,,, float*, , , i64, i64) define @test_vluxseg3_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14269,7 +14269,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14289,7 +14289,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i32(,,, float*, , , i64, i64) define @test_vluxseg3_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14300,7 +14300,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14320,7 +14320,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i16(,,, float*, , , i64, i64) define @test_vluxseg3_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14331,7 +14331,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14351,7 +14351,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv1f32.nxv1i8(,,, float*, , , i64, i64) define @test_vluxseg3_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14362,7 +14362,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv1f32.nxv1i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -14382,7 +14382,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i64(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i64(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14393,7 +14393,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14415,7 +14415,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i32(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14426,7 +14426,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14448,7 +14448,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i16(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14459,7 +14459,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14481,7 +14481,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv1f32.nxv1i8(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14492,7 +14492,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv1f32.nxv1i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -14514,7 +14514,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i64(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i64(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14525,7 +14525,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14548,7 +14548,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i32(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14559,7 +14559,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14582,7 +14582,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i16(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14593,7 +14593,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14616,7 +14616,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(,,,,, float*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv1f32.nxv1i8(,,,,, float*, , , i64, i64) define @test_vluxseg5_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14627,7 +14627,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -14650,7 +14650,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i64(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i64(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14661,7 +14661,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14685,7 +14685,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i32(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14696,7 +14696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14720,7 +14720,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i16(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14731,7 +14731,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14755,7 +14755,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(,,,,,, float*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv1f32.nxv1i8(,,,,,, float*, , , i64, i64) define @test_vluxseg6_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14766,7 +14766,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -14790,7 +14790,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i64(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i64(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14801,7 +14801,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i64( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14826,7 +14826,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i32(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14837,7 +14837,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i32( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14862,7 +14862,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i16(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -14873,7 +14873,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i16( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14898,7 +14898,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(,,,,,,, float*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv1f32.nxv1i8(,,,,,,, float*, , , i64, i64) define @test_vluxseg7_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -14909,7 +14909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv1f32.nxv1i8( undef, undef, undef, undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -14934,7 +14934,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i64(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i64(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i64(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv1f32_nxv1i64(float* %base, %index, i64 %vl) { @@ -14945,7 +14945,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i64( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -14971,7 +14971,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i32(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv1f32_nxv1i32(float* %base, %index, i64 %vl) { @@ -14982,7 +14982,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i32( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15008,7 +15008,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i16(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv1f32_nxv1i16(float* %base, %index, i64 %vl) { @@ -15019,7 +15019,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i16( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15045,7 +15045,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(float*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(,,,,,,,, float*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv1f32.nxv1i8(,,,,,,,, float*, , , i64, i64) define @test_vluxseg8_nxv1f32_nxv1i8(float* %base, %index, i64 %vl) { @@ -15056,7 +15056,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv1f32.nxv1i8( undef, undef , undef , undef, undef , undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -15082,7 +15082,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i16(,, half*, , , i64, i64) define @test_vluxseg2_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15093,7 +15093,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15111,7 +15111,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i8(,, half*, , , i64, i64) define @test_vluxseg2_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15122,7 +15122,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15140,7 +15140,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i64(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i64(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i64(,, half*, , , i64, i64) define @test_vluxseg2_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15151,7 +15151,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15169,7 +15169,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f16.nxv8i32(,, half*, , , i64, i64) define @test_vluxseg2_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15180,7 +15180,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f16.nxv8i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15198,7 +15198,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i16(,,, half*, , , i64, i64) define @test_vluxseg3_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15209,7 +15209,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15229,7 +15229,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i8(,,, half*, , , i64, i64) define @test_vluxseg3_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15240,7 +15240,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15260,7 +15260,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i64(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i64(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i64(,,, half*, , , i64, i64) define @test_vluxseg3_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15271,7 +15271,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15290,7 +15290,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv8f16.nxv8i32(,,, half*, , , i64, i64) define @test_vluxseg3_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15301,7 +15301,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv8f16.nxv8i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15320,7 +15320,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i16(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv8f16_nxv8i16(half* %base, %index, i64 %vl) { @@ -15331,7 +15331,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15353,7 +15353,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i8(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv8f16_nxv8i8(half* %base, %index, i64 %vl) { @@ -15364,7 +15364,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15386,7 +15386,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i64(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i64(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv8f16_nxv8i64(half* %base, %index, i64 %vl) { @@ -15397,7 +15397,7 @@ ; CHECK-NEXT: vmv2r.v v8, v18 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15417,7 +15417,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv8f16.nxv8i32(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv8f16_nxv8i32(half* %base, %index, i64 %vl) { @@ -15428,7 +15428,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv8f16.nxv8i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15449,7 +15449,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i16(,, float*, , , i64, i64) define @test_vluxseg2_nxv8f32_nxv8i16(float* %base, %index, i64 %vl) { @@ -15460,7 +15460,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15478,7 +15478,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i8(,, float*, , , i64, i64) define @test_vluxseg2_nxv8f32_nxv8i8(float* %base, %index, i64 %vl) { @@ -15489,7 +15489,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15507,7 +15507,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i64(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i64(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i64(,, float*, , , i64, i64) define @test_vluxseg2_nxv8f32_nxv8i64(float* %base, %index, i64 %vl) { @@ -15518,7 +15518,7 @@ ; CHECK-NEXT: vmv4r.v v8, v20 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15536,7 +15536,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv8f32.nxv8i32(,, float*, , , i64, i64) define @test_vluxseg2_nxv8f32_nxv8i32(float* %base, %index, i64 %vl) { @@ -15547,7 +15547,7 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv8f32.nxv8i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15565,7 +15565,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i32(,, double*, , , i64, i64) define @test_vluxseg2_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15576,7 +15576,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i32( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15594,7 +15594,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i8(,, double*, , , i64, i64) define @test_vluxseg2_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15605,7 +15605,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i8( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15623,7 +15623,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i16(,, double*, , , i64, i64) define @test_vluxseg2_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15634,7 +15634,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i16( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15652,7 +15652,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i64(double*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i64(,, double*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f64.nxv2i64(,, double*, , , i64, i64) define @test_vluxseg2_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15663,7 +15663,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f64.nxv2i64( undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15681,7 +15681,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i32(,,, double*, , , i64, i64) define @test_vluxseg3_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15692,7 +15692,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i32( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15712,7 +15712,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i8(,,, double*, , , i64, i64) define @test_vluxseg3_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15723,7 +15723,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i8( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15743,7 +15743,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i16(,,, double*, , , i64, i64) define @test_vluxseg3_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15754,7 +15754,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i16( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15774,7 +15774,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i64(double*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i64(,,, double*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f64.nxv2i64(,,, double*, , , i64, i64) define @test_vluxseg3_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15785,7 +15785,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f64.nxv2i64( undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -15805,7 +15805,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i32(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv2f64_nxv2i32(double* %base, %index, i64 %vl) { @@ -15816,7 +15816,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i32( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15838,7 +15838,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i8(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv2f64_nxv2i8(double* %base, %index, i64 %vl) { @@ -15849,7 +15849,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i8( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15871,7 +15871,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i16(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv2f64_nxv2i16(double* %base, %index, i64 %vl) { @@ -15882,7 +15882,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i16( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15904,7 +15904,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i64(double*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i64(,,,, double*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f64.nxv2i64(,,,, double*, , , i64, i64) define @test_vluxseg4_nxv2f64_nxv2i64(double* %base, %index, i64 %vl) { @@ -15915,7 +15915,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i64(double* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f64.nxv2i64( undef, undef, undef, undef, double* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -15937,7 +15937,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i32(,, half*, , , i64, i64) define @test_vluxseg2_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -15948,7 +15948,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15966,7 +15966,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i8(,, half*, , , i64, i64) define @test_vluxseg2_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -15977,7 +15977,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -15995,7 +15995,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i64(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i64(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i64(,, half*, , , i64, i64) define @test_vluxseg2_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16006,7 +16006,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16024,7 +16024,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f16.nxv4i16(,, half*, , , i64, i64) define @test_vluxseg2_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16035,7 +16035,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f16.nxv4i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16053,7 +16053,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i32(,,, half*, , , i64, i64) define @test_vluxseg3_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16064,7 +16064,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16083,7 +16083,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i8(,,, half*, , , i64, i64) define @test_vluxseg3_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16094,7 +16094,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16114,7 +16114,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i64(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i64(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i64(,,, half*, , , i64, i64) define @test_vluxseg3_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16125,7 +16125,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16144,7 +16144,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f16.nxv4i16(,,, half*, , , i64, i64) define @test_vluxseg3_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16155,7 +16155,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f16.nxv4i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -16175,7 +16175,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i32(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16186,7 +16186,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16207,7 +16207,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i8(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16218,7 +16218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16240,7 +16240,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i64(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i64(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16251,7 +16251,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16271,7 +16271,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f16.nxv4i16(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16282,7 +16282,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f16.nxv4i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -16304,7 +16304,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i32(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16315,7 +16315,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16338,7 +16338,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i8(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16349,7 +16349,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16372,7 +16372,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i64(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16383,7 +16383,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16404,7 +16404,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv4f16.nxv4i16(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16415,7 +16415,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -16438,7 +16438,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i32(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16449,7 +16449,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16473,7 +16473,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i8(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16484,7 +16484,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16508,7 +16508,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i64(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16519,7 +16519,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16542,7 +16542,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv4f16.nxv4i16(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16553,7 +16553,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -16577,7 +16577,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i32(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16588,7 +16588,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16613,7 +16613,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i8(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16624,7 +16624,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16649,7 +16649,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i64(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16660,7 +16660,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16685,7 +16685,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv4f16.nxv4i16(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16696,7 +16696,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv4f16.nxv4i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -16721,7 +16721,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i32(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv4f16_nxv4i32(half* %base, %index, i64 %vl) { @@ -16732,7 +16732,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16758,7 +16758,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i8(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv4f16_nxv4i8(half* %base, %index, i64 %vl) { @@ -16769,7 +16769,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16795,7 +16795,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i64(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv4f16_nxv4i64(half* %base, %index, i64 %vl) { @@ -16806,7 +16806,7 @@ ; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16832,7 +16832,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv4f16.nxv4i16(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv4f16_nxv4i16(half* %base, %index, i64 %vl) { @@ -16843,7 +16843,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv4f16.nxv4i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -16869,7 +16869,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i32(,, half*, , , i64, i64) define @test_vluxseg2_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -16880,7 +16880,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i32( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16898,7 +16898,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i8(,, half*, , , i64, i64) define @test_vluxseg2_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -16909,7 +16909,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i8( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16927,7 +16927,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i16(,, half*, , , i64, i64) define @test_vluxseg2_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -16938,7 +16938,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i16( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16956,7 +16956,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i64(half*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i64(,, half*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv2f16.nxv2i64(,, half*, , , i64, i64) define @test_vluxseg2_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -16967,7 +16967,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv2f16.nxv2i64( undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -16985,7 +16985,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i32(,,, half*, , , i64, i64) define @test_vluxseg3_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -16996,7 +16996,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i32( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17016,7 +17016,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i8(,,, half*, , , i64, i64) define @test_vluxseg3_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17027,7 +17027,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i8( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17047,7 +17047,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i16(,,, half*, , , i64, i64) define @test_vluxseg3_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17058,7 +17058,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i16( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17078,7 +17078,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i64(half*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i64(,,, half*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv2f16.nxv2i64(,,, half*, , , i64, i64) define @test_vluxseg3_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17089,7 +17089,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv2f16.nxv2i64( undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17108,7 +17108,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i32(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17119,7 +17119,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i32( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17141,7 +17141,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i8(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17152,7 +17152,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i8( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17174,7 +17174,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i16(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17185,7 +17185,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i16( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17207,7 +17207,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i64(half*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i64(,,,, half*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv2f16.nxv2i64(,,,, half*, , , i64, i64) define @test_vluxseg4_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17218,7 +17218,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv2f16.nxv2i64( undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -17239,7 +17239,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i32(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17250,7 +17250,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17273,7 +17273,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i8(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17284,7 +17284,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17307,7 +17307,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i16(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17318,7 +17318,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17341,7 +17341,7 @@ ret %1 } -declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i64(,,,,, half*, , i64) declare {,,,,} @llvm.riscv.vluxseg5.mask.nxv2f16.nxv2i64(,,,,, half*, , , i64, i64) define @test_vluxseg5_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17352,7 +17352,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,} @llvm.riscv.vluxseg5.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,} %0, 1 ret %1 } @@ -17375,7 +17375,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i32(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17386,7 +17386,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17410,7 +17410,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i8(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17421,7 +17421,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17445,7 +17445,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i16(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17456,7 +17456,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17480,7 +17480,7 @@ ret %1 } -declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i64(,,,,,, half*, , i64) declare {,,,,,} @llvm.riscv.vluxseg6.mask.nxv2f16.nxv2i64(,,,,,, half*, , , i64, i64) define @test_vluxseg6_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17491,7 +17491,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,} @llvm.riscv.vluxseg6.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,} %0, 1 ret %1 } @@ -17515,7 +17515,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i32(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17526,7 +17526,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i32( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17551,7 +17551,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i8(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17562,7 +17562,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i8( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17587,7 +17587,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i16(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17598,7 +17598,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i16( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17623,7 +17623,7 @@ ret %1 } -declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i64(,,,,,,, half*, , i64) declare {,,,,,,} @llvm.riscv.vluxseg7.mask.nxv2f16.nxv2i64(,,,,,,, half*, , , i64, i64) define @test_vluxseg7_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17634,7 +17634,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,} @llvm.riscv.vluxseg7.nxv2f16.nxv2i64( undef, undef, undef, undef, undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,} %0, 1 ret %1 } @@ -17659,7 +17659,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i32(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv2f16_nxv2i32(half* %base, %index, i64 %vl) { @@ -17670,7 +17670,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i32( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17696,7 +17696,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i8(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv2f16_nxv2i8(half* %base, %index, i64 %vl) { @@ -17707,7 +17707,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i8( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17733,7 +17733,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i16(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv2f16_nxv2i16(half* %base, %index, i64 %vl) { @@ -17744,7 +17744,7 @@ ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i16( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17770,7 +17770,7 @@ ret %1 } -declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i64(half*, , i64) +declare {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i64(,,,,,,,, half*, , i64) declare {,,,,,,,} @llvm.riscv.vluxseg8.mask.nxv2f16.nxv2i64(,,,,,,,, half*, , , i64, i64) define @test_vluxseg8_nxv2f16_nxv2i64(half* %base, %index, i64 %vl) { @@ -17781,7 +17781,7 @@ ; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i64(half* %base, %index, i64 %vl) + %0 = tail call {,,,,,,,} @llvm.riscv.vluxseg8.nxv2f16.nxv2i64( undef, undef , undef , undef, undef , undef, undef, undef, half* %base, %index, i64 %vl) %1 = extractvalue {,,,,,,,} %0, 1 ret %1 } @@ -17807,7 +17807,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i32(,, float*, , , i64, i64) define @test_vluxseg2_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -17818,7 +17818,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i32( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17836,7 +17836,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i8(,, float*, , , i64, i64) define @test_vluxseg2_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -17847,7 +17847,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i8( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17865,7 +17865,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i64(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i64(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i64(,, float*, , , i64, i64) define @test_vluxseg2_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -17876,7 +17876,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i64( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17894,7 +17894,7 @@ ret %1 } -declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(float*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(,, float*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv4f32.nxv4i16(,, float*, , , i64, i64) define @test_vluxseg2_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -17905,7 +17905,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv4f32.nxv4i16( undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,} %0, 1 ret %1 } @@ -17923,7 +17923,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i32(,,, float*, , , i64, i64) define @test_vluxseg3_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -17934,7 +17934,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i32( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17954,7 +17954,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i8(,,, float*, , , i64, i64) define @test_vluxseg3_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -17965,7 +17965,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i8( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -17985,7 +17985,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i64(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i64(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i64(,,, float*, , , i64, i64) define @test_vluxseg3_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -17996,7 +17996,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i64( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -18015,7 +18015,7 @@ ret %1 } -declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(float*, , i64) +declare {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(,,, float*, , i64) declare {,,} @llvm.riscv.vluxseg3.mask.nxv4f32.nxv4i16(,,, float*, , , i64, i64) define @test_vluxseg3_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -18026,7 +18026,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,,} @llvm.riscv.vluxseg3.nxv4f32.nxv4i16( undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,} %0, 1 ret %1 } @@ -18046,7 +18046,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i32(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv4f32_nxv4i32(float* %base, %index, i64 %vl) { @@ -18057,7 +18057,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i32( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18079,7 +18079,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i8(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv4f32_nxv4i8(float* %base, %index, i64 %vl) { @@ -18090,7 +18090,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i8( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18112,7 +18112,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i64(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i64(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i64(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv4f32_nxv4i64(float* %base, %index, i64 %vl) { @@ -18123,7 +18123,7 @@ ; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i64(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i64( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } @@ -18144,7 +18144,7 @@ ret %1 } -declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(float*, , i64) +declare {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(,,,, float*, , i64) declare {,,,} @llvm.riscv.vluxseg4.mask.nxv4f32.nxv4i16(,,,, float*, , , i64, i64) define @test_vluxseg4_nxv4f32_nxv4i16(float* %base, %index, i64 %vl) { @@ -18155,7 +18155,7 @@ ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: - %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16(float* %base, %index, i64 %vl) + %0 = tail call {,,,} @llvm.riscv.vluxseg4.nxv4f32.nxv4i16( undef, undef, undef, undef, float* %base, %index, i64 %vl) %1 = extractvalue {,,,} %0, 1 ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll @@ -5,7 +5,7 @@ ; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use ; for these intrinsics. -declare {,} @llvm.riscv.vlseg2.nxv16i16(i16* , i64) +declare {,} @llvm.riscv.vlseg2.nxv16i16(,, i16*, i64) declare {,} @llvm.riscv.vlseg2.mask.nxv16i16(,, i16*, , i64, i64) define @test_vlseg2_mask_nxv16i16(i16* %base, %mask) { @@ -17,14 +17,14 @@ ; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 0) + %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16( undef, undef, i16* %base, i64 0) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlseg2.mask.nxv16i16( %1, %1, i16* %base, %mask, i64 0, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64) +declare {,} @llvm.riscv.vlsseg2.nxv16i16(,, i16*, i64, i64) declare {,} @llvm.riscv.vlsseg2.mask.nxv16i16(,, i16*, i64, , i64, i64) define @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, %mask) { @@ -36,13 +36,13 @@ ; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 0) + %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16( undef, undef, i16* %base, i64 %offset, i64 0) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vlsseg2.mask.nxv16i16( %1, %1, i16* %base, i64 %offset, %mask, i64 0, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, , i64) +declare {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(,, i16*, , i64) declare {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i64, i64) define @test_vloxseg2_mask_nxv16i16_nxv16i16(i16* %base, %index, %mask) { @@ -55,14 +55,14 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, %index, i64 0) + %0 = tail call {,} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i64 0) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16( %1, %1, i16* %base, %index, %mask, i64 0, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, , i64) +declare {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(,, i16*, , i64) declare {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(,, i16*, , , i64, i64) define @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, %index, %mask) { @@ -75,14 +75,14 @@ ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: - %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, %index, i64 0) + %0 = tail call {,} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16( undef, undef, i16* %base, %index, i64 0) %1 = extractvalue {,} %0, 0 %2 = tail call {,} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16( %1, %1, i16* %base, %index, %mask, i64 0, i64 1) %3 = extractvalue {,} %2, 1 ret %3 } -declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64) +declare {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(,, i16* , i64) declare {,, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(,, i16*, , i64, i64) define @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) { @@ -94,7 +94,7 @@ ; CHECK-NEXT: sd a0, 0(a1) ; CHECK-NEXT: ret entry: - %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 0) + %0 = tail call {,, i64} @llvm.riscv.vlseg2ff.nxv16i16( undef, undef, i16* %base, i64 0) %1 = extractvalue {,, i64} %0, 1 %2 = extractvalue {,, i64} %0, 2 store i64 %2, i64* %outvl