diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5027,6 +5027,7 @@
 }
 }
 
+let Predicates = [HasNEON] in {
 // If an integer is about to be converted to a floating point value,
 // just load it on the floating point unit.
 // Here are the patterns for 8 and 16-bits to float.
@@ -5113,6 +5114,7 @@
                           (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
 // 64-bits -> double are handled in target specific dag combine:
 // performIntToFpCombine.
+}
 
 //===----------------------------------------------------------------------===//
 // Advanced SIMD three different-sized vector instructions.
@@ -6771,7 +6773,7 @@
                                   dsub)),
                                0),
                              ssub)))>,
-    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
+    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;
 
 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
                           (LDRBroW  GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
@@ -6791,7 +6793,7 @@
                                   INST,
                                   hsub),
                                 0),
-                            ssub)))>, Requires<[NotForCodeSize]>;
+                            ssub)))>, Requires<[NotForCodeSize, HasNEON]>;
 
 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
                            (LDRHroW   GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
@@ -6825,7 +6827,7 @@
                                    dsub)),
                                0),
                              dsub)))>,
-    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
+    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;
 
 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
                            (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
@@ -6844,7 +6846,7 @@
                                   INST,
                                   ssub),
                                0),
-                             dsub)))>, Requires<[NotForCodeSize]>;
+                             dsub)))>, Requires<[NotForCodeSize, HasNEON]>;
 
 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
                            (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
diff --git a/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll b/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
--- a/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
+++ b/llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
@@ -4,20 +4,32 @@
 ; RUN: llc -mtriple=aarch64 -mattr=+neon,+fullfp16 --asm-show-inst < %s | FileCheck %s --check-prefixes=CHECK,NEON-ENABLED
 ; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 --asm-show-inst < %s | FileCheck %s --check-prefixes=CHECK,NEON-DISABLED
 ;; Emit an object file so that verifyPredicates is called (it is not used for ASM output).
-; RUNTODO: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
+; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
 
 define double @ui8_to_double(i8* %i, float* %f) {
-; CHECK-LABEL: ui8_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr b0, [x0] // <MCInst #[[#]] LDRBui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: ui8_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr b0, [x0] // <MCInst #[[#]] LDRBui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: ui8_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrb w8, [x0] // <MCInst #[[#]] LDRBBui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    ucvtf d0, w8 // <MCInst #[[#]] UCVTFUWDri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i8, i8* %i, align 1
   %conv = uitofp i8 %ld to double
@@ -25,17 +37,29 @@
 }
 
 define float @ui8_to_float(i8* %i, float* %f) {
-; CHECK-LABEL: ui8_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr b0, [x0] // <MCInst #[[#]] LDRBui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: ui8_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr b0, [x0] // <MCInst #[[#]] LDRBui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: ui8_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrb w8, [x0] // <MCInst #[[#]] LDRBBui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    ucvtf s0, w8 // <MCInst #[[#]] UCVTFUWSri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i8, i8* %i, align 1
   %conv = uitofp i8 %ld to float
@@ -61,17 +85,29 @@
 }
 
 define double @ui16_to_double(i16* %i, float* %f) {
-; CHECK-LABEL: ui16_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: ui16_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: ui16_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrh w8, [x0] // <MCInst #[[#]] LDRHHui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    ucvtf d0, w8 // <MCInst #[[#]] UCVTFUWDri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = uitofp i16 %ld to double
@@ -79,17 +115,29 @@
 }
 
 define float @ui16_to_float(i16* %i, float* %f) {
-; CHECK-LABEL: ui16_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: ui16_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: ui16_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrh w8, [x0] // <MCInst #[[#]] LDRHHui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    ucvtf s0, w8 // <MCInst #[[#]] UCVTFUWSri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = uitofp i16 %ld to float
@@ -115,17 +163,29 @@
 }
 
 define double @ui32_to_double(i32* %i, float* %f) {
-; CHECK-LABEL: ui32_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr s0, [x0] // <MCInst #[[#]] LDRSui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: ui32_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr s0, [x0] // <MCInst #[[#]] LDRSui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: ui32_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldr w8, [x0] // <MCInst #[[#]] LDRWui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    ucvtf d0, w8 // <MCInst #[[#]] UCVTFUWDri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i32, i32* %i, align 1
   %conv = uitofp i32 %ld to double
@@ -320,21 +380,33 @@
 }
 
 define float @si16_to_float(i16* %i, float* %f) {
-; CHECK-LABEL: si16_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    sshll v0.4s, v0.4h, #0 // <MCInst #[[#]] SSHLLv4i16_shift
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    scvtf s0, s0 // <MCInst #[[#]] SCVTFv1i32
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: si16_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0] // <MCInst #[[#]] LDRHui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    sshll v0.4s, v0.4h, #0 // <MCInst #[[#]] SSHLLv4i16_shift
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    scvtf s0, s0 // <MCInst #[[#]] SCVTFv1i32
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: si16_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrsh w8, [x0] // <MCInst #[[#]] LDRSHWui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    scvtf s0, w8 // <MCInst #[[#]] SCVTFUWSri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = sitofp i16 %ld to float
@@ -360,21 +432,33 @@
 }
 
 define double @si32_to_double(i32* %i, float* %f) {
-; CHECK-LABEL: si32_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr s0, [x0] // <MCInst #[[#]] LDRSui
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    sshll v0.2d, v0.2s, #0 // <MCInst #[[#]] SSHLLv2i32_shift
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Imm:0>>
-; CHECK-NEXT:    scvtf d0, d0 // <MCInst #[[#]] SCVTFv1i64
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
-; CHECK-NEXT:    ret // <MCInst #[[#]] RET
-; CHECK-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-LABEL: si32_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr s0, [x0] // <MCInst #[[#]] LDRSui
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    sshll v0.2d, v0.2s, #0 // <MCInst #[[#]] SSHLLv2i32_shift
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-ENABLED-NEXT:    scvtf d0, d0 // <MCInst #[[#]] SCVTFv1i64
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-ENABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-ENABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+;
+; NEON-DISABLED-LABEL: si32_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldr w8, [x0] // <MCInst #[[#]] LDRWui
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Imm:0>>
+; NEON-DISABLED-NEXT:    scvtf d0, w8 // <MCInst #[[#]] SCVTFUWDri
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
+; NEON-DISABLED-NEXT:    ret // <MCInst #[[#]] RET
+; NEON-DISABLED-NEXT:    // <MCOperand Reg:[[#]]>>
 entry:
   %ld = load i32, i32* %i, align 1
   %conv = sitofp i32 %ld to double