diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
--- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
@@ -548,7 +548,6 @@
 }
 
 define void @br_fcmp_uno(double %a, double %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IFD-LABEL: br_fcmp_uno:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
--- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -549,7 +549,6 @@
 }
 
 define void @br_fcmp_uno(float %a, float %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IF-LABEL: br_fcmp_uno:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
@@ -626,7 +625,6 @@
 ; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
 ; and RISCVInstrInfo::loadRegFromStackSlot
 define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
-; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
 ; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
--- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
@@ -549,7 +549,6 @@
 }
 
 define void @br_fcmp_uno(half %a, half %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IZFH-LABEL: br_fcmp_uno:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
diff --git a/llvm/test/MC/RISCV/rvd-aliases-valid.s b/llvm/test/MC/RISCV/rvd-aliases-valid.s
--- a/llvm/test/MC/RISCV/rvd-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvd-aliases-valid.s
@@ -23,8 +23,12 @@
 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 ##===----------------------------------------------------------------------===##
 
-# TODO fld
-# TODO fsd
+# CHECK-INST: fld ft0, 0(a0)
+# CHECK-ALIAS:  fld ft0, 0(a0)
+fld f0, (a0)
+# CHECK-INST: fsd ft0, 0(a0)
+# CHECK-ALIAS: fsd ft0, 0(a0)
+fsd f0, (a0)
 
 # CHECK-INST: fsgnj.d ft0, ft1, ft1
 # CHECK-ALIAS: fmv.d ft0, ft1
diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s
--- a/llvm/test/MC/RISCV/rvf-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvf-aliases-valid.s
@@ -23,8 +23,12 @@
 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 ##===----------------------------------------------------------------------===##
 
-# TODO flw
-# TODO fsw
+# CHECK-INST: flw ft0, 0(a0)
+# CHECK-ALIAS:  flw ft0, 0(a0)
+flw f0, (a0)
+# CHECK-INST: fsw ft0, 0(a0)
+# CHECK-ALIAS: fsw ft0, 0(a0)
+fsw f0, (a0)
 
 # CHECK-INST: fsgnj.s ft0, ft1, ft1
 # CHECK-ALIAS: fmv.s ft0, ft1