diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -20,204 +20,209 @@
 
 def OtherVT : ValueType<0,   1>;  // "Other" value
 def i1      : ValueType<1,   2>;  // One bit boolean value
-def i8      : ValueType<8,   3>;  // 8-bit integer value
-def i16     : ValueType<16,  4>;  // 16-bit integer value
-def i32     : ValueType<32,  5>;  // 32-bit integer value
-def i64     : ValueType<64,  6>;  // 64-bit integer value
-def i128    : ValueType<128, 7>;  // 128-bit integer value
-
-def bf16    : ValueType<16,   8>;  // 16-bit brain floating point value
-def f16     : ValueType<16,   9>;  // 16-bit floating point value
-def f32     : ValueType<32,  10>;  // 32-bit floating point value
-def f64     : ValueType<64,  11>;  // 64-bit floating point value
-def f80     : ValueType<80,  12>;  // 80-bit floating point value
-def f128    : ValueType<128, 13>;  // 128-bit floating point value
-def ppcf128 : ValueType<128, 14>;  // PPC 128-bit floating point value
-
-def v1i1    : ValueType<1,    15>;  //    1 x i1 vector value
-def v2i1    : ValueType<2,    16>;  //    2 x i1 vector value
-def v4i1    : ValueType<4,    17>;  //    4 x i1 vector value
-def v8i1    : ValueType<8,    18>;  //    8 x i1 vector value
-def v16i1   : ValueType<16,   19>;  //   16 x i1 vector value
-def v32i1   : ValueType<32,   20>;  //   32 x i1 vector value
-def v64i1   : ValueType<64,   21>;  //   64 x i1 vector value
-def v128i1  : ValueType<128,  22>;  //  128 x i1 vector value
-def v256i1  : ValueType<256,  23>;  //  256 x i1 vector value
-def v512i1  : ValueType<512,  24>;  //  512 x i1 vector value
-def v1024i1 : ValueType<1024, 25>;  // 1024 x i1 vector value
-
-def v1i8    : ValueType<8,    26>;  //    1 x i8 vector value
-def v2i8    : ValueType<16,   27>;  //    2 x i8 vector value
-def v4i8    : ValueType<32,   28>;  //    4 x i8 vector value
-def v8i8    : ValueType<64,   29>;  //    8 x i8 vector value
-def v16i8   : ValueType<128,  30>;  //   16 x i8 vector value
-def v32i8   : ValueType<256,  31>;  //   32 x i8 vector value
-def v64i8   : ValueType<512,  32>;  //   64 x i8 vector value
-def v128i8  : ValueType<1024, 33>;  //  128 x i8 vector value
-def v256i8  : ValueType<2048, 34>;  //  256 x i8 vector value
-def v512i8  : ValueType<4096, 35>;  //  512 x i8 vector value
-def v1024i8 : ValueType<8192, 36>;  // 1024 x i8 vector value
-
-def v1i16   : ValueType<16,   37>;  //   1 x i16 vector value
-def v2i16   : ValueType<32,   38>;  //   2 x i16 vector value
-def v3i16   : ValueType<48,   39>;  //   3 x i16 vector value
-def v4i16   : ValueType<64,   40>;  //   4 x i16 vector value
-def v8i16   : ValueType<128,  41>;  //   8 x i16 vector value
-def v16i16  : ValueType<256,  42>;  //  16 x i16 vector value
-def v32i16  : ValueType<512,  43>;  //  32 x i16 vector value
-def v64i16  : ValueType<1024, 44>;  //  64 x i16 vector value
-def v128i16 : ValueType<2048, 45>;  // 128 x i16 vector value
-def v256i16 : ValueType<4096, 46>;  // 256 x i16 vector value
-def v512i16 : ValueType<8192, 47>;  // 512 x i16 vector value
-
-def v1i32    : ValueType<32,    48>;  //    1 x i32 vector value
-def v2i32    : ValueType<64,    49>;  //    2 x i32 vector value
-def v3i32    : ValueType<96,    50>;  //    3 x i32 vector value
-def v4i32    : ValueType<128,   51>;  //    4 x i32 vector value
-def v5i32    : ValueType<160,   52>;  //    5 x i32 vector value
-def v6i32    : ValueType<192,   53>;  //    6 x f32 vector value
-def v7i32    : ValueType<224,   54>;  //    7 x f32 vector value
-def v8i32    : ValueType<256,   55>;  //    8 x i32 vector value
-def v16i32   : ValueType<512,   56>;  //   16 x i32 vector value
-def v32i32   : ValueType<1024,  57>;  //   32 x i32 vector value
-def v64i32   : ValueType<2048,  58>;  //   64 x i32 vector value
-def v128i32  : ValueType<4096,  59>;  //  128 x i32 vector value
-def v256i32  : ValueType<8192,  60>;  //  256 x i32 vector value
-def v512i32  : ValueType<16384, 61>;  //  512 x i32 vector value
-def v1024i32 : ValueType<32768, 62>;  // 1024 x i32 vector value
-def v2048i32 : ValueType<65536, 63>;  // 2048 x i32 vector value
-
-def v1i64   : ValueType<64,    64>;  //   1 x i64 vector value
-def v2i64   : ValueType<128,   65>;  //   2 x i64 vector value
-def v3i64   : ValueType<192,   66>;  //   3 x i64 vector value
-def v4i64   : ValueType<256,   67>;  //   4 x i64 vector value
-def v8i64   : ValueType<512,   68>;  //   8 x i64 vector value
-def v16i64  : ValueType<1024,  69>;  //  16 x i64 vector value
-def v32i64  : ValueType<2048,  70>;  //  32 x i64 vector value
-def v64i64  : ValueType<4096,  71>;  //  64 x i64 vector value
-def v128i64 : ValueType<8192,  72>;  // 128 x i64 vector value
-def v256i64 : ValueType<16384, 73>;  // 256 x i64 vector value
-
-def v1i128 : ValueType<128, 74>;  //  1 x i128 vector value
-
-def v1f16    : ValueType<16,     75>;  //    1 x f16 vector value
-def v2f16    : ValueType<32,     76>;  //    2 x f16 vector value
-def v3f16    : ValueType<48,     77>;  //    3 x f16 vector value
-def v4f16    : ValueType<64,     78>;  //    4 x f16 vector value
-def v8f16    : ValueType<128,    79>;  //    8 x f16 vector value
-def v16f16   : ValueType<256,    80>;  //   16 x f16 vector value
-def v32f16   : ValueType<512,    81>;  //   32 x f16 vector value
-def v64f16   : ValueType<1024,   82>;  //   64 x f16 vector value
-def v128f16  : ValueType<2048,   83>;  //  128 x f16 vector value
-def v256f16  : ValueType<4096,   84>;  //  256 x f16 vector value
-def v512f16  : ValueType<8192,   85>;  //  512 x f16 vector value
-
-def v2bf16   : ValueType<32,     86>;  //    2 x bf16 vector value
-def v3bf16   : ValueType<48,     87>;  //    3 x bf16 vector value
-def v4bf16   : ValueType<64,     88>;  //    4 x bf16 vector value
-def v8bf16   : ValueType<128,    89>;  //    8 x bf16 vector value
-def v16bf16  : ValueType<256,    90>;  //   16 x bf16 vector value
-def v32bf16  : ValueType<512,    91>;  //   32 x bf16 vector value
-def v64bf16  : ValueType<1024,   92>;  //   64 x bf16 vector value
-def v128bf16 : ValueType<2048,   93>;  //  128 x bf16 vector value
-
-def v1f32    : ValueType<32,     94>;  //    1 x f32 vector value
-def v2f32    : ValueType<64,     95>;  //    2 x f32 vector value
-def v3f32    : ValueType<96,     96>;  //    3 x f32 vector value
-def v4f32    : ValueType<128,    97>;  //    4 x f32 vector value
-def v5f32    : ValueType<160,    98>;  //    5 x f32 vector value
-def v6f32    : ValueType<192,    99>;  //    6 x f32 vector value
-def v7f32    : ValueType<224,   100>;  //    7 x f32 vector value
-def v8f32    : ValueType<256,   101>;  //    8 x f32 vector value
-def v16f32   : ValueType<512,   102>;  //   16 x f32 vector value
-def v32f32   : ValueType<1024,  103>;  //   32 x f32 vector value
-def v64f32   : ValueType<2048,  104>;  //   64 x f32 vector value
-def v128f32  : ValueType<4096,  105>;  //  128 x f32 vector value
-def v256f32  : ValueType<8192,  106>;  //  256 x f32 vector value
-def v512f32  : ValueType<16384, 107>;  //  512 x f32 vector value
-def v1024f32 : ValueType<32768, 108>;  // 1024 x f32 vector value
-def v2048f32 : ValueType<65536, 109>;  // 2048 x f32 vector value
-
-def v1f64    : ValueType<64,    110>;  //    1 x f64 vector value
-def v2f64    : ValueType<128,   111>;  //    2 x f64 vector value
-def v3f64    : ValueType<192,   112>;  //    3 x f64 vector value
-def v4f64    : ValueType<256,   113>;  //    4 x f64 vector value
-def v8f64    : ValueType<512,   114>;  //    8 x f64 vector value
-def v16f64   : ValueType<1024,  115>;  //   16 x f64 vector value
-def v32f64   : ValueType<2048,  116>;  //   32 x f64 vector value
-def v64f64   : ValueType<4096,  117>;  //   64 x f64 vector value
-def v128f64  : ValueType<8192,  118>;  //  128 x f64 vector value
-def v256f64  : ValueType<16384, 119>;  //  256 x f64 vector value
-
-def nxv1i1  : ValueType<1,  120>;  // n x  1 x i1  vector value
-def nxv2i1  : ValueType<2,  121>;  // n x  2 x i1  vector value
-def nxv4i1  : ValueType<4,  122>;  // n x  4 x i1  vector value
-def nxv8i1  : ValueType<8,  123>;  // n x  8 x i1  vector value
-def nxv16i1 : ValueType<16, 124>;  // n x 16 x i1  vector value
-def nxv32i1 : ValueType<32, 125>;  // n x 32 x i1  vector value
-def nxv64i1 : ValueType<64, 126>;  // n x 64 x i1  vector value
-
-def nxv1i8  : ValueType<8,   127>;  // n x  1 x i8  vector value
-def nxv2i8  : ValueType<16,  128>;  // n x  2 x i8  vector value
-def nxv4i8  : ValueType<32,  129>;  // n x  4 x i8  vector value
-def nxv8i8  : ValueType<64,  130>;  // n x  8 x i8  vector value
-def nxv16i8 : ValueType<128, 131>;  // n x 16 x i8  vector value
-def nxv32i8 : ValueType<256, 132>;  // n x 32 x i8  vector value
-def nxv64i8 : ValueType<512, 133>;  // n x 64 x i8  vector value
-
-def nxv1i16  : ValueType<16,  134>;  // n x  1 x i16 vector value
-def nxv2i16  : ValueType<32,  135>;  // n x  2 x i16 vector value
-def nxv4i16  : ValueType<64,  136>;  // n x  4 x i16 vector value
-def nxv8i16  : ValueType<128, 137>;  // n x  8 x i16 vector value
-def nxv16i16 : ValueType<256, 138>;  // n x 16 x i16 vector value
-def nxv32i16 : ValueType<512, 139>;  // n x 32 x i16 vector value
-
-def nxv1i32  : ValueType<32,   140>;  // n x  1 x i32 vector value
-def nxv2i32  : ValueType<64,   141>;  // n x  2 x i32 vector value
-def nxv4i32  : ValueType<128,  142>;  // n x  4 x i32 vector value
-def nxv8i32  : ValueType<256,  143>;  // n x  8 x i32 vector value
-def nxv16i32 : ValueType<512,  144>;  // n x 16 x i32 vector value
-def nxv32i32 : ValueType<1024, 145>;  // n x 32 x i32 vector value
-
-def nxv1i64  : ValueType<64,   146>;  // n x  1 x i64 vector value
-def nxv2i64  : ValueType<128,  147>;  // n x  2 x i64 vector value
-def nxv4i64  : ValueType<256,  148>;  // n x  4 x i64 vector value
-def nxv8i64  : ValueType<512,  149>;  // n x  8 x i64 vector value
-def nxv16i64 : ValueType<1024, 150>;  // n x 16 x i64 vector value
-def nxv32i64 : ValueType<2048, 151>;  // n x 32 x i64 vector value
-
-def nxv1f16  : ValueType<16,  152>;  // n x  1 x  f16 vector value
-def nxv2f16  : ValueType<32,  153>;  // n x  2 x  f16 vector value
-def nxv4f16  : ValueType<64,  154>;  // n x  4 x  f16 vector value
-def nxv8f16  : ValueType<128, 155>;  // n x  8 x  f16 vector value
-def nxv16f16 : ValueType<256, 156>;  // n x 16 x  f16 vector value
-def nxv32f16 : ValueType<512, 157>;  // n x 32 x  f16 vector value
-
-def nxv1bf16 : ValueType<16,  158>;  // n x  1 x bf16 vector value
-def nxv2bf16 : ValueType<32,  159>;  // n x  2 x bf16 vector value
-def nxv4bf16 : ValueType<64,  160>;  // n x  4 x bf16 vector value
-def nxv8bf16 : ValueType<128, 161>;  // n x  8 x bf16 vector value
-
-def nxv1f32  : ValueType<32,  162>;  // n x  1 x  f32 vector value
-def nxv2f32  : ValueType<64,  163>;  // n x  2 x  f32 vector value
-def nxv4f32  : ValueType<128, 164>;  // n x  4 x  f32 vector value
-def nxv8f32  : ValueType<256, 165>;  // n x  8 x  f32 vector value
-def nxv16f32 : ValueType<512, 166>;  // n x 16 x  f32 vector value
-
-def nxv1f64  : ValueType<64,  167>;  // n x  1 x  f64 vector value
-def nxv2f64  : ValueType<128, 168>;  // n x  2 x  f64 vector value
-def nxv4f64  : ValueType<256, 169>;  // n x  4 x  f64 vector value
-def nxv8f64  : ValueType<512, 170>;  // n x  8 x  f64 vector value
-
-def x86mmx    : ValueType<64,   171>;  // X86 MMX value
-def FlagVT    : ValueType<0,    172>;  // Pre-RA sched glue
-def isVoid    : ValueType<0,    173>;  // Produces no value
-def untyped   : ValueType<8,    174>;  // Produces an untyped value
-def funcref   : ValueType<0,    175>;  // WebAssembly's funcref type
-def externref : ValueType<0,    176>;  // WebAssembly's externref type
-def x86amx    : ValueType<8192, 177>;  // X86 AMX value
-def i64x8     : ValueType<512,  178>;  // 8 Consecutive GPRs (AArch64)
-
+def i2      : ValueType<2,   3>;  // 2-bit integer value
+def i4      : ValueType<4,   4>;  // 4-bit integer value
+def i8      : ValueType<8,   5>;  // 8-bit integer value
+def i16     : ValueType<16,  6>;  // 16-bit integer value
+def i32     : ValueType<32,  7>;  // 32-bit integer value
+def i64     : ValueType<64,  8>;  // 64-bit integer value
+def i128    : ValueType<128, 9>;  // 128-bit integer value
+
+def bf16    : ValueType<16,  10>;  // 16-bit brain floating point value
+def f16     : ValueType<16,  11>;  // 16-bit floating point value
+def f32     : ValueType<32,  12>;  // 32-bit floating point value
+def f64     : ValueType<64,  13>;  // 64-bit floating point value
+def f80     : ValueType<80,  14>;  // 80-bit floating point value
+def f128    : ValueType<128, 15>;  // 128-bit floating point value
+def ppcf128 : ValueType<128, 16>;  // PPC 128-bit floating point value
+
+def v1i1    : ValueType<1,    17>;  //    1 x i1 vector value
+def v2i1    : ValueType<2,    18>;  //    2 x i1 vector value
+def v4i1    : ValueType<4,    19>;  //    4 x i1 vector value
+def v8i1    : ValueType<8,    20>;  //    8 x i1 vector value
+def v16i1   : ValueType<16,   21>;  //   16 x i1 vector value
+def v32i1   : ValueType<32,   22>;  //   32 x i1 vector value
+def v64i1   : ValueType<64,   23>;  //   64 x i1 vector value
+def v128i1  : ValueType<128,  24>;  //  128 x i1 vector value
+def v256i1  : ValueType<256,  25>;  //  256 x i1 vector value
+def v512i1  : ValueType<512,  26>;  //  512 x i1 vector value
+def v1024i1 : ValueType<1024, 27>;  // 1024 x i1 vector value
+
+def v128i2  : ValueType<256,  28>;   //  128 x i2 vector value
+
+def v64i4   : ValueType<256,  29>;   //   64 x i4 vector value
+
+def v1i8    : ValueType<8,    30>;  //    1 x i8 vector value
+def v2i8    : ValueType<16,   31>;  //    2 x i8 vector value
+def v4i8    : ValueType<32,   32>;  //    4 x i8 vector value
+def v8i8    : ValueType<64,   33>;  //    8 x i8 vector value
+def v16i8   : ValueType<128,  34>;  //   16 x i8 vector value
+def v32i8   : ValueType<256,  35>;  //   32 x i8 vector value
+def v64i8   : ValueType<512,  36>;  //   64 x i8 vector value
+def v128i8  : ValueType<1024, 37>;  //  128 x i8 vector value
+def v256i8  : ValueType<2048, 38>;  //  256 x i8 vector value
+def v512i8  : ValueType<4096, 39>;  //  512 x i8 vector value
+def v1024i8 : ValueType<8192, 40>;  // 1024 x i8 vector value
+
+def v1i16   : ValueType<16,   41>;  //   1 x i16 vector value
+def v2i16   : ValueType<32,   42>;  //   2 x i16 vector value
+def v3i16   : ValueType<48,   43>;  //   3 x i16 vector value
+def v4i16   : ValueType<64,   44>;  //   4 x i16 vector value
+def v8i16   : ValueType<128,  45>;  //   8 x i16 vector value
+def v16i16  : ValueType<256,  46>;  //  16 x i16 vector value
+def v32i16  : ValueType<512,  47>;  //  32 x i16 vector value
+def v64i16  : ValueType<1024, 48>;  //  64 x i16 vector value
+def v128i16 : ValueType<2048, 49>;  // 128 x i16 vector value
+def v256i16 : ValueType<4096, 50>;  // 256 x i16 vector value
+def v512i16 : ValueType<8192, 51>;  // 512 x i16 vector value
+
+def v1i32    : ValueType<32,    52>;  //    1 x i32 vector value
+def v2i32    : ValueType<64,    53>;  //    2 x i32 vector value
+def v3i32    : ValueType<96,    54>;  //    3 x i32 vector value
+def v4i32    : ValueType<128,   55>;  //    4 x i32 vector value
+def v5i32    : ValueType<160,   56>;  //    5 x i32 vector value
+def v6i32    : ValueType<192,   57>;  //    6 x f32 vector value
+def v7i32    : ValueType<224,   58>;  //    7 x f32 vector value
+def v8i32    : ValueType<256,   59>;  //    8 x i32 vector value
+def v16i32   : ValueType<512,   60>;  //   16 x i32 vector value
+def v32i32   : ValueType<1024,  61>;  //   32 x i32 vector value
+def v64i32   : ValueType<2048,  62>;  //   64 x i32 vector value
+def v128i32  : ValueType<4096,  63>;  //  128 x i32 vector value
+def v256i32  : ValueType<8192,  64>;  //  256 x i32 vector value
+def v512i32  : ValueType<16384, 65>;  //  512 x i32 vector value
+def v1024i32 : ValueType<32768, 66>;  // 1024 x i32 vector value
+def v2048i32 : ValueType<65536, 67>;  // 2048 x i32 vector value
+
+def v1i64   : ValueType<64,    68>;  //   1 x i64 vector value
+def v2i64   : ValueType<128,   69>;  //   2 x i64 vector value
+def v3i64   : ValueType<192,   70>;  //   3 x i64 vector value
+def v4i64   : ValueType<256,   71>;  //   4 x i64 vector value
+def v8i64   : ValueType<512,   72>;  //   8 x i64 vector value
+def v16i64  : ValueType<1024,  73>;  //  16 x i64 vector value
+def v32i64  : ValueType<2048,  74>;  //  32 x i64 vector value
+def v64i64  : ValueType<4096,  75>;  //  64 x i64 vector value
+def v128i64 : ValueType<8192,  76>;  // 128 x i64 vector value
+def v256i64 : ValueType<16384, 77>;  // 256 x i64 vector value
+
+def v1i128 : ValueType<128, 78>;  //  1 x i128 vector value
+
+def v1f16    : ValueType<16,     79>;  //    1 x f16 vector value
+def v2f16    : ValueType<32,     80>;  //    2 x f16 vector value
+def v3f16    : ValueType<48,     81>;  //    3 x f16 vector value
+def v4f16    : ValueType<64,     82>;  //    4 x f16 vector value
+def v8f16    : ValueType<128,    83>;  //    8 x f16 vector value
+def v16f16   : ValueType<256,    84>;  //   16 x f16 vector value
+def v32f16   : ValueType<512,    85>;  //   32 x f16 vector value
+def v64f16   : ValueType<1024,   86>;  //   64 x f16 vector value
+def v128f16  : ValueType<2048,   87>;  //  128 x f16 vector value
+def v256f16  : ValueType<4096,   88>;  //  256 x f16 vector value
+def v512f16  : ValueType<8192,   89>;  //  512 x f16 vector value
+
+def v2bf16   : ValueType<32,     90>;  //    2 x bf16 vector value
+def v3bf16   : ValueType<48,     91>;  //    3 x bf16 vector value
+def v4bf16   : ValueType<64,     92>;  //    4 x bf16 vector value
+def v8bf16   : ValueType<128,    93>;  //    8 x bf16 vector value
+def v16bf16  : ValueType<256,    94>;  //   16 x bf16 vector value
+def v32bf16  : ValueType<512,    95>;  //   32 x bf16 vector value
+def v64bf16  : ValueType<1024,   96>;  //   64 x bf16 vector value
+def v128bf16 : ValueType<2048,   97>;  //  128 x bf16 vector value
+
+def v1f32    : ValueType<32,     98>;  //    1 x f32 vector value
+def v2f32    : ValueType<64,     99>;  //    2 x f32 vector value
+def v3f32    : ValueType<96,    100>;  //    3 x f32 vector value
+def v4f32    : ValueType<128,   101>;  //    4 x f32 vector value
+def v5f32    : ValueType<160,   102>;  //    5 x f32 vector value
+def v6f32    : ValueType<192,   103>;  //    6 x f32 vector value
+def v7f32    : ValueType<224,   104>;  //    7 x f32 vector value
+def v8f32    : ValueType<256,   105>;  //    8 x f32 vector value
+def v16f32   : ValueType<512,   106>;  //   16 x f32 vector value
+def v32f32   : ValueType<1024,  107>;  //   32 x f32 vector value
+def v64f32   : ValueType<2048,  108>;  //   64 x f32 vector value
+def v128f32  : ValueType<4096,  109>;  //  128 x f32 vector value
+def v256f32  : ValueType<8192,  110>;  //  256 x f32 vector value
+def v512f32  : ValueType<16384, 111>;  //  512 x f32 vector value
+def v1024f32 : ValueType<32768, 112>;  // 1024 x f32 vector value
+def v2048f32 : ValueType<65536, 113>;  // 2048 x f32 vector value
+
+def v1f64    : ValueType<64,    114>;  //    1 x f64 vector value
+def v2f64    : ValueType<128,   115>;  //    2 x f64 vector value
+def v3f64    : ValueType<192,   116>;  //    3 x f64 vector value
+def v4f64    : ValueType<256,   117>;  //    4 x f64 vector value
+def v8f64    : ValueType<512,   118>;  //    8 x f64 vector value
+def v16f64   : ValueType<1024,  119>;  //   16 x f64 vector value
+def v32f64   : ValueType<2048,  120>;  //   32 x f64 vector value
+def v64f64   : ValueType<4096,  121>;  //   64 x f64 vector value
+def v128f64  : ValueType<8192,  122>;  //  128 x f64 vector value
+def v256f64  : ValueType<16384, 123>;  //  256 x f64 vector value
+
+def nxv1i1  : ValueType<1,  124>;  // n x  1 x i1  vector value
+def nxv2i1  : ValueType<2,  125>;  // n x  2 x i1  vector value
+def nxv4i1  : ValueType<4,  126>;  // n x  4 x i1  vector value
+def nxv8i1  : ValueType<8,  127>;  // n x  8 x i1  vector value
+def nxv16i1 : ValueType<16, 128>;  // n x 16 x i1  vector value
+def nxv32i1 : ValueType<32, 129>;  // n x 32 x i1  vector value
+def nxv64i1 : ValueType<64, 130>;  // n x 64 x i1  vector value
+
+def nxv1i8  : ValueType<8,   131>;  // n x  1 x i8  vector value
+def nxv2i8  : ValueType<16,  132>;  // n x  2 x i8  vector value
+def nxv4i8  : ValueType<32,  133>;  // n x  4 x i8  vector value
+def nxv8i8  : ValueType<64,  134>;  // n x  8 x i8  vector value
+def nxv16i8 : ValueType<128, 135>;  // n x 16 x i8  vector value
+def nxv32i8 : ValueType<256, 136>;  // n x 32 x i8  vector value
+def nxv64i8 : ValueType<512, 137>;  // n x 64 x i8  vector value
+
+def nxv1i16  : ValueType<16,  138>;  // n x  1 x i16 vector value
+def nxv2i16  : ValueType<32,  139>;  // n x  2 x i16 vector value
+def nxv4i16  : ValueType<64,  140>;  // n x  4 x i16 vector value
+def nxv8i16  : ValueType<128, 141>;  // n x  8 x i16 vector value
+def nxv16i16 : ValueType<256, 142>;  // n x 16 x i16 vector value
+def nxv32i16 : ValueType<512, 143>;  // n x 32 x i16 vector value
+
+def nxv1i32  : ValueType<32,   144>;  // n x  1 x i32 vector value
+def nxv2i32  : ValueType<64,   145>;  // n x  2 x i32 vector value
+def nxv4i32  : ValueType<128,  146>;  // n x  4 x i32 vector value
+def nxv8i32  : ValueType<256,  147>;  // n x  8 x i32 vector value
+def nxv16i32 : ValueType<512,  148>;  // n x 16 x i32 vector value
+def nxv32i32 : ValueType<1024, 149>;  // n x 32 x i32 vector value
+
+def nxv1i64  : ValueType<64,   150>;  // n x  1 x i64 vector value
+def nxv2i64  : ValueType<128,  151>;  // n x  2 x i64 vector value
+def nxv4i64  : ValueType<256,  152>;  // n x  4 x i64 vector value
+def nxv8i64  : ValueType<512,  153>;  // n x  8 x i64 vector value
+def nxv16i64 : ValueType<1024, 154>;  // n x 16 x i64 vector value
+def nxv32i64 : ValueType<2048, 155>;  // n x 32 x i64 vector value
+
+def nxv1f16  : ValueType<16,  156>;  // n x  1 x  f16 vector value
+def nxv2f16  : ValueType<32,  157>;  // n x  2 x  f16 vector value
+def nxv4f16  : ValueType<64,  158>;  // n x  4 x  f16 vector value
+def nxv8f16  : ValueType<128, 159>;  // n x  8 x  f16 vector value
+def nxv16f16 : ValueType<256, 160>;  // n x 16 x  f16 vector value
+def nxv32f16 : ValueType<512, 161>;  // n x 32 x  f16 vector value
+
+def nxv1bf16 : ValueType<16,  162>;  // n x  1 x bf16 vector value
+def nxv2bf16 : ValueType<32,  163>;  // n x  2 x bf16 vector value
+def nxv4bf16 : ValueType<64,  164>;  // n x  4 x bf16 vector value
+def nxv8bf16 : ValueType<128, 165>;  // n x  8 x bf16 vector value
+
+def nxv1f32  : ValueType<32,  166>;  // n x  1 x  f32 vector value
+def nxv2f32  : ValueType<64,  167>;  // n x  2 x  f32 vector value
+def nxv4f32  : ValueType<128, 168>;  // n x  4 x  f32 vector value
+def nxv8f32  : ValueType<256, 169>;  // n x  8 x  f32 vector value
+def nxv16f32 : ValueType<512, 170>;  // n x 16 x  f32 vector value
+
+def nxv1f64  : ValueType<64,  171>;  // n x  1 x  f64 vector value
+def nxv2f64  : ValueType<128, 172>;  // n x  2 x  f64 vector value
+def nxv4f64  : ValueType<256, 173>;  // n x  4 x  f64 vector value
+def nxv8f64  : ValueType<512, 174>;  // n x  8 x  f64 vector value
+
+def x86mmx    : ValueType<64,   175>;  // X86 MMX value
+def FlagVT    : ValueType<0,    176>;  // Pre-RA sched glue
+def isVoid    : ValueType<0,    177>;  // Produces no value
+def untyped   : ValueType<8,    178>;  // Produces an untyped value
+def funcref   : ValueType<0,    179>;  // WebAssembly's funcref type
+def externref : ValueType<0,    180>;  // WebAssembly's externref type
+def x86amx    : ValueType<8192, 181>;  // X86 AMX value
+def i64x8     : ValueType<512,  182>;  // 8 Consecutive GPRs (AArch64)
 
 def token      : ValueType<0, 248>;  // TokenTy
 def MetadataVT : ValueType<0, 249>;  // Metadata
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -41,143 +41,149 @@
       // ValueTypes.td as well!
       Other          =   1,   // This is a non-standard value
       i1             =   2,   // This is a 1 bit integer value
-      i8             =   3,   // This is an 8 bit integer value
-      i16            =   4,   // This is a 16 bit integer value
-      i32            =   5,   // This is a 32 bit integer value
-      i64            =   6,   // This is a 64 bit integer value
-      i128           =   7,   // This is a 128 bit integer value
+      i2             =   3,   // This is a 2 bit integer value
+      i4             =   4,   // This is a 4 bit integer value
+      i8             =   5,   // This is an 8 bit integer value
+      i16            =   6,   // This is a 16 bit integer value
+      i32            =   7,   // This is a 32 bit integer value
+      i64            =   8,   // This is a 64 bit integer value
+      i128           =   9,   // This is a 128 bit integer value
 
       FIRST_INTEGER_VALUETYPE = i1,
       LAST_INTEGER_VALUETYPE  = i128,
 
-      bf16           =   8,   // This is a 16 bit brain floating point value
-      f16            =   9,   // This is a 16 bit floating point value
-      f32            =  10,   // This is a 32 bit floating point value
-      f64            =  11,   // This is a 64 bit floating point value
-      f80            =  12,   // This is a 80 bit floating point value
-      f128           =  13,   // This is a 128 bit floating point value
-      ppcf128        =  14,   // This is a PPC 128-bit floating point value
+      bf16           =  10,   // This is a 16 bit brain floating point value
+      f16            =  11,   // This is a 16 bit floating point value
+      f32            =  12,   // This is a 32 bit floating point value
+      f64            =  13,   // This is a 64 bit floating point value
+      f80            =  14,   // This is a 80 bit floating point value
+      f128           =  15,   // This is a 128 bit floating point value
+      ppcf128        =  16,   // This is a PPC 128-bit floating point value
 
       FIRST_FP_VALUETYPE = bf16,
       LAST_FP_VALUETYPE  = ppcf128,
 
-      v1i1           =  15,   //    1 x i1
-      v2i1           =  16,   //    2 x i1
-      v4i1           =  17,   //    4 x i1
-      v8i1           =  18,   //    8 x i1
-      v16i1          =  19,   //   16 x i1
-      v32i1          =  20,   //   32 x i1
-      v64i1          =  21,   //   64 x i1
-      v128i1         =  22,   //  128 x i1
-      v256i1         =  23,   //  256 x i1
-      v512i1         =  24,   //  512 x i1
-      v1024i1        =  25,   // 1024 x i1
-
-      v1i8           =  26,   //    1 x i8
-      v2i8           =  27,   //    2 x i8
-      v4i8           =  28,   //    4 x i8
-      v8i8           =  29,   //    8 x i8
-      v16i8          =  30,   //   16 x i8
-      v32i8          =  31,   //   32 x i8
-      v64i8          =  32,   //   64 x i8
-      v128i8         =  33,   //  128 x i8
-      v256i8         =  34,   //  256 x i8
-      v512i8         =  35,   //  512 x i8
-      v1024i8        =  36,   // 1024 x i8
-
-      v1i16          =  37,   //   1 x i16
-      v2i16          =  38,   //   2 x i16
-      v3i16          =  39,   //   3 x i16
-      v4i16          =  40,   //   4 x i16
-      v8i16          =  41,   //   8 x i16
-      v16i16         =  42,   //  16 x i16
-      v32i16         =  43,   //  32 x i16
-      v64i16         =  44,   //  64 x i16
-      v128i16        =  45,   // 128 x i16
-      v256i16        =  46,   // 256 x i16
-      v512i16        =  47,   // 512 x i16
-
-      v1i32          =  48,   //    1 x i32
-      v2i32          =  49,   //    2 x i32
-      v3i32          =  50,   //    3 x i32
-      v4i32          =  51,   //    4 x i32
-      v5i32          =  52,   //    5 x i32
-      v6i32          =  53,   //    6 x i32
-      v7i32          =  54,   //    7 x i32
-      v8i32          =  55,   //    8 x i32
-      v16i32         =  56,   //   16 x i32
-      v32i32         =  57,   //   32 x i32
-      v64i32         =  58,   //   64 x i32
-      v128i32        =  59,   //  128 x i32
-      v256i32        =  60,   //  256 x i32
-      v512i32        =  61,   //  512 x i32
-      v1024i32       =  62,   // 1024 x i32
-      v2048i32       =  63,   // 2048 x i32
-
-      v1i64          =  64,   //   1 x i64
-      v2i64          =  65,   //   2 x i64
-      v3i64          =  66,   //   3 x i64
-      v4i64          =  67,   //   4 x i64
-      v8i64          =  68,   //   8 x i64
-      v16i64         =  69,   //  16 x i64
-      v32i64         =  70,   //  32 x i64
-      v64i64         =  71,   //  64 x i64
-      v128i64        =  72,   // 128 x i64
-      v256i64        =  73,   // 256 x i64
-
-      v1i128         =  74,   //  1 x i128
+      v1i1           =  17,   //    1 x i1
+      v2i1           =  18,   //    2 x i1
+      v4i1           =  19,   //    4 x i1
+      v8i1           =  20,   //    8 x i1
+      v16i1          =  21,   //   16 x i1
+      v32i1          =  22,   //   32 x i1
+      v64i1          =  23,   //   64 x i1
+      v128i1         =  24,   //  128 x i1
+      v256i1         =  25,   //  256 x i1
+      v512i1         =  26,   //  512 x i1
+      v1024i1        =  27,   // 1024 x i1
+
+      v128i2         =  28,   //  128 x i2
+
+      v64i4          =  29,   //   64 x i4
+
+      v1i8           =  30,   //    1 x i8
+      v2i8           =  31,   //    2 x i8
+      v4i8           =  32,   //    4 x i8
+      v8i8           =  33,   //    8 x i8
+      v16i8          =  34,   //   16 x i8
+      v32i8          =  35,   //   32 x i8
+      v64i8          =  36,   //   64 x i8
+      v128i8         =  37,   //  128 x i8
+      v256i8         =  38,   //  256 x i8
+      v512i8         =  39,   //  512 x i8
+      v1024i8        =  40,   // 1024 x i8
+
+      v1i16          =  41,   //   1 x i16
+      v2i16          =  42,   //   2 x i16
+      v3i16          =  43,   //   3 x i16
+      v4i16          =  44,   //   4 x i16
+      v8i16          =  45,   //   8 x i16
+      v16i16         =  46,   //  16 x i16
+      v32i16         =  47,   //  32 x i16
+      v64i16         =  48,   //  64 x i16
+      v128i16        =  49,   // 128 x i16
+      v256i16        =  50,   // 256 x i16
+      v512i16        =  51,   // 512 x i16
+
+      v1i32          =  52,   //    1 x i32
+      v2i32          =  53,   //    2 x i32
+      v3i32          =  54,   //    3 x i32
+      v4i32          =  55,   //    4 x i32
+      v5i32          =  56,   //    5 x i32
+      v6i32          =  57,   //    6 x i32
+      v7i32          =  58,   //    7 x i32
+      v8i32          =  59,   //    8 x i32
+      v16i32         =  60,   //   16 x i32
+      v32i32         =  61,   //   32 x i32
+      v64i32         =  62,   //   64 x i32
+      v128i32        =  63,   //  128 x i32
+      v256i32        =  64,   //  256 x i32
+      v512i32        =  65,   //  512 x i32
+      v1024i32       =  66,   // 1024 x i32
+      v2048i32       =  67,   // 2048 x i32
+
+      v1i64          =  68,   //   1 x i64
+      v2i64          =  69,   //   2 x i64
+      v3i64          =  70,   //   3 x i64
+      v4i64          =  71,   //   4 x i64
+      v8i64          =  72,   //   8 x i64
+      v16i64         =  73,   //  16 x i64
+      v32i64         =  74,   //  32 x i64
+      v64i64         =  75,   //  64 x i64
+      v128i64        =  76,   // 128 x i64
+      v256i64        =  77,   // 256 x i64
+
+      v1i128         =  78,   //  1 x i128
 
       FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
       LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
 
-      v1f16          =  75,   //    1 x f16
-      v2f16          =  76,   //    2 x f16
-      v3f16          =  77,   //    3 x f16
-      v4f16          =  78,   //    4 x f16
-      v8f16          =  79,   //    8 x f16
-      v16f16         =  80,   //   16 x f16
-      v32f16         =  81,   //   32 x f16
-      v64f16         =  82,   //   64 x f16
-      v128f16        =  83,   //  128 x f16
-      v256f16        =  84,   //  256 x f16
-      v512f16        =  85,   //  256 x f16
-
-      v2bf16         =  86,   //    2 x bf16
-      v3bf16         =  87,   //    3 x bf16
-      v4bf16         =  88,   //    4 x bf16
-      v8bf16         =  89,   //    8 x bf16
-      v16bf16        =  90,   //   16 x bf16
-      v32bf16        =  91,   //   32 x bf16
-      v64bf16        =  92,   //   64 x bf16
-      v128bf16       =  93,   //  128 x bf16
-
-      v1f32          =  94,   //    1 x f32
-      v2f32          =  95,   //    2 x f32
-      v3f32          =  96,   //    3 x f32
-      v4f32          =  97,   //    4 x f32
-      v5f32          =  98,   //    5 x f32
-      v6f32          =  99,   //    6 x f32
-      v7f32          = 100,   //    7 x f32
-      v8f32          = 101,   //    8 x f32
-      v16f32         = 102,   //   16 x f32
-      v32f32         = 103,   //   32 x f32
-      v64f32         = 104,   //   64 x f32
-      v128f32        = 105,   //  128 x f32
-      v256f32        = 106,   //  256 x f32
-      v512f32        = 107,   //  512 x f32
-      v1024f32       = 108,   // 1024 x f32
-      v2048f32       = 109,   // 2048 x f32
-
-      v1f64          = 110,   //    1 x f64
-      v2f64          = 111,   //    2 x f64
-      v3f64          = 112,   //    3 x f64
-      v4f64          = 113,   //    4 x f64
-      v8f64          = 114,   //    8 x f64
-      v16f64         = 115,   //   16 x f64
-      v32f64         = 116,   //   32 x f64
-      v64f64         = 117,   //   64 x f64
-      v128f64        = 118,   //  128 x f64
-      v256f64        = 119,   //  256 x f64
+      v1f16          =  79,   //    1 x f16
+      v2f16          =  80,   //    2 x f16
+      v3f16          =  81,   //    3 x f16
+      v4f16          =  82,   //    4 x f16
+      v8f16          =  83,   //    8 x f16
+      v16f16         =  84,   //   16 x f16
+      v32f16         =  85,   //   32 x f16
+      v64f16         =  86,   //   64 x f16
+      v128f16        =  87,   //  128 x f16
+      v256f16        =  88,   //  256 x f16
+      v512f16        =  89,   //  256 x f16
+
+      v2bf16         =  90,   //    2 x bf16
+      v3bf16         =  91,   //    3 x bf16
+      v4bf16         =  92,   //    4 x bf16
+      v8bf16         =  93,   //    8 x bf16
+      v16bf16        =  94,   //   16 x bf16
+      v32bf16        =  95,   //   32 x bf16
+      v64bf16        =  96,   //   64 x bf16
+      v128bf16       =  97,   //  128 x bf16
+
+      v1f32          =  98,   //    1 x f32
+      v2f32          =  99,   //    2 x f32
+      v3f32          = 100,   //    3 x f32
+      v4f32          = 101,   //    4 x f32
+      v5f32          = 102,   //    5 x f32
+      v6f32          = 103,   //    6 x f32
+      v7f32          = 104,   //    7 x f32
+      v8f32          = 105,   //    8 x f32
+      v16f32         = 106,   //   16 x f32
+      v32f32         = 107,   //   32 x f32
+      v64f32         = 108,   //   64 x f32
+      v128f32        = 109,   //  128 x f32
+      v256f32        = 110,   //  256 x f32
+      v512f32        = 111,   //  512 x f32
+      v1024f32       = 112,   // 1024 x f32
+      v2048f32       = 113,   // 2048 x f32
+
+      v1f64          = 114,   //    1 x f64
+      v2f64          = 115,   //    2 x f64
+      v3f64          = 116,   //    3 x f64
+      v4f64          = 117,   //    4 x f64
+      v8f64          = 118,   //    8 x f64
+      v16f64         = 119,   //   16 x f64
+      v32f64         = 120,   //   32 x f64
+      v64f64         = 121,   //   64 x f64
+      v128f64        = 122,   //  128 x f64
+      v256f64        = 123,   //  256 x f64
 
       FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
       LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
@@ -185,68 +191,68 @@
       FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
       LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
 
-      nxv1i1         = 120,   // n x  1 x i1
-      nxv2i1         = 121,   // n x  2 x i1
-      nxv4i1         = 122,   // n x  4 x i1
-      nxv8i1         = 123,   // n x  8 x i1
-      nxv16i1        = 124,   // n x 16 x i1
-      nxv32i1        = 125,   // n x 32 x i1
-      nxv64i1        = 126,   // n x 64 x i1
-
-      nxv1i8         = 127,   // n x  1 x i8
-      nxv2i8         = 128,   // n x  2 x i8
-      nxv4i8         = 129,   // n x  4 x i8
-      nxv8i8         = 130,   // n x  8 x i8
-      nxv16i8        = 131,   // n x 16 x i8
-      nxv32i8        = 132,   // n x 32 x i8
-      nxv64i8        = 133,   // n x 64 x i8
-
-      nxv1i16        = 134,  // n x  1 x i16
-      nxv2i16        = 135,  // n x  2 x i16
-      nxv4i16        = 136,  // n x  4 x i16
-      nxv8i16        = 137,  // n x  8 x i16
-      nxv16i16       = 138,  // n x 16 x i16
-      nxv32i16       = 139,  // n x 32 x i16
-
-      nxv1i32        = 140,  // n x  1 x i32
-      nxv2i32        = 141,  // n x  2 x i32
-      nxv4i32        = 142,  // n x  4 x i32
-      nxv8i32        = 143,  // n x  8 x i32
-      nxv16i32       = 144,  // n x 16 x i32
-      nxv32i32       = 145,  // n x 32 x i32
-
-      nxv1i64        = 146,  // n x  1 x i64
-      nxv2i64        = 147,  // n x  2 x i64
-      nxv4i64        = 148,  // n x  4 x i64
-      nxv8i64        = 149,  // n x  8 x i64
-      nxv16i64       = 150,  // n x 16 x i64
-      nxv32i64       = 151,  // n x 32 x i64
+      nxv1i1         = 124,   // n x  1 x i1
+      nxv2i1         = 125,   // n x  2 x i1
+      nxv4i1         = 126,   // n x  4 x i1
+      nxv8i1         = 127,   // n x  8 x i1
+      nxv16i1        = 128,   // n x 16 x i1
+      nxv32i1        = 129,   // n x 32 x i1
+      nxv64i1        = 130,   // n x 64 x i1
+
+      nxv1i8         = 131,   // n x  1 x i8
+      nxv2i8         = 132,   // n x  2 x i8
+      nxv4i8         = 133,   // n x  4 x i8
+      nxv8i8         = 134,   // n x  8 x i8
+      nxv16i8        = 135,   // n x 16 x i8
+      nxv32i8        = 136,   // n x 32 x i8
+      nxv64i8        = 137,   // n x 64 x i8
+
+      nxv1i16        = 138,  // n x  1 x i16
+      nxv2i16        = 139,  // n x  2 x i16
+      nxv4i16        = 140,  // n x  4 x i16
+      nxv8i16        = 141,  // n x  8 x i16
+      nxv16i16       = 142,  // n x 16 x i16
+      nxv32i16       = 143,  // n x 32 x i16
+
+      nxv1i32        = 144,  // n x  1 x i32
+      nxv2i32        = 145,  // n x  2 x i32
+      nxv4i32        = 146,  // n x  4 x i32
+      nxv8i32        = 147,  // n x  8 x i32
+      nxv16i32       = 148,  // n x 16 x i32
+      nxv32i32       = 149,  // n x 32 x i32
+
+      nxv1i64        = 150,  // n x  1 x i64
+      nxv2i64        = 151,  // n x  2 x i64
+      nxv4i64        = 152,  // n x  4 x i64
+      nxv8i64        = 153,  // n x  8 x i64
+      nxv16i64       = 154,  // n x 16 x i64
+      nxv32i64       = 155,  // n x 32 x i64
 
       FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
       LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
 
-      nxv1f16        = 152,  // n x  1 x f16
-      nxv2f16        = 153,  // n x  2 x f16
-      nxv4f16        = 154,  // n x  4 x f16
-      nxv8f16        = 155,  // n x  8 x f16
-      nxv16f16       = 156,  // n x 16 x f16
-      nxv32f16       = 157,  // n x 32 x f16
-
-      nxv1bf16       = 158,  // n x  1 x bf16
-      nxv2bf16       = 159,  // n x  2 x bf16
-      nxv4bf16       = 160,  // n x  4 x bf16
-      nxv8bf16       = 161,  // n x  8 x bf16
-
-      nxv1f32        = 162,  // n x  1 x f32
-      nxv2f32        = 163,  // n x  2 x f32
-      nxv4f32        = 164,  // n x  4 x f32
-      nxv8f32        = 165,  // n x  8 x f32
-      nxv16f32       = 166,  // n x 16 x f32
-
-      nxv1f64        = 167,  // n x  1 x f64
-      nxv2f64        = 168,  // n x  2 x f64
-      nxv4f64        = 169,  // n x  4 x f64
-      nxv8f64        = 170,  // n x  8 x f64
+      nxv1f16        = 156,  // n x  1 x f16
+      nxv2f16        = 157,  // n x  2 x f16
+      nxv4f16        = 158,  // n x  4 x f16
+      nxv8f16        = 159,  // n x  8 x f16
+      nxv16f16       = 160,  // n x 16 x f16
+      nxv32f16       = 161,  // n x 32 x f16
+
+      nxv1bf16       = 162,  // n x  1 x bf16
+      nxv2bf16       = 163,  // n x  2 x bf16
+      nxv4bf16       = 164,  // n x  4 x bf16
+      nxv8bf16       = 165,  // n x  8 x bf16
+
+      nxv1f32        = 166,  // n x  1 x f32
+      nxv2f32        = 167,  // n x  2 x f32
+      nxv4f32        = 168,  // n x  4 x f32
+      nxv8f32        = 169,  // n x  8 x f32
+      nxv16f32       = 170,  // n x 16 x f32
+
+      nxv1f64        = 171,  // n x  1 x f64
+      nxv2f64        = 172,  // n x  2 x f64
+      nxv4f64        = 173,  // n x  4 x f64
+      nxv8f64        = 174,  // n x  8 x f64
 
       FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
       LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
@@ -257,20 +263,20 @@
       FIRST_VECTOR_VALUETYPE = v1i1,
       LAST_VECTOR_VALUETYPE  = nxv8f64,
 
-      x86mmx         = 171,    // This is an X86 MMX value
+      x86mmx         = 175,    // This is an X86 MMX value
 
-      Glue           = 172,    // This glues nodes together during pre-RA sched
+      Glue           = 176,    // This glues nodes together during pre-RA sched
 
-      isVoid         = 173,    // This has no value
+      isVoid         = 177,    // This has no value
 
-      Untyped        = 174,    // This value takes a register, but has
+      Untyped        = 178,    // This value takes a register, but has
                                // unspecified type.  The register class
                                // will be determined by the opcode.
 
-      funcref        = 175,    // WebAssembly's funcref type
-      externref      = 176,    // WebAssembly's externref type
-      x86amx         = 177,    // This is an X86 AMX value
-      i64x8          = 178,    // 8 Consecutive GPRs (AArch64)
+      funcref        = 179,    // WebAssembly's funcref type
+      externref      = 180,    // WebAssembly's externref type
+      x86amx         = 181,    // This is an X86 AMX value
+      i64x8          = 182,    // 8 Consecutive GPRs (AArch64)
 
       FIRST_VALUETYPE =  1,    // This is always the beginning of the list.
       LAST_VALUETYPE = i64x8,  // This always remains at the end of the list.
@@ -415,10 +421,11 @@
     /// Return true if this is a 256-bit vector type.
     bool is256BitVector() const {
       return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
-              SimpleTy == MVT::v8f32  || SimpleTy == MVT::v4f64   ||
-              SimpleTy == MVT::v32i8  || SimpleTy == MVT::v16i16  ||
-              SimpleTy == MVT::v8i32  || SimpleTy == MVT::v4i64   ||
-              SimpleTy == MVT::v256i1);
+              SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
+              SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
+              SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 ||
+              SimpleTy == MVT::v256i1 || SimpleTy == MVT::v128i2 ||
+              SimpleTy == MVT::v64i4);
     }
 
     /// Return true if this is a 512-bit vector type.
@@ -517,6 +524,7 @@
     }
 
     MVT getVectorElementType() const {
+      // clang-format off
       switch (SimpleTy) {
       default:
         llvm_unreachable("Not a vector MVT!");
@@ -538,6 +546,8 @@
       case nxv16i1:
       case nxv32i1:
       case nxv64i1: return i1;
+      case v128i2: return i2;
+      case v64i4: return i4;
       case v1i8:
       case v2i8:
       case v4i8:
@@ -677,6 +687,7 @@
       case nxv4f64:
       case nxv8f64: return f64;
       }
+      // clang-format on
     }
 
     /// Given a vector type, return the minimum number of elements it contains.
@@ -705,6 +716,7 @@
       case v256f32:
       case v256f64: return 256;
       case v128i1:
+      case v128i2:
       case v128i8:
       case v128i16:
       case v128i32:
@@ -714,6 +726,7 @@
       case v128f32:
       case v128f64: return 128;
       case v64i1:
+      case v64i4:
       case v64i8:
       case v64i16:
       case v64i32:
@@ -883,8 +896,10 @@
       case i1:
       case v1i1: return TypeSize::Fixed(1);
       case nxv1i1: return TypeSize::Scalable(1);
+      case i2:
       case v2i1: return TypeSize::Fixed(2);
       case nxv2i1: return TypeSize::Scalable(2);
+      case i4:
       case v4i1: return TypeSize::Fixed(4);
       case nxv4i1: return TypeSize::Scalable(4);
       case i8  :
@@ -977,6 +992,8 @@
       case v7i32:
       case v7f32: return TypeSize::Fixed(224);
       case v256i1:
+      case v128i2:
+      case v64i4:
       case v32i8:
       case v16i16:
       case v8i32:
@@ -1171,6 +1188,10 @@
         return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
       case 1:
         return MVT::i1;
+      case 2:
+        return MVT::i2;
+      case 4:
+        return MVT::i4;
       case 8:
         return MVT::i8;
       case 16:
@@ -1185,6 +1206,7 @@
     }
 
     static MVT getVectorVT(MVT VT, unsigned NumElements) {
+      // clang-format off
       switch (VT.SimpleTy) {
       default:
         break;
@@ -1201,6 +1223,12 @@
         if (NumElements == 512)  return MVT::v512i1;
         if (NumElements == 1024) return MVT::v1024i1;
         break;
+      case MVT::i2:
+        if (NumElements == 128) return MVT::v128i2;
+        break;
+      case MVT::i4:
+        if (NumElements == 64) return MVT::v64i4;
+        break;
       case MVT::i8:
         if (NumElements == 1)   return MVT::v1i8;
         if (NumElements == 2)   return MVT::v2i8;
@@ -1315,6 +1343,7 @@
         break;
       }
       return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
+      // clang-format on
     }
 
     static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -739,6 +739,31 @@
   std::fill(std::begin(TargetDAGCombineArray),
             std::end(TargetDAGCombineArray), 0);
 
+  // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
+  // remove this and targets should individually set these types if not legal.
+  for (ISD::NodeType NT :
+       enum_seq_inclusive(ISD::DELETED_NODE, ISD::BUILTIN_OP_END,
+                          force_iteration_on_noniterable_enum)) {
+    for (MVT VT : {MVT::i2, MVT::i4})
+      OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
+  }
+  for (MVT AVT : MVT::all_valuetypes()) {
+    for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
+      setTruncStoreAction(AVT, VT, Expand);
+      setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand);
+      setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand);
+    }
+  }
+  for (unsigned IM = (unsigned)ISD::PRE_INC;
+       IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
+    for (MVT VT : {MVT::i2, MVT::i4}) {
+      setIndexedLoadAction(IM, VT, Expand);
+      setIndexedStoreAction(IM, VT, Expand);
+      setIndexedMaskedLoadAction(IM, VT, Expand);
+      setIndexedMaskedStoreAction(IM, VT, Expand);
+    }
+  }
+
   for (MVT VT : MVT::fp_valuetypes()) {
     MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
     if (IntVT.isValid()) {
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -180,19 +180,22 @@
 /// specified EVT.  For integer types, this returns an unsigned type.  Note
 /// that this will abort for types that cannot be represented.
 Type *EVT::getTypeForEVT(LLVMContext &Context) const {
+  // clang-format off
   switch (V.SimpleTy) {
   default:
     assert(isExtended() && "Type is not extended!");
     return LLVMTy;
   case MVT::isVoid:  return Type::getVoidTy(Context);
   case MVT::i1:      return Type::getInt1Ty(Context);
+  case MVT::i2:      return Type::getIntNTy(Context, 2);
+  case MVT::i4:      return Type::getIntNTy(Context, 4);
   case MVT::i8:      return Type::getInt8Ty(Context);
   case MVT::i16:     return Type::getInt16Ty(Context);
   case MVT::i32:     return Type::getInt32Ty(Context);
   case MVT::i64:     return Type::getInt64Ty(Context);
   case MVT::i128:    return IntegerType::get(Context, 128);
   case MVT::f16:     return Type::getHalfTy(Context);
-  case MVT::bf16:     return Type::getBFloatTy(Context);
+  case MVT::bf16:    return Type::getBFloatTy(Context);
   case MVT::f32:     return Type::getFloatTy(Context);
   case MVT::f64:     return Type::getDoubleTy(Context);
   case MVT::f80:     return Type::getX86_FP80Ty(Context);
@@ -229,6 +232,10 @@
     return FixedVectorType::get(Type::getInt1Ty(Context), 512);
   case MVT::v1024i1:
     return FixedVectorType::get(Type::getInt1Ty(Context), 1024);
+  case MVT::v128i2:
+    return FixedVectorType::get(Type::getIntNTy(Context, 2), 128);
+  case MVT::v64i4:
+    return FixedVectorType::get(Type::getIntNTy(Context, 4), 64);
   case MVT::v1i8:
     return FixedVectorType::get(Type::getInt8Ty(Context), 1);
   case MVT::v2i8:
@@ -521,6 +528,7 @@
     return ScalableVectorType::get(Type::getDoubleTy(Context), 8);
   case MVT::Metadata: return Type::getMetadataTy(Context);
   }
+  // clang-format on
 }
 
 /// Return the value type corresponding to the specified type.  This returns all
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -927,25 +927,25 @@
 enum IIT_Info {
   // Common values should be encoded with 0-15.
   IIT_Done = 0,
-  IIT_I1   = 1,
-  IIT_I8   = 2,
-  IIT_I16  = 3,
-  IIT_I32  = 4,
-  IIT_I64  = 5,
-  IIT_F16  = 6,
-  IIT_F32  = 7,
-  IIT_F64  = 8,
-  IIT_V2   = 9,
-  IIT_V4   = 10,
-  IIT_V8   = 11,
-  IIT_V16  = 12,
-  IIT_V32  = 13,
-  IIT_PTR  = 14,
-  IIT_ARG  = 15,
+  IIT_I1 = 1,
+  IIT_I8 = 2,
+  IIT_I16 = 3,
+  IIT_I32 = 4,
+  IIT_I64 = 5,
+  IIT_F16 = 6,
+  IIT_F32 = 7,
+  IIT_F64 = 8,
+  IIT_V2 = 9,
+  IIT_V4 = 10,
+  IIT_V8 = 11,
+  IIT_V16 = 12,
+  IIT_V32 = 13,
+  IIT_PTR = 14,
+  IIT_ARG = 15,
 
   // Values from 16+ are only encodable with the inefficient encoding.
-  IIT_V64  = 16,
-  IIT_MMX  = 17,
+  IIT_V64 = 16,
+  IIT_MMX = 17,
   IIT_TOKEN = 18,
   IIT_METADATA = 19,
   IIT_EMPTYSTRUCT = 20,
@@ -956,7 +956,7 @@
   IIT_EXTEND_ARG = 25,
   IIT_TRUNC_ARG = 26,
   IIT_ANYPTR = 27,
-  IIT_V1   = 28,
+  IIT_V1 = 28,
   IIT_VARARG = 29,
   IIT_HALF_VEC_ARG = 30,
   IIT_SAME_VEC_WIDTH_ARG = 31,
@@ -979,12 +979,14 @@
   IIT_BF16 = 48,
   IIT_STRUCT9 = 49,
   IIT_V256 = 50,
-  IIT_AMX  = 51,
+  IIT_AMX = 51,
   IIT_PPCF128 = 52,
   IIT_V3 = 53,
   IIT_EXTERNREF = 54,
   IIT_FUNCREF = 55,
   IIT_ANYPTR_TO_ELT = 56,
+  IIT_I2 = 57,
+  IIT_I4 = 58,
 };
 
 static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
@@ -1037,6 +1039,12 @@
   case IIT_I1:
     OutputTable.push_back(IITDescriptor::get(IITDescriptor::Integer, 1));
     return;
+  case IIT_I2:
+    OutputTable.push_back(IITDescriptor::get(IITDescriptor::Integer, 2));
+    return;
+  case IIT_I4:
+    OutputTable.push_back(IITDescriptor::get(IITDescriptor::Integer, 4));
+    return;
   case IIT_I8:
     OutputTable.push_back(IITDescriptor::get(IITDescriptor::Integer, 8));
     return;
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
@@ -23,15 +23,13 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
 ; CHECK-NEXT:    sbfx w9, w0, #0, #4
-; CHECK-NEXT:    movk w8, #10922, lsl #16
-; CHECK-NEXT:    smull x8, w9, w8
-; CHECK-NEXT:    lsr x10, x8, #63
-; CHECK-NEXT:    lsr x8, x8, #32
-; CHECK-NEXT:    add w8, w8, w10
-; CHECK-NEXT:    mov w10, #6
-; CHECK-NEXT:    msub w8, w8, w10, w9
+; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    add w9, w9, w9, lsl #1
+; CHECK-NEXT:    ubfx w10, w9, #7, #1
+; CHECK-NEXT:    add w9, w10, w9, lsr #4
+; CHECK-NEXT:    msub w8, w9, w8, w0
+; CHECK-NEXT:    and w8, w8, #0xf
 ; CHECK-NEXT:    cmp w8, #1
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
@@ -22,13 +22,15 @@
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_bfe_i32 v0, v0, 0, 4
-; CHECK-NEXT:    s_mov_b32 s4, 0x2aaaaaab
-; CHECK-NEXT:    v_mul_hi_i32 v1, v0, s4
-; CHECK-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v1, v1, 6
+; CHECK-NEXT:    v_bfe_i32 v1, v0, 0, 4
+; CHECK-NEXT:    v_mul_i32_i24_e32 v1, 3, v1
+; CHECK-NEXT:    v_lshrrev_b32_e32 v2, 4, v1
+; CHECK-NEXT:    v_bfe_u32 v1, v1, 7, 1
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; CHECK-NEXT:    v_and_b32_e32 v1, 15, v1
+; CHECK-NEXT:    v_mul_u32_u24_e32 v1, 6, v1
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT:    v_and_b32_e32 v0, 15, v0
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
@@ -114,96 +114,88 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; ARM5-LABEL: test_srem_even:
 ; ARM5:       @ %bb.0:
-; ARM5-NEXT:    ldr r2, .LCPI1_0
-; ARM5-NEXT:    lsl r0, r0, #28
-; ARM5-NEXT:    asr r12, r0, #28
-; ARM5-NEXT:    smull r3, r1, r12, r2
-; ARM5-NEXT:    add r1, r1, r1, lsr #31
+; ARM5-NEXT:    lsl r1, r0, #28
+; ARM5-NEXT:    mov r2, #1
+; ARM5-NEXT:    asr r1, r1, #28
+; ARM5-NEXT:    add r1, r1, r1, lsl #1
+; ARM5-NEXT:    and r2, r2, r1, lsr #7
+; ARM5-NEXT:    add r1, r2, r1, lsr #4
 ; ARM5-NEXT:    add r1, r1, r1, lsl #1
-; ARM5-NEXT:    mvn r1, r1, lsl #1
-; ARM5-NEXT:    add r0, r1, r0, asr #28
+; ARM5-NEXT:    sub r0, r0, r1, lsl #1
+; ARM5-NEXT:    and r0, r0, #15
+; ARM5-NEXT:    sub r0, r0, #1
 ; ARM5-NEXT:    clz r0, r0
 ; ARM5-NEXT:    lsr r0, r0, #5
 ; ARM5-NEXT:    bx lr
-; ARM5-NEXT:    .p2align 2
-; ARM5-NEXT:  @ %bb.1:
-; ARM5-NEXT:  .LCPI1_0:
-; ARM5-NEXT:    .long 715827883 @ 0x2aaaaaab
 ;
 ; ARM6-LABEL: test_srem_even:
 ; ARM6:       @ %bb.0:
-; ARM6-NEXT:    ldr r2, .LCPI1_0
-; ARM6-NEXT:    lsl r0, r0, #28
-; ARM6-NEXT:    asr r1, r0, #28
-; ARM6-NEXT:    smmul r1, r1, r2
-; ARM6-NEXT:    add r1, r1, r1, lsr #31
+; ARM6-NEXT:    lsl r1, r0, #28
+; ARM6-NEXT:    mov r2, #1
+; ARM6-NEXT:    asr r1, r1, #28
+; ARM6-NEXT:    add r1, r1, r1, lsl #1
+; ARM6-NEXT:    and r2, r2, r1, lsr #7
+; ARM6-NEXT:    add r1, r2, r1, lsr #4
 ; ARM6-NEXT:    add r1, r1, r1, lsl #1
-; ARM6-NEXT:    mvn r1, r1, lsl #1
-; ARM6-NEXT:    add r0, r1, r0, asr #28
+; ARM6-NEXT:    sub r0, r0, r1, lsl #1
+; ARM6-NEXT:    and r0, r0, #15
+; ARM6-NEXT:    sub r0, r0, #1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    bx lr
-; ARM6-NEXT:    .p2align 2
-; ARM6-NEXT:  @ %bb.1:
-; ARM6-NEXT:  .LCPI1_0:
-; ARM6-NEXT:    .long 715827883 @ 0x2aaaaaab
 ;
 ; ARM7-LABEL: test_srem_even:
 ; ARM7:       @ %bb.0:
-; ARM7-NEXT:    movw r2, #43691
 ; ARM7-NEXT:    sbfx r1, r0, #0, #4
-; ARM7-NEXT:    movt r2, #10922
-; ARM7-NEXT:    lsl r0, r0, #28
-; ARM7-NEXT:    smmul r1, r1, r2
-; ARM7-NEXT:    add r1, r1, r1, lsr #31
 ; ARM7-NEXT:    add r1, r1, r1, lsl #1
-; ARM7-NEXT:    mvn r1, r1, lsl #1
-; ARM7-NEXT:    add r0, r1, r0, asr #28
+; ARM7-NEXT:    ubfx r2, r1, #7, #1
+; ARM7-NEXT:    add r1, r2, r1, lsr #4
+; ARM7-NEXT:    add r1, r1, r1, lsl #1
+; ARM7-NEXT:    sub r0, r0, r1, lsl #1
+; ARM7-NEXT:    and r0, r0, #15
+; ARM7-NEXT:    sub r0, r0, #1
 ; ARM7-NEXT:    clz r0, r0
 ; ARM7-NEXT:    lsr r0, r0, #5
 ; ARM7-NEXT:    bx lr
 ;
 ; ARM8-LABEL: test_srem_even:
 ; ARM8:       @ %bb.0:
-; ARM8-NEXT:    movw r2, #43691
 ; ARM8-NEXT:    sbfx r1, r0, #0, #4
-; ARM8-NEXT:    movt r2, #10922
-; ARM8-NEXT:    lsl r0, r0, #28
-; ARM8-NEXT:    smmul r1, r1, r2
-; ARM8-NEXT:    add r1, r1, r1, lsr #31
 ; ARM8-NEXT:    add r1, r1, r1, lsl #1
-; ARM8-NEXT:    mvn r1, r1, lsl #1
-; ARM8-NEXT:    add r0, r1, r0, asr #28
+; ARM8-NEXT:    ubfx r2, r1, #7, #1
+; ARM8-NEXT:    add r1, r2, r1, lsr #4
+; ARM8-NEXT:    add r1, r1, r1, lsl #1
+; ARM8-NEXT:    sub r0, r0, r1, lsl #1
+; ARM8-NEXT:    and r0, r0, #15
+; ARM8-NEXT:    sub r0, r0, #1
 ; ARM8-NEXT:    clz r0, r0
 ; ARM8-NEXT:    lsr r0, r0, #5
 ; ARM8-NEXT:    bx lr
 ;
 ; NEON7-LABEL: test_srem_even:
 ; NEON7:       @ %bb.0:
-; NEON7-NEXT:    movw r2, #43691
 ; NEON7-NEXT:    sbfx r1, r0, #0, #4
-; NEON7-NEXT:    movt r2, #10922
-; NEON7-NEXT:    lsl r0, r0, #28
-; NEON7-NEXT:    smmul r1, r1, r2
-; NEON7-NEXT:    add r1, r1, r1, lsr #31
 ; NEON7-NEXT:    add r1, r1, r1, lsl #1
-; NEON7-NEXT:    mvn r1, r1, lsl #1
-; NEON7-NEXT:    add r0, r1, r0, asr #28
+; NEON7-NEXT:    ubfx r2, r1, #7, #1
+; NEON7-NEXT:    add r1, r2, r1, lsr #4
+; NEON7-NEXT:    add r1, r1, r1, lsl #1
+; NEON7-NEXT:    sub r0, r0, r1, lsl #1
+; NEON7-NEXT:    and r0, r0, #15
+; NEON7-NEXT:    sub r0, r0, #1
 ; NEON7-NEXT:    clz r0, r0
 ; NEON7-NEXT:    lsr r0, r0, #5
 ; NEON7-NEXT:    bx lr
 ;
 ; NEON8-LABEL: test_srem_even:
 ; NEON8:       @ %bb.0:
-; NEON8-NEXT:    movw r2, #43691
 ; NEON8-NEXT:    sbfx r1, r0, #0, #4
-; NEON8-NEXT:    movt r2, #10922
-; NEON8-NEXT:    lsl r0, r0, #28
-; NEON8-NEXT:    smmul r1, r1, r2
-; NEON8-NEXT:    add r1, r1, r1, lsr #31
 ; NEON8-NEXT:    add r1, r1, r1, lsl #1
-; NEON8-NEXT:    mvn r1, r1, lsl #1
-; NEON8-NEXT:    add r0, r1, r0, asr #28
+; NEON8-NEXT:    ubfx r2, r1, #7, #1
+; NEON8-NEXT:    add r1, r2, r1, lsr #4
+; NEON8-NEXT:    add r1, r1, r1, lsl #1
+; NEON8-NEXT:    sub r0, r0, r1, lsl #1
+; NEON8-NEXT:    and r0, r0, #15
+; NEON8-NEXT:    sub r0, r0, #1
 ; NEON8-NEXT:    clz r0, r0
 ; NEON8-NEXT:    lsr r0, r0, #5
 ; NEON8-NEXT:    bx lr
diff --git a/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
@@ -43,39 +43,41 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; MIPSEL-LABEL: test_srem_even:
 ; MIPSEL:       # %bb.0:
-; MIPSEL-NEXT:    lui $1, 10922
-; MIPSEL-NEXT:    ori $1, $1, 43691
-; MIPSEL-NEXT:    sll $2, $4, 28
-; MIPSEL-NEXT:    sra $2, $2, 28
-; MIPSEL-NEXT:    mult $2, $1
-; MIPSEL-NEXT:    mfhi $1
-; MIPSEL-NEXT:    srl $3, $1, 31
-; MIPSEL-NEXT:    addu $1, $1, $3
+; MIPSEL-NEXT:    sll $1, $4, 28
+; MIPSEL-NEXT:    sra $1, $1, 28
+; MIPSEL-NEXT:    sll $2, $1, 1
+; MIPSEL-NEXT:    addu $1, $2, $1
+; MIPSEL-NEXT:    srl $2, $1, 4
+; MIPSEL-NEXT:    srl $1, $1, 7
+; MIPSEL-NEXT:    andi $1, $1, 1
 ; MIPSEL-NEXT:    addiu $3, $zero, 1
-; MIPSEL-NEXT:    sll $4, $1, 1
+; MIPSEL-NEXT:    addu $1, $2, $1
+; MIPSEL-NEXT:    sll $2, $1, 1
 ; MIPSEL-NEXT:    sll $1, $1, 2
-; MIPSEL-NEXT:    addu $1, $1, $4
-; MIPSEL-NEXT:    subu $1, $2, $1
+; MIPSEL-NEXT:    addu $1, $1, $2
+; MIPSEL-NEXT:    subu $1, $4, $1
+; MIPSEL-NEXT:    andi $1, $1, 15
 ; MIPSEL-NEXT:    xor $1, $1, $3
 ; MIPSEL-NEXT:    jr $ra
 ; MIPSEL-NEXT:    sltiu $2, $1, 1
 ;
 ; MIPS64EL-LABEL: test_srem_even:
 ; MIPS64EL:       # %bb.0:
-; MIPS64EL-NEXT:    lui $1, 10922
-; MIPS64EL-NEXT:    ori $1, $1, 43691
-; MIPS64EL-NEXT:    sll $2, $4, 0
-; MIPS64EL-NEXT:    sll $2, $2, 28
+; MIPS64EL-NEXT:    sll $1, $4, 0
+; MIPS64EL-NEXT:    sll $2, $1, 28
 ; MIPS64EL-NEXT:    sra $2, $2, 28
-; MIPS64EL-NEXT:    mult $2, $1
-; MIPS64EL-NEXT:    mfhi $1
+; MIPS64EL-NEXT:    sll $3, $2, 1
+; MIPS64EL-NEXT:    addu $2, $3, $2
 ; MIPS64EL-NEXT:    addiu $3, $zero, 1
-; MIPS64EL-NEXT:    srl $4, $1, 31
-; MIPS64EL-NEXT:    addu $1, $1, $4
-; MIPS64EL-NEXT:    sll $4, $1, 1
-; MIPS64EL-NEXT:    sll $1, $1, 2
-; MIPS64EL-NEXT:    addu $1, $1, $4
-; MIPS64EL-NEXT:    subu $1, $2, $1
+; MIPS64EL-NEXT:    srl $4, $2, 4
+; MIPS64EL-NEXT:    srl $2, $2, 7
+; MIPS64EL-NEXT:    andi $2, $2, 1
+; MIPS64EL-NEXT:    addu $2, $4, $2
+; MIPS64EL-NEXT:    sll $4, $2, 1
+; MIPS64EL-NEXT:    sll $2, $2, 2
+; MIPS64EL-NEXT:    addu $2, $2, $4
+; MIPS64EL-NEXT:    subu $1, $1, $2
+; MIPS64EL-NEXT:    andi $1, $1, 15
 ; MIPS64EL-NEXT:    xor $1, $1, $3
 ; MIPS64EL-NEXT:    jr $ra
 ; MIPS64EL-NEXT:    sltiu $2, $1, 1
diff --git a/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
@@ -45,38 +45,39 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; PPC-LABEL: test_srem_even:
 ; PPC:       # %bb.0:
-; PPC-NEXT:    lis 4, 10922
-; PPC-NEXT:    slwi 3, 3, 28
-; PPC-NEXT:    ori 4, 4, 43691
-; PPC-NEXT:    srawi 3, 3, 28
-; PPC-NEXT:    mulhw 4, 3, 4
-; PPC-NEXT:    srwi 5, 4, 31
-; PPC-NEXT:    add 4, 4, 5
-; PPC-NEXT:    li 5, 0
-; PPC-NEXT:    mulli 4, 4, 6
-; PPC-NEXT:    sub 3, 3, 4
+; PPC-NEXT:    slwi 5, 3, 28
+; PPC-NEXT:    srawi 5, 5, 28
+; PPC-NEXT:    mulli 5, 5, 3
+; PPC-NEXT:    rlwinm 6, 5, 25, 31, 31
+; PPC-NEXT:    srwi 5, 5, 4
+; PPC-NEXT:    add 5, 5, 6
+; PPC-NEXT:    mulli 5, 5, 6
+; PPC-NEXT:    sub 3, 3, 5
+; PPC-NEXT:    clrlwi 3, 3, 28
+; PPC-NEXT:    li 4, 0
 ; PPC-NEXT:    cmpwi 3, 1
 ; PPC-NEXT:    li 3, 1
 ; PPC-NEXT:    bclr 12, 2, 0
 ; PPC-NEXT:  # %bb.1:
-; PPC-NEXT:    ori 3, 5, 0
+; PPC-NEXT:    ori 3, 4, 0
 ; PPC-NEXT:    blr
 ;
 ; PPC64LE-LABEL: test_srem_even:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    lis 4, 10922
-; PPC64LE-NEXT:    slwi 3, 3, 28
-; PPC64LE-NEXT:    ori 4, 4, 43691
-; PPC64LE-NEXT:    srawi 3, 3, 28
-; PPC64LE-NEXT:    mulhw 4, 3, 4
-; PPC64LE-NEXT:    srwi 5, 4, 31
-; PPC64LE-NEXT:    add 4, 4, 5
-; PPC64LE-NEXT:    mulli 4, 4, 6
-; PPC64LE-NEXT:    sub 3, 3, 4
-; PPC64LE-NEXT:    li 4, 1
+; PPC64LE-NEXT:    slwi 5, 3, 28
+; PPC64LE-NEXT:    li 4, 0
+; PPC64LE-NEXT:    srawi 5, 5, 28
+; PPC64LE-NEXT:    slwi 6, 5, 1
+; PPC64LE-NEXT:    add 5, 5, 6
+; PPC64LE-NEXT:    rlwinm 6, 5, 25, 31, 31
+; PPC64LE-NEXT:    srwi 5, 5, 4
+; PPC64LE-NEXT:    add 5, 5, 6
+; PPC64LE-NEXT:    mulli 5, 5, 6
+; PPC64LE-NEXT:    sub 3, 3, 5
+; PPC64LE-NEXT:    clrlwi 3, 3, 28
 ; PPC64LE-NEXT:    cmpwi 3, 1
-; PPC64LE-NEXT:    li 3, 0
-; PPC64LE-NEXT:    iseleq 3, 4, 3
+; PPC64LE-NEXT:    li 3, 1
+; PPC64LE-NEXT:    iseleq 3, 3, 4
 ; PPC64LE-NEXT:    blr
   %srem = srem i4 %X, 6
   %cmp = icmp eq i4 %srem, 1
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -140,64 +140,72 @@
 ;
 ; RV32M-LABEL: test_srem_even:
 ; RV32M:       # %bb.0:
-; RV32M-NEXT:    slli a0, a0, 28
-; RV32M-NEXT:    srai a0, a0, 28
-; RV32M-NEXT:    lui a1, 174763
-; RV32M-NEXT:    addi a1, a1, -1365
-; RV32M-NEXT:    mulh a1, a0, a1
-; RV32M-NEXT:    srli a2, a1, 31
-; RV32M-NEXT:    add a1, a1, a2
+; RV32M-NEXT:    slli a1, a0, 28
+; RV32M-NEXT:    srai a1, a1, 28
+; RV32M-NEXT:    slli a2, a1, 1
+; RV32M-NEXT:    add a1, a2, a1
+; RV32M-NEXT:    srli a2, a1, 4
+; RV32M-NEXT:    slli a1, a1, 24
+; RV32M-NEXT:    srli a1, a1, 31
+; RV32M-NEXT:    add a1, a2, a1
 ; RV32M-NEXT:    li a2, 6
 ; RV32M-NEXT:    mul a1, a1, a2
 ; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    andi a0, a0, 15
 ; RV32M-NEXT:    addi a0, a0, -1
 ; RV32M-NEXT:    seqz a0, a0
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_srem_even:
 ; RV64M:       # %bb.0:
-; RV64M-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64M-NEXT:    ld a1, %lo(.LCPI1_0)(a1)
-; RV64M-NEXT:    slli a0, a0, 60
-; RV64M-NEXT:    srai a0, a0, 60
-; RV64M-NEXT:    mulh a1, a0, a1
-; RV64M-NEXT:    srli a2, a1, 63
-; RV64M-NEXT:    add a1, a1, a2
+; RV64M-NEXT:    slli a1, a0, 60
+; RV64M-NEXT:    srai a1, a1, 60
+; RV64M-NEXT:    slli a2, a1, 1
+; RV64M-NEXT:    add a1, a2, a1
+; RV64M-NEXT:    srli a2, a1, 4
+; RV64M-NEXT:    slli a1, a1, 56
+; RV64M-NEXT:    srli a1, a1, 63
+; RV64M-NEXT:    addw a1, a2, a1
 ; RV64M-NEXT:    li a2, 6
-; RV64M-NEXT:    mul a1, a1, a2
-; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    mulw a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    andi a0, a0, 15
 ; RV64M-NEXT:    addi a0, a0, -1
 ; RV64M-NEXT:    seqz a0, a0
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_srem_even:
 ; RV32MV:       # %bb.0:
-; RV32MV-NEXT:    slli a0, a0, 28
-; RV32MV-NEXT:    srai a0, a0, 28
-; RV32MV-NEXT:    lui a1, 174763
-; RV32MV-NEXT:    addi a1, a1, -1365
-; RV32MV-NEXT:    mulh a1, a0, a1
-; RV32MV-NEXT:    srli a2, a1, 31
-; RV32MV-NEXT:    add a1, a1, a2
+; RV32MV-NEXT:    slli a1, a0, 28
+; RV32MV-NEXT:    srai a1, a1, 28
+; RV32MV-NEXT:    slli a2, a1, 1
+; RV32MV-NEXT:    add a1, a2, a1
+; RV32MV-NEXT:    srli a2, a1, 4
+; RV32MV-NEXT:    slli a1, a1, 24
+; RV32MV-NEXT:    srli a1, a1, 31
+; RV32MV-NEXT:    add a1, a2, a1
 ; RV32MV-NEXT:    li a2, 6
 ; RV32MV-NEXT:    mul a1, a1, a2
 ; RV32MV-NEXT:    sub a0, a0, a1
+; RV32MV-NEXT:    andi a0, a0, 15
 ; RV32MV-NEXT:    addi a0, a0, -1
 ; RV32MV-NEXT:    seqz a0, a0
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_srem_even:
 ; RV64MV:       # %bb.0:
-; RV64MV-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64MV-NEXT:    ld a1, %lo(.LCPI1_0)(a1)
-; RV64MV-NEXT:    slli a0, a0, 60
-; RV64MV-NEXT:    srai a0, a0, 60
-; RV64MV-NEXT:    mulh a1, a0, a1
-; RV64MV-NEXT:    srli a2, a1, 63
-; RV64MV-NEXT:    add a1, a1, a2
+; RV64MV-NEXT:    slli a1, a0, 60
+; RV64MV-NEXT:    srai a1, a1, 60
+; RV64MV-NEXT:    slli a2, a1, 1
+; RV64MV-NEXT:    add a1, a2, a1
+; RV64MV-NEXT:    srli a2, a1, 4
+; RV64MV-NEXT:    slli a1, a1, 56
+; RV64MV-NEXT:    srli a1, a1, 63
+; RV64MV-NEXT:    addw a1, a2, a1
 ; RV64MV-NEXT:    li a2, 6
-; RV64MV-NEXT:    mul a1, a1, a2
-; RV64MV-NEXT:    sub a0, a0, a1
+; RV64MV-NEXT:    mulw a1, a1, a2
+; RV64MV-NEXT:    subw a0, a0, a1
+; RV64MV-NEXT:    andi a0, a0, 15
 ; RV64MV-NEXT:    addi a0, a0, -1
 ; RV64MV-NEXT:    seqz a0, a0
 ; RV64MV-NEXT:    ret
diff --git a/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
@@ -33,18 +33,22 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r7, lr}
-; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    lsls r0, r0, #28
-; CHECK-NEXT:    asrs r0, r0, #28
-; CHECK-NEXT:    movs r1, #6
-; CHECK-NEXT:    bl __aeabi_idivmod
+; CHECK-NEXT:    lsls r1, r0, #28
+; CHECK-NEXT:    asrs r1, r1, #28
+; CHECK-NEXT:    movs r2, #3
+; CHECK-NEXT:    muls r2, r1, r2
+; CHECK-NEXT:    lsrs r1, r2, #31
+; CHECK-NEXT:    lsrs r2, r2, #4
+; CHECK-NEXT:    adds r1, r2, r1
+; CHECK-NEXT:    movs r2, #6
+; CHECK-NEXT:    muls r2, r1, r2
+; CHECK-NEXT:    subs r0, r0, r2
+; CHECK-NEXT:    movs r1, #15
+; CHECK-NEXT:    ands r1, r0
 ; CHECK-NEXT:    subs r1, r1, #1
 ; CHECK-NEXT:    rsbs r0, r1, #0
 ; CHECK-NEXT:    adcs r0, r1
-; CHECK-NEXT:    pop {r7}
-; CHECK-NEXT:    pop {r1}
-; CHECK-NEXT:    bx r1
+; CHECK-NEXT:    bx lr
   %srem = srem i4 %X, 6
   %cmp = icmp eq i4 %srem, 1
   ret i1 %cmp
diff --git a/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
@@ -25,15 +25,14 @@
 define i1 @test_srem_even(i4 %X) nounwind {
 ; CHECK-LABEL: test_srem_even:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    movw r2, #43691
 ; CHECK-NEXT:    sbfx r1, r0, #0, #4
-; CHECK-NEXT:    movt r2, #10922
-; CHECK-NEXT:    lsls r0, r0, #28
-; CHECK-NEXT:    smmul r1, r1, r2
-; CHECK-NEXT:    add.w r1, r1, r1, lsr #31
 ; CHECK-NEXT:    add.w r1, r1, r1, lsl #1
-; CHECK-NEXT:    mvn.w r1, r1, lsl #1
-; CHECK-NEXT:    add.w r0, r1, r0, asr #28
+; CHECK-NEXT:    ubfx r2, r1, #7, #1
+; CHECK-NEXT:    add.w r1, r2, r1, lsr #4
+; CHECK-NEXT:    add.w r1, r1, r1, lsl #1
+; CHECK-NEXT:    sub.w r0, r0, r1, lsl #1
+; CHECK-NEXT:    and r0, r0, #15
+; CHECK-NEXT:    subs r0, #1
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
diff --git a/llvm/test/CodeGen/X86/bitreverse.ll b/llvm/test/CodeGen/X86/bitreverse.ll
--- a/llvm/test/CodeGen/X86/bitreverse.ll
+++ b/llvm/test/CodeGen/X86/bitreverse.ll
@@ -397,39 +397,39 @@
 define i4 @test_bitreverse_i4(i4 %a) {
 ; X86-LABEL: test_bitreverse_i4:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    rolb $4, %al
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    andb $51, %cl
-; X86-NEXT:    shlb $2, %cl
-; X86-NEXT:    shrb $2, %al
-; X86-NEXT:    andb $51, %al
-; X86-NEXT:    orb %cl, %al
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    andb $80, %cl
-; X86-NEXT:    addb %cl, %cl
-; X86-NEXT:    shrb %al
-; X86-NEXT:    andb $80, %al
-; X86-NEXT:    orb %cl, %al
-; X86-NEXT:    shrb $4, %al
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT:    movl %ecx, %eax
+; X86-NEXT:    andb $15, %al
+; X86-NEXT:    movl %ecx, %edx
+; X86-NEXT:    addb %cl, %dl
+; X86-NEXT:    andb $4, %dl
+; X86-NEXT:    shlb $3, %cl
+; X86-NEXT:    andb $8, %cl
+; X86-NEXT:    orb %dl, %cl
+; X86-NEXT:    movl %eax, %edx
+; X86-NEXT:    shrb %dl
+; X86-NEXT:    andb $2, %dl
+; X86-NEXT:    orb %cl, %dl
+; X86-NEXT:    shrb $3, %al
+; X86-NEXT:    orb %dl, %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bitreverse_i4:
 ; X64:       # %bb.0:
-; X64-NEXT:    rolb $4, %dil
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi), %ecx
+; X64-NEXT:    leal (,%rdi,8), %edx
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    andb $51, %al
-; X64-NEXT:    shlb $2, %al
-; X64-NEXT:    shrb $2, %dil
-; X64-NEXT:    andb $51, %dil
-; X64-NEXT:    orb %dil, %al
+; X64-NEXT:    andb $15, %al
+; X64-NEXT:    andb $4, %cl
+; X64-NEXT:    andb $8, %dl
+; X64-NEXT:    orb %cl, %dl
 ; X64-NEXT:    movl %eax, %ecx
-; X64-NEXT:    andb $80, %cl
-; X64-NEXT:    addb %cl, %cl
-; X64-NEXT:    shrb %al
-; X64-NEXT:    andb $80, %al
+; X64-NEXT:    shrb %cl
+; X64-NEXT:    andb $2, %cl
+; X64-NEXT:    orb %dl, %cl
+; X64-NEXT:    shrb $3, %al
 ; X64-NEXT:    orb %cl, %al
-; X64-NEXT:    shrb $4, %al
 ; X64-NEXT:    retq
 ;
 ; X86XOP-LABEL: test_bitreverse_i4:
diff --git a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
--- a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
@@ -34,38 +34,41 @@
 ; X86-LABEL: test_srem_even:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    shlb $4, %al
-; X86-NEXT:    sarb $4, %al
-; X86-NEXT:    movsbl %al, %ecx
-; X86-NEXT:    imull $43, %ecx, %ecx
-; X86-NEXT:    movzwl %cx, %ecx
+; X86-NEXT:    movl %eax, %ecx
+; X86-NEXT:    shlb $4, %cl
+; X86-NEXT:    sarb $4, %cl
+; X86-NEXT:    movzbl %cl, %ecx
+; X86-NEXT:    leal (%ecx,%ecx,2), %ecx
 ; X86-NEXT:    movl %ecx, %edx
-; X86-NEXT:    shrl $15, %edx
-; X86-NEXT:    addb %ch, %dl
-; X86-NEXT:    movzbl %dl, %ecx
+; X86-NEXT:    shrb $7, %dl
+; X86-NEXT:    shrb $4, %cl
+; X86-NEXT:    addb %dl, %cl
+; X86-NEXT:    movzbl %cl, %ecx
 ; X86-NEXT:    addl %ecx, %ecx
 ; X86-NEXT:    leal (%ecx,%ecx,2), %ecx
 ; X86-NEXT:    subb %cl, %al
+; X86-NEXT:    andb $15, %al
 ; X86-NEXT:    cmpb $1, %al
 ; X86-NEXT:    sete %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_srem_even:
 ; X64:       # %bb.0:
-; X64-NEXT:    shlb $4, %dil
-; X64-NEXT:    sarb $4, %dil
-; X64-NEXT:    movsbl %dil, %eax
-; X64-NEXT:    imull $43, %eax, %ecx
-; X64-NEXT:    movzwl %cx, %ecx
-; X64-NEXT:    movl %ecx, %edx
-; X64-NEXT:    shrl $15, %edx
-; X64-NEXT:    shrl $8, %ecx
-; X64-NEXT:    addb %dl, %cl
-; X64-NEXT:    movzbl %cl, %ecx
-; X64-NEXT:    addl %ecx, %ecx
-; X64-NEXT:    leal (%rcx,%rcx,2), %ecx
-; X64-NEXT:    subb %cl, %al
-; X64-NEXT:    cmpb $1, %al
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shlb $4, %al
+; X64-NEXT:    sarb $4, %al
+; X64-NEXT:    movzbl %al, %eax
+; X64-NEXT:    leal (%rax,%rax,2), %eax
+; X64-NEXT:    movl %eax, %ecx
+; X64-NEXT:    shrb $7, %cl
+; X64-NEXT:    shrb $4, %al
+; X64-NEXT:    addb %cl, %al
+; X64-NEXT:    movzbl %al, %eax
+; X64-NEXT:    addl %eax, %eax
+; X64-NEXT:    leal (%rax,%rax,2), %eax
+; X64-NEXT:    subb %al, %dil
+; X64-NEXT:    andb $15, %dil
+; X64-NEXT:    cmpb $1, %dil
 ; X64-NEXT:    sete %al
 ; X64-NEXT:    retq
   %srem = srem i4 %X, 6
diff --git a/llvm/test/TableGen/intrinsic-pointer-to-any.td b/llvm/test/TableGen/intrinsic-pointer-to-any.td
--- a/llvm/test/TableGen/intrinsic-pointer-to-any.td
+++ b/llvm/test/TableGen/intrinsic-pointer-to-any.td
@@ -54,4 +54,4 @@
 def llvm_i8_ty : LLVMType<i8>;
 
 def int_has_ptr_to_any : Intrinsic<[LLVMPointerType<llvm_any_ty>, llvm_i8_ty]>;
-// CHECK: /* 0 */ 21, 14, 15, 0, 2, 0
+// CHECK: /* 0 */ 21, 14, 15, 0, 57, 0
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -53,9 +53,12 @@
 }
 
 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
+  // clang-format off
   switch (T) {
   case MVT::Other:    return "MVT::Other";
   case MVT::i1:       return "MVT::i1";
+  case MVT::i2:       return "MVT::i2";
+  case MVT::i4:       return "MVT::i4";
   case MVT::i8:       return "MVT::i8";
   case MVT::i16:      return "MVT::i16";
   case MVT::i32:      return "MVT::i32";
@@ -88,6 +91,8 @@
   case MVT::v256i1:   return "MVT::v256i1";
   case MVT::v512i1:   return "MVT::v512i1";
   case MVT::v1024i1:  return "MVT::v1024i1";
+  case MVT::v128i2:   return "MVT::v128i2";
+  case MVT::v64i4:    return "MVT::v64i4";
   case MVT::v1i8:     return "MVT::v1i8";
   case MVT::v2i8:     return "MVT::v2i8";
   case MVT::v4i8:     return "MVT::v4i8";
@@ -242,6 +247,7 @@
   case MVT::externref: return "MVT::externref";
   default: llvm_unreachable("ILLEGAL VALUE TYPE!");
   }
+  // clang-format on
 }
 
 /// getQualifiedName - Return the name of the specified record, with a
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -196,25 +196,25 @@
 enum IIT_Info {
   // Common values should be encoded with 0-15.
   IIT_Done = 0,
-  IIT_I1   = 1,
-  IIT_I8   = 2,
-  IIT_I16  = 3,
-  IIT_I32  = 4,
-  IIT_I64  = 5,
-  IIT_F16  = 6,
-  IIT_F32  = 7,
-  IIT_F64  = 8,
-  IIT_V2   = 9,
-  IIT_V4   = 10,
-  IIT_V8   = 11,
-  IIT_V16  = 12,
-  IIT_V32  = 13,
-  IIT_PTR  = 14,
-  IIT_ARG  = 15,
+  IIT_I1 = 1,
+  IIT_I8 = 2,
+  IIT_I16 = 3,
+  IIT_I32 = 4,
+  IIT_I64 = 5,
+  IIT_F16 = 6,
+  IIT_F32 = 7,
+  IIT_F64 = 8,
+  IIT_V2 = 9,
+  IIT_V4 = 10,
+  IIT_V8 = 11,
+  IIT_V16 = 12,
+  IIT_V32 = 13,
+  IIT_PTR = 14,
+  IIT_ARG = 15,
 
   // Values from 16+ are only encodable with the inefficient encoding.
-  IIT_V64  = 16,
-  IIT_MMX  = 17,
+  IIT_V64 = 16,
+  IIT_MMX = 17,
   IIT_TOKEN = 18,
   IIT_METADATA = 19,
   IIT_EMPTYSTRUCT = 20,
@@ -225,7 +225,7 @@
   IIT_EXTEND_ARG = 25,
   IIT_TRUNC_ARG = 26,
   IIT_ANYPTR = 27,
-  IIT_V1   = 28,
+  IIT_V1 = 28,
   IIT_VARARG = 29,
   IIT_HALF_VEC_ARG = 30,
   IIT_SAME_VEC_WIDTH_ARG = 31,
@@ -248,21 +248,26 @@
   IIT_BF16 = 48,
   IIT_STRUCT9 = 49,
   IIT_V256 = 50,
-  IIT_AMX  = 51,
+  IIT_AMX = 51,
   IIT_PPCF128 = 52,
   IIT_V3 = 53,
   IIT_EXTERNREF = 54,
   IIT_FUNCREF = 55,
   IIT_ANYPTR_TO_ELT = 56,
+  IIT_I2 = 57,
+  IIT_I4 = 58,
 };
 
 static void EncodeFixedValueType(MVT::SimpleValueType VT,
                                  std::vector<unsigned char> &Sig) {
+  // clang-format off
   if (MVT(VT).isInteger()) {
     unsigned BitWidth = MVT(VT).getFixedSizeInBits();
     switch (BitWidth) {
     default: PrintFatalError("unhandled integer type width in intrinsic!");
     case 1: return Sig.push_back(IIT_I1);
+    case 2: return Sig.push_back(IIT_I2);
+    case 4: return Sig.push_back(IIT_I4);
     case 8: return Sig.push_back(IIT_I8);
     case 16: return Sig.push_back(IIT_I16);
     case 32: return Sig.push_back(IIT_I32);
@@ -292,6 +297,7 @@
   case MVT::funcref:
     return Sig.push_back(IIT_FUNCREF);
   }
+  // clang-format on
 }
 
 #if defined(_MSC_VER) && !defined(__clang__)