diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
@@ -52,6 +52,70 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
+
+define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
+
+define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
+
+define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
+
+define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
@@ -95,6 +159,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
+
+define signext i1 @vreduce_umax_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
+
+define signext i1 @vreduce_smax_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
+
+define signext i1 @vreduce_umin_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
+
+define signext i1 @vreduce_smin_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_or_v4i1(<4 x i1> %v) {
@@ -138,6 +260,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1>)
+
+define signext i1 @vreduce_umax_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v4i1(<4 x i1>)
+
+define signext i1 @vreduce_smax_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v4i1(<4 x i1>)
+
+define signext i1 @vreduce_umin_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v4i1(<4 x i1>)
+
+define signext i1 @vreduce_smin_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_or_v8i1(<8 x i1> %v) {
@@ -181,6 +361,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v8i1(<8 x i1>)
+
+define signext i1 @vreduce_umax_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v8i1(<8 x i1>)
+
+define signext i1 @vreduce_smax_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v8i1(<8 x i1>)
+
+define signext i1 @vreduce_umin_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v8i1(<8 x i1>)
+
+define signext i1 @vreduce_smin_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
 
 define signext i1 @vreduce_or_v16i1(<16 x i1> %v) {
@@ -224,6 +462,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v16i1(<16 x i1>)
+
+define signext i1 @vreduce_umax_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v16i1(<16 x i1>)
+
+define signext i1 @vreduce_smax_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v16i1(<16 x i1>)
+
+define signext i1 @vreduce_umin_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v16i1(<16 x i1>)
+
+define signext i1 @vreduce_smin_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
 
 define signext i1 @vreduce_or_v32i1(<32 x i1> %v) {
@@ -297,6 +593,104 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.v32i1(<32 x i1>)
+
+define signext i1 @vreduce_umax_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_umax_v32i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmor.mm v8, v0, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    snez a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umax_v32i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 32
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    snez a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v32i1(<32 x i1>)
+
+define signext i1 @vreduce_smax_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_smax_v32i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmnand.mm v8, v0, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    seqz a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smax_v32i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 32
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; LMULMAX8-NEXT:    vmnot.m v8, v0
+; LMULMAX8-NEXT:    vcpop.m a0, v8
+; LMULMAX8-NEXT:    seqz a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v32i1(<32 x i1>)
+
+define signext i1 @vreduce_umin_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_umin_v32i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmnand.mm v8, v0, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    seqz a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umin_v32i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 32
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; LMULMAX8-NEXT:    vmnot.m v8, v0
+; LMULMAX8-NEXT:    vcpop.m a0, v8
+; LMULMAX8-NEXT:    seqz a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v32i1(<32 x i1>)
+
+define signext i1 @vreduce_smin_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_smin_v32i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmor.mm v8, v0, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    snez a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smin_v32i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 32
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    snez a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
 
 define signext i1 @vreduce_or_v64i1(<64 x i1> %v) {
@@ -375,3 +769,109 @@
   %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)
   ret i1 %red
 }
+
+declare i1 @llvm.vector.reduce.umax.v64i1(<64 x i1>)
+
+define signext i1 @vreduce_umax_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_umax_v64i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmor.mm v8, v8, v10
+; LMULMAX1-NEXT:    vmor.mm v9, v0, v9
+; LMULMAX1-NEXT:    vmor.mm v8, v9, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    snez a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umax_v64i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 64
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    snez a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.v64i1(<64 x i1>)
+
+define signext i1 @vreduce_smax_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_smax_v64i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmand.mm v8, v8, v10
+; LMULMAX1-NEXT:    vmand.mm v9, v0, v9
+; LMULMAX1-NEXT:    vmnand.mm v8, v9, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    seqz a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smax_v64i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 64
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
+; LMULMAX8-NEXT:    vmnot.m v8, v0
+; LMULMAX8-NEXT:    vcpop.m a0, v8
+; LMULMAX8-NEXT:    seqz a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.v64i1(<64 x i1>)
+
+define signext i1 @vreduce_umin_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_umin_v64i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmand.mm v8, v8, v10
+; LMULMAX1-NEXT:    vmand.mm v9, v0, v9
+; LMULMAX1-NEXT:    vmnand.mm v8, v9, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    seqz a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umin_v64i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 64
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
+; LMULMAX8-NEXT:    vmnot.m v8, v0
+; LMULMAX8-NEXT:    vcpop.m a0, v8
+; LMULMAX8-NEXT:    seqz a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.v64i1(<64 x i1>)
+
+define signext i1 @vreduce_smin_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_smin_v64i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT:    vmor.mm v8, v8, v10
+; LMULMAX1-NEXT:    vmor.mm v9, v0, v9
+; LMULMAX1-NEXT:    vmor.mm v8, v9, v8
+; LMULMAX1-NEXT:    vcpop.m a0, v8
+; LMULMAX1-NEXT:    snez a0, a0
+; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smin_v64i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    li a0, 64
+; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    snez a0, a0
+; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
+  ret i1 %red
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
@@ -45,6 +45,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1>)
+
+define signext i1 @vreduce_umax_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1>)
+
+define signext i1 @vreduce_smax_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1>)
+
+define signext i1 @vreduce_umin_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1>)
+
+define signext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)
 
 define signext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {
@@ -88,6 +146,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1>)
+
+define signext i1 @vreduce_umax_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1>)
+
+define signext i1 @vreduce_smax_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1>)
+
+define signext i1 @vreduce_umin_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1>)
+
+define signext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1>)
 
 define signext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {
@@ -131,6 +247,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1>)
+
+define signext i1 @vreduce_umax_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1>)
+
+define signext i1 @vreduce_smax_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1>)
+
+define signext i1 @vreduce_umin_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1>)
+
+define signext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1>)
 
 define signext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {
@@ -174,6 +348,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1>)
+
+define signext i1 @vreduce_umax_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1>)
+
+define signext i1 @vreduce_smax_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1>)
+
+define signext i1 @vreduce_umin_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1>)
+
+define signext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
 
 define signext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {
@@ -217,6 +449,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1>)
+
+define signext i1 @vreduce_umax_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1>)
+
+define signext i1 @vreduce_smax_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1>)
+
+define signext i1 @vreduce_umin_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1>)
+
+define signext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>)
 
 define signext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {
@@ -260,6 +550,64 @@
   ret i1 %red
 }
 
+declare i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1>)
+
+define signext i1 @vreduce_umax_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1>)
+
+define signext i1 @vreduce_smax_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1>)
+
+define signext i1 @vreduce_umin_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1>)
+
+define signext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %v)
+  ret i1 %red
+}
+
 declare i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1>)
 
 define signext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {
@@ -302,3 +650,61 @@
   %red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)
   ret i1 %red
 }
+
+declare i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1>)
+
+define signext i1 @vreduce_umax_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_umax_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1>)
+
+define signext i1 @vreduce_smax_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_smax_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1>)
+
+define signext i1 @vreduce_umin_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_umin_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1> %v)
+  ret i1 %red
+}
+
+declare i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1>)
+
+define signext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_smin_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)
+  ret i1 %red
+}