diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -15536,6 +15536,11 @@ } SDValue CsetOp = CmpOp->getOperand(IsAdd ? 0 : 1); + + // Strip away AND with 1. + if (CsetOp.getOpcode() == ISD::AND && isOneConstant(CsetOp.getOperand(1))) + CsetOp = CsetOp.getOperand(0); + auto CC = getCSETCondCode(CsetOp); if (CC != (IsAdd ? AArch64CC::HS : AArch64CC::LO)) return SDValue(); diff --git a/llvm/test/CodeGen/AArch64/i256-math.ll b/llvm/test/CodeGen/AArch64/i256-math.ll --- a/llvm/test/CodeGen/AArch64/i256-math.ll +++ b/llvm/test/CodeGen/AArch64/i256-math.ll @@ -98,11 +98,7 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: subs x0, x0, x4 ; CHECK-NEXT: sbcs x1, x1, x5 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x2, x2, x6 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x3, x3, x7 ; CHECK-NEXT: cset w8, lo ; CHECK-NEXT: eor w4, w8, #0x1 @@ -122,11 +118,7 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: subs x0, x0, x4 ; CHECK-NEXT: sbcs x1, x1, x5 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x2, x2, x6 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x3, x3, x7 ; CHECK-NEXT: cset w4, lo ; CHECK-NEXT: ret @@ -244,11 +236,7 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: subs x0, x0, x4 ; CHECK-NEXT: sbcs x1, x1, x5 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x2, x2, x6 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x3, x3, x7 ; CHECK-NEXT: cset w8, vs ; CHECK-NEXT: eor w4, w8, #0x1 @@ -268,11 +256,7 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: subs x0, x0, x4 ; CHECK-NEXT: sbcs x1, x1, x5 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x2, x2, x6 -; CHECK-NEXT: cset w8, lo -; CHECK-NEXT: cmp wzr, w8 ; CHECK-NEXT: sbcs x3, x3, x7 ; CHECK-NEXT: cset w4, vs ; CHECK-NEXT: ret