diff --git a/llvm/test/CodeGen/RISCV/float-arith-strict.ll b/llvm/test/CodeGen/RISCV/float-arith-strict.ll --- a/llvm/test/CodeGen/RISCV/float-arith-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-arith-strict.ll @@ -1,25 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s define float @fadd_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fadd_s: ; RV32I: # %bb.0: @@ -44,15 +39,10 @@ declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) define float @fsub_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsub.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsub.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsub.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsub_s: ; RV32I: # %bb.0: @@ -77,15 +67,10 @@ declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) define float @fmul_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fmul_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmul.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmul_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmul.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmul_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmul.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmul_s: ; RV32I: # %bb.0: @@ -110,15 +95,10 @@ declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) define float @fdiv_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fdiv_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fdiv_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fdiv_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fdiv.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fdiv_s: ; RV32I: # %bb.0: @@ -143,15 +123,10 @@ declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) define float @fsqrt_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fsqrt_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsqrt_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsqrt_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsqrt_s: ; RV32I: # %bb.0: @@ -258,15 +233,10 @@ declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmadd_s: ; RV32I: # %bb.0: @@ -291,19 +261,12 @@ declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmsub_s: ; RV32I: # %bb.0: @@ -355,21 +318,13 @@ } define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmadd_s: ; RV32I: # %bb.0: @@ -435,21 +390,13 @@ } define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmadd_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa0, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_2: ; RV32I: # %bb.0: @@ -515,19 +462,12 @@ } define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa0, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa0, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa0, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmsub_s: ; RV32I: # %bb.0: @@ -577,19 +517,12 @@ } define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmsub_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa0, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_2: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ @@ -14,15 +14,10 @@ ; instructions that don't directly match a RISC-V instruction. define float @fadd_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fadd_s: ; RV32I: # %bb.0: @@ -46,15 +41,10 @@ } define float @fsub_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsub.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsub.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsub.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsub_s: ; RV32I: # %bb.0: @@ -78,15 +68,10 @@ } define float @fmul_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmul_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmul.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmul_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmul.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmul_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmul.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmul_s: ; RV32I: # %bb.0: @@ -110,15 +95,10 @@ } define float @fdiv_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fdiv_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fdiv_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fdiv_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fdiv.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fdiv_s: ; RV32I: # %bb.0: @@ -144,15 +124,10 @@ declare float @llvm.sqrt.f32(float) define float @fsqrt_s(float %a) nounwind { -; RV32IF-LABEL: fsqrt_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsqrt_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsqrt_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsqrt_s: ; RV32I: # %bb.0: @@ -178,15 +153,10 @@ declare float @llvm.copysign.f32(float, float) define float @fsgnj_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsgnj_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsgnj_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsgnj_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsgnj.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsgnj_s: ; RV32I: # %bb.0: @@ -212,19 +182,12 @@ ; This function performs extra work to ensure that ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. define i32 @fneg_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fneg_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa0 -; RV32IF-NEXT: fneg.s ft1, ft0 -; RV32IF-NEXT: feq.s a0, ft0, ft1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fneg_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa0 -; RV64IF-NEXT: fneg.s ft1, ft0 -; RV64IF-NEXT: feq.s a0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fneg_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa0 +; CHECK-NEXT: fneg.s ft1, ft0 +; CHECK-NEXT: feq.s a0, ft0, ft1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fneg_s: ; RV32I: # %bb.0: @@ -263,17 +226,11 @@ ; This function performs extra work to ensure that ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. define float @fsgnjn_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsgnjn_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fsgnjn.s fa0, fa0, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsgnjn_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fsgnjn.s fa0, fa0, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fsgnjn_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fsgnjn.s fa0, fa0, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fsgnjn_s: ; RV32I: # %bb.0: @@ -321,19 +278,12 @@ ; This function performs extra work to ensure that ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and. define float @fabs_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fabs_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fabs.s ft1, ft0 -; RV32IF-NEXT: fadd.s fa0, ft1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fabs_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fabs.s ft1, ft0 -; RV64IF-NEXT: fadd.s fa0, ft1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fabs_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fabs.s ft1, ft0 +; CHECK-NEXT: fadd.s fa0, ft1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fabs_s: ; RV32I: # %bb.0: @@ -369,15 +319,10 @@ declare float @llvm.minnum.f32(float, float) define float @fmin_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmin_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmin.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmin_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmin.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmin_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmin.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmin_s: ; RV32I: # %bb.0: @@ -403,15 +348,10 @@ declare float @llvm.maxnum.f32(float, float) define float @fmax_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmax_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmax.s fa0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmax_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmax.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmax_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmax.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmax_s: ; RV32I: # %bb.0: @@ -437,15 +377,10 @@ declare float @llvm.fma.f32(float, float, float) define float @fmadd_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmadd_s: ; RV32I: # %bb.0: @@ -469,19 +404,12 @@ } define float @fmsub_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmsub_s: ; RV32I: # %bb.0: @@ -533,21 +461,13 @@ } define float @fnmadd_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmadd_s: ; RV32I: # %bb.0: @@ -613,21 +533,13 @@ } define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa0, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_2: ; RV32I: # %bb.0: @@ -693,19 +605,12 @@ } define float @fnmsub_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa0, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa0, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa0, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmsub_s: ; RV32I: # %bb.0: @@ -755,19 +660,12 @@ } define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa0, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_2: ; RV32I: # %bb.0: @@ -819,15 +717,10 @@ } define float @fmadd_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmadd_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmadd_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmadd_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmadd_s_contract: ; RV32I: # %bb.0: @@ -862,19 +755,12 @@ } define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmsub_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmsub_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmsub_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmsub_s_contract: ; RV32I: # %bb.0: @@ -932,23 +818,14 @@ } define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft2, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft2, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft2, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, ft2, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_contract: ; RV32I: # %bb.0: @@ -1027,21 +904,13 @@ } define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft1, ft0, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_contract: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll --- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ @@ -15,15 +15,10 @@ ; support rounding mode. define i32 @fcvt_w_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_w_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_w_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s: ; RV32I: # %bb.0: @@ -48,15 +43,10 @@ declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) define i32 @fcvt_wu_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_wu_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s: ; RV32I: # %bb.0: @@ -83,25 +73,15 @@ ; Test where the fptoui has multiple uses, one of which causes a sext to be ; inserted on RV64. define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind { -; RV32IF-LABEL: fcvt_wu_s_multiple_use: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: beqz a1, .LBB2_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: .LBB2_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_multiple_use: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: beqz a1, .LBB2_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: .LBB2_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_multiple_use: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a1, fa0, rtz +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: beqz a1, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_multiple_use: ; RV32I: # %bb.0: @@ -139,15 +119,10 @@ } define float @fcvt_s_w(i32 %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w: ; RV32I: # %bb.0: @@ -173,17 +148,11 @@ declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata) define float @fcvt_s_w_load(i32* %p) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_load: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lw a0, 0(a0) -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_load: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lw a0, 0(a0) -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_load: +; CHECK: # %bb.0: +; CHECK-NEXT: lw a0, 0(a0) +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_load: ; RV32I: # %bb.0: @@ -210,15 +179,10 @@ } define float @fcvt_s_wu(i32 %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu: ; RV32I: # %bb.0: @@ -429,15 +393,10 @@ declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata) define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i8: ; RV32I: # %bb.0: @@ -462,15 +421,10 @@ declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata) define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i8: ; RV32I: # %bb.0: @@ -495,15 +449,10 @@ declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata) define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i16: ; RV32I: # %bb.0: @@ -528,15 +477,10 @@ declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata) define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i16: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -1,23 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s define i32 @fcvt_w_s(float %a) nounwind { -; RV32IF-LABEL: fcvt_w_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_w_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s: ; RV32I: # %bb.0: @@ -41,23 +36,14 @@ } define i32 @fcvt_w_s_sat(float %a) nounwind { -; RV32IF-LABEL: fcvt_w_s_sat: -; RV32IF: # %bb.0: # %start -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB1_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: .LBB1_2: # %start -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_w_s_sat: -; RV64IF: # %bb.0: # %start -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB1_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: .LBB1_2: # %start -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s_sat: +; CHECK: # %bb.0: # %start +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: .LBB1_2: # %start +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s_sat: ; RV32I: # %bb.0: # %start @@ -159,15 +145,10 @@ declare i32 @llvm.fptosi.sat.i32.f32(float) define i32 @fcvt_wu_s(float %a) nounwind { -; RV32IF-LABEL: fcvt_wu_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s: ; RV32I: # %bb.0: @@ -193,25 +174,15 @@ ; Test where the fptoui has multiple uses, one of which causes a sext to be ; inserted on RV64. define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind { -; RV32IF-LABEL: fcvt_wu_s_multiple_use: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: beqz a1, .LBB3_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: .LBB3_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_multiple_use: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: beqz a1, .LBB3_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: .LBB3_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_multiple_use: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a1, fa0, rtz +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: beqz a1, .LBB3_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_multiple_use: ; RV32I: # %bb.0: @@ -249,23 +220,14 @@ } define i32 @fcvt_wu_s_sat(float %a) nounwind { -; RV32IF-LABEL: fcvt_wu_s_sat: -; RV32IF: # %bb.0: # %start -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB4_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: .LBB4_2: # %start -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_sat: -; RV64IF: # %bb.0: # %start -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB4_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: .LBB4_2: # %start -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_sat: +; CHECK: # %bb.0: # %start +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: .LBB4_2: # %start +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_sat: ; RV32I: # %bb.0: # %start @@ -343,17 +305,11 @@ declare i32 @llvm.fptoui.sat.i32.f32(float) define i32 @fmv_x_w(float %a, float %b) nounwind { -; RV32IF-LABEL: fmv_x_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fmv.x.w a0, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmv_x_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fmv.x.w a0, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmv_x_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fmv.x.w a0, ft0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmv_x_w: ; RV32I: # %bb.0: @@ -379,15 +335,10 @@ } define float @fcvt_s_w(i32 %a) nounwind { -; RV32IF-LABEL: fcvt_s_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w: ; RV32I: # %bb.0: @@ -412,17 +363,11 @@ } define float @fcvt_s_w_load(i32* %p) nounwind { -; RV32IF-LABEL: fcvt_s_w_load: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lw a0, 0(a0) -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_load: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lw a0, 0(a0) -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_load: +; CHECK: # %bb.0: +; CHECK-NEXT: lw a0, 0(a0) +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_load: ; RV32I: # %bb.0: @@ -449,15 +394,10 @@ } define float @fcvt_s_wu(i32 %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu: ; RV32I: # %bb.0: @@ -519,19 +459,12 @@ } define float @fmv_w_x(i32 %a, i32 %b) nounwind { -; RV32IF-LABEL: fmv_w_x: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: fmv.w.x ft1, a1 -; RV32IF-NEXT: fadd.s fa0, ft0, ft1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmv_w_x: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fmv.w.x ft1, a1 -; RV64IF-NEXT: fadd.s fa0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmv_w_x: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: fmv.w.x ft1, a1 +; CHECK-NEXT: fadd.s fa0, ft0, ft1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmv_w_x: ; RV32I: # %bb.0: @@ -1051,15 +984,10 @@ } define float @fcvt_s_w_i8(i8 signext %a) nounwind { -; RV32IF-LABEL: fcvt_s_w_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i8: ; RV32I: # %bb.0: @@ -1083,15 +1011,10 @@ } define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i8: ; RV32I: # %bb.0: @@ -1115,15 +1038,10 @@ } define float @fcvt_s_w_i16(i16 signext %a) nounwind { -; RV32IF-LABEL: fcvt_s_w_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i16: ; RV32I: # %bb.0: @@ -1147,15 +1065,10 @@ } define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_wu_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i16: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll --- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll @@ -1,25 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_oeq: ; RV32I: # %bb.0: @@ -47,21 +42,13 @@ declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata) define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ogt: ; RV32I: # %bb.0: @@ -88,21 +75,13 @@ } define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_oge: ; RV32I: # %bb.0: @@ -131,21 +110,13 @@ } define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_olt: ; RV32I: # %bb.0: @@ -172,21 +143,13 @@ } define i32 @fcmp_ole(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ole: ; RV32I: # %bb.0: @@ -215,31 +178,18 @@ ; FIXME: We only need one frflags before the two flts and one fsflags after the ; two flts. define i32 @fcmp_one(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a2, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: or a0, a2, a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a2, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: or a0, a2, a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_one: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a2, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: or a0, a2, a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_one: ; RV32I: # %bb.0: @@ -292,19 +242,12 @@ } define i32 @fcmp_ord(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ord: ; RV32I: # %bb.0: @@ -333,33 +276,19 @@ ; FIXME: We only need one frflags before the two flts and one fsflags after the ; two flts. define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a2, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: or a0, a2, a1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a2, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: or a0, a2, a1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a2, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: or a0, a2, a1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ueq: ; RV32I: # %bb.0: @@ -412,23 +341,14 @@ } define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: ; RV32I: # %bb.0: @@ -455,23 +375,14 @@ } define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: ; RV32I: # %bb.0: @@ -500,23 +411,14 @@ } define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: fle.s a1, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: fle.s a1, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: fle.s a1, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: ; RV32I: # %bb.0: @@ -543,23 +445,14 @@ } define i32 @fcmp_ule(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: ; RV32I: # %bb.0: @@ -586,17 +479,11 @@ } define i32 @fcmp_une(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_une: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_une: ; RV32I: # %bb.0: @@ -623,21 +510,13 @@ } define i32 @fcmp_uno(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_uno: ; RV32I: # %bb.0: @@ -664,19 +543,12 @@ } define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_oeq: ; RV32I: # %bb.0: @@ -704,15 +576,10 @@ declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata) define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ogt: ; RV32I: # %bb.0: @@ -739,15 +606,10 @@ } define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_oge: ; RV32I: # %bb.0: @@ -776,15 +638,10 @@ } define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_olt: ; RV32I: # %bb.0: @@ -811,15 +668,10 @@ } define i32 @fcmps_ole(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ole: ; RV32I: # %bb.0: @@ -846,19 +698,12 @@ } define i32 @fcmps_one(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_one: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_one: ; RV32I: # %bb.0: @@ -911,19 +756,12 @@ } define i32 @fcmps_ord(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa1 -; RV32IF-NEXT: fle.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa1 -; RV64IF-NEXT: fle.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa1 +; CHECK-NEXT: fle.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ord: ; RV32I: # %bb.0: @@ -950,21 +788,13 @@ } define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ueq: ; RV32I: # %bb.0: @@ -1017,17 +847,11 @@ } define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ugt: ; RV32I: # %bb.0: @@ -1054,17 +878,11 @@ } define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_uge: ; RV32I: # %bb.0: @@ -1093,17 +911,11 @@ } define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ult: ; RV32I: # %bb.0: @@ -1130,17 +942,11 @@ } define i32 @fcmps_ule(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_ule: ; RV32I: # %bb.0: @@ -1167,21 +973,13 @@ } define i32 @fcmps_une(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_une: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_une: ; RV32I: # %bb.0: @@ -1208,21 +1006,13 @@ } define i32 @fcmps_uno(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa1 -; RV32IF-NEXT: fle.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa1 -; RV64IF-NEXT: fle.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa1 +; CHECK-NEXT: fle.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmps_uno: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -1,23 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s define i32 @fcmp_false(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_false: -; RV32IF: # %bb.0: -; RV32IF-NEXT: li a0, 0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_false: -; RV64IF: # %bb.0: -; RV64IF-NEXT: li a0, 0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_false: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_false: ; RV32I: # %bb.0: @@ -34,15 +29,10 @@ } define i32 @fcmp_oeq(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_oeq: ; RV32I: # %bb.0: @@ -69,15 +59,10 @@ } define i32 @fcmp_ogt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ogt: ; RV32I: # %bb.0: @@ -104,15 +89,10 @@ } define i32 @fcmp_oge(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_oge: ; RV32I: # %bb.0: @@ -141,15 +121,10 @@ } define i32 @fcmp_olt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_olt: ; RV32I: # %bb.0: @@ -176,15 +151,10 @@ } define i32 @fcmp_ole(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ole: ; RV32I: # %bb.0: @@ -211,19 +181,12 @@ } define i32 @fcmp_one(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_one: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_one: ; RV32I: # %bb.0: @@ -276,19 +239,12 @@ } define i32 @fcmp_ord(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ord: ; RV32I: # %bb.0: @@ -315,21 +271,13 @@ } define i32 @fcmp_ueq(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ueq: ; RV32I: # %bb.0: @@ -382,17 +330,11 @@ } define i32 @fcmp_ugt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: ; RV32I: # %bb.0: @@ -419,17 +361,11 @@ } define i32 @fcmp_uge(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: ; RV32I: # %bb.0: @@ -458,17 +394,11 @@ } define i32 @fcmp_ult(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: ; RV32I: # %bb.0: @@ -495,17 +425,11 @@ } define i32 @fcmp_ule(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: ; RV32I: # %bb.0: @@ -532,17 +456,11 @@ } define i32 @fcmp_une(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_une: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_une: ; RV32I: # %bb.0: @@ -569,21 +487,13 @@ } define i32 @fcmp_uno(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_uno: ; RV32I: # %bb.0: @@ -610,15 +520,10 @@ } define i32 @fcmp_true(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_true: -; RV32IF: # %bb.0: -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_true: -; RV64IF: # %bb.0: -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_true: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fcmp_true: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll --- a/llvm/test/CodeGen/RISCV/float-imm.ll +++ b/llvm/test/CodeGen/RISCV/float-imm.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s ; TODO: constant pool shouldn't be necessary for RV64IF. define float @float_imm() nounwind { @@ -17,6 +17,11 @@ ; RV64IF-NEXT: lui a0, %hi(.LCPI0_0) ; RV64IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0) ; RV64IF-NEXT: ret +; CHECK-LABEL: float_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI0_0) +; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0) +; CHECK-NEXT: ret ret float 3.14159274101257324218750 } @@ -34,6 +39,12 @@ ; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV64IF-NEXT: fadd.s fa0, fa0, ft0 ; RV64IF-NEXT: ret +; CHECK-LABEL: float_imm_op: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI1_0) +; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a0) +; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: ret %1 = fadd float %a, 1.0 ret float %1 } diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll --- a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation \ ; RUN: | FileCheck -check-prefix=RV32I %s @@ -15,15 +15,10 @@ declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata) define float @sqrt_f32(float %a) nounwind strictfp { -; RV32IF-LABEL: sqrt_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: sqrt_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: sqrt_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; ; RV32I-LABEL: sqrt_f32: ; RV32I: # %bb.0: @@ -512,15 +507,10 @@ declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) define float @fma_f32(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fma_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fma_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fma_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fma_f32: ; RV32I: # %bb.0: @@ -546,15 +536,10 @@ declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata) define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmuladd_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmuladd_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmuladd_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; ; RV32I-LABEL: fmuladd_f32: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-isnan.ll b/llvm/test/CodeGen/RISCV/float-isnan.ll --- a/llvm/test/CodeGen/RISCV/float-isnan.ll +++ b/llvm/test/CodeGen/RISCV/float-isnan.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV32IF %s +; RUN: < %s | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV64IF %s +; RUN: < %s | FileCheck -check-prefixes=CHECK %s define zeroext i1 @float_is_nan(float %a) nounwind { ; RV32IF-LABEL: float_is_nan: @@ -16,6 +16,11 @@ ; RV64IF-NEXT: feq.s a0, fa0, fa0 ; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: ret +; CHECK-LABEL: float_is_nan: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret %1 = fcmp uno float %a, 0.000000e+00 ret i1 %1 } @@ -30,6 +35,10 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: feq.s a0, fa0, fa0 ; RV64IF-NEXT: ret +; CHECK-LABEL: float_not_nan: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: ret %1 = fcmp ord float %a, 0.000000e+00 ret i1 %1 } diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll --- a/llvm/test/CodeGen/RISCV/float-mem.ll +++ b/llvm/test/CodeGen/RISCV/float-mem.ll @@ -1,23 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s define dso_local float @flw(float *%a) nounwind { -; RV32IF-LABEL: flw: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flw ft0, 0(a0) -; RV32IF-NEXT: flw ft1, 12(a0) -; RV32IF-NEXT: fadd.s fa0, ft0, ft1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: flw: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flw ft0, 0(a0) -; RV64IF-NEXT: flw ft1, 12(a0) -; RV64IF-NEXT: fadd.s fa0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECK-LABEL: flw: +; CHECK: # %bb.0: +; CHECK-NEXT: flw ft0, 0(a0) +; CHECK-NEXT: flw ft1, 12(a0) +; CHECK-NEXT: fadd.s fa0, ft0, ft1 +; CHECK-NEXT: ret %1 = load float, float* %a %2 = getelementptr float, float* %a, i32 3 %3 = load float, float* %2 @@ -30,19 +23,12 @@ define dso_local void @fsw(float *%a, float %b, float %c) nounwind { ; Use %b and %c in an FP op to ensure floating point registers are used, even ; for the soft float ABI -; RV32IF-LABEL: fsw: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fsw ft0, 0(a0) -; RV32IF-NEXT: fsw ft0, 32(a0) -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fsw: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fsw ft0, 0(a0) -; RV64IF-NEXT: fsw ft0, 32(a0) -; RV64IF-NEXT: ret +; CHECK-LABEL: fsw: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fsw ft0, 0(a0) +; CHECK-NEXT: fsw ft0, 32(a0) +; CHECK-NEXT: ret %1 = fadd float %b, %c store float %1, float* %a %2 = getelementptr float, float* %a, i32 8 @@ -56,27 +42,16 @@ define dso_local float @flw_fsw_global(float %a, float %b) nounwind { ; Use %a and %b in an FP op to ensure floating point registers are used, even ; for the soft float ABI -; RV32IF-LABEL: flw_fsw_global: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: lui a0, %hi(G) -; RV32IF-NEXT: flw ft0, %lo(G)(a0) -; RV32IF-NEXT: fsw fa0, %lo(G)(a0) -; RV32IF-NEXT: addi a0, a0, %lo(G) -; RV32IF-NEXT: flw ft0, 36(a0) -; RV32IF-NEXT: fsw fa0, 36(a0) -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: flw_fsw_global: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: lui a0, %hi(G) -; RV64IF-NEXT: flw ft0, %lo(G)(a0) -; RV64IF-NEXT: fsw fa0, %lo(G)(a0) -; RV64IF-NEXT: addi a0, a0, %lo(G) -; RV64IF-NEXT: flw ft0, 36(a0) -; RV64IF-NEXT: fsw fa0, 36(a0) -; RV64IF-NEXT: ret +; CHECK-LABEL: flw_fsw_global: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: lui a0, %hi(G) +; CHECK-NEXT: flw ft0, %lo(G)(a0) +; CHECK-NEXT: fsw fa0, %lo(G)(a0) +; CHECK-NEXT: addi a0, a0, %lo(G) +; CHECK-NEXT: flw ft0, 36(a0) +; CHECK-NEXT: fsw fa0, 36(a0) +; CHECK-NEXT: ret %1 = fadd float %a, %b %2 = load volatile float, float* @G store float %1, float* @G diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -1,27 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s define signext i32 @test_floor_si32(float %x) { -; RV32IF-LABEL: test_floor_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB0_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV32IF-NEXT: .LBB0_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_floor_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB0_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV64IF-NEXT: .LBB0_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_floor_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rdn +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -98,23 +89,14 @@ } define signext i32 @test_floor_ui32(float %x) { -; RV32IF-LABEL: test_floor_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB2_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV32IF-NEXT: .LBB2_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_floor_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB2_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV64IF-NEXT: .LBB2_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_floor_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rdn +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -178,23 +160,14 @@ } define signext i32 @test_ceil_si32(float %x) { -; RV32IF-LABEL: test_ceil_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB4_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rup -; RV32IF-NEXT: .LBB4_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_ceil_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB4_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rup -; RV64IF-NEXT: .LBB4_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_ceil_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rup +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -271,23 +244,14 @@ } define signext i32 @test_ceil_ui32(float %x) { -; RV32IF-LABEL: test_ceil_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB6_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV32IF-NEXT: .LBB6_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_ceil_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB6_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV64IF-NEXT: .LBB6_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_ceil_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB6_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rup +; CHECK-NEXT: .LBB6_2: +; CHECK-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -351,23 +315,14 @@ } define signext i32 @test_trunc_si32(float %x) { -; RV32IF-LABEL: test_trunc_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB8_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: .LBB8_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_trunc_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB8_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: .LBB8_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_trunc_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB8_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: .LBB8_2: +; CHECK-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -444,23 +399,14 @@ } define signext i32 @test_trunc_ui32(float %x) { -; RV32IF-LABEL: test_trunc_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB10_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: .LBB10_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_trunc_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB10_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: .LBB10_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_trunc_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: .LBB10_2: +; CHECK-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -524,23 +470,14 @@ } define signext i32 @test_round_si32(float %x) { -; RV32IF-LABEL: test_round_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB12_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV32IF-NEXT: .LBB12_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_round_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB12_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV64IF-NEXT: .LBB12_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_round_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB12_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rmm +; CHECK-NEXT: .LBB12_2: +; CHECK-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -617,23 +554,14 @@ } define signext i32 @test_round_ui32(float %x) { -; RV32IF-LABEL: test_round_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB14_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV32IF-NEXT: .LBB14_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_round_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB14_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV64IF-NEXT: .LBB14_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_round_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB14_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rmm +; CHECK-NEXT: .LBB14_2: +; CHECK-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -697,23 +625,14 @@ } define signext i32 @test_roundeven_si32(float %x) { -; RV32IF-LABEL: test_roundeven_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB16_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rne -; RV32IF-NEXT: .LBB16_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_roundeven_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB16_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rne -; RV64IF-NEXT: .LBB16_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_roundeven_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB16_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rne +; CHECK-NEXT: .LBB16_2: +; CHECK-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -790,23 +709,14 @@ } define signext i32 @test_roundeven_ui32(float %x) { -; RV32IF-LABEL: test_roundeven_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB18_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV32IF-NEXT: .LBB18_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: test_roundeven_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB18_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV64IF-NEXT: .LBB18_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: test_roundeven_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB18_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rne +; CHECK-NEXT: .LBB18_2: +; CHECK-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF %s define float @select_fcmp_false(float %a, float %b) nounwind { ; RV32IF-LABEL: select_fcmp_false: @@ -14,6 +14,10 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_false: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: ret %1 = fcmp false float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -37,6 +41,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB1_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_oeq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB1_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB1_2: +; CHECKIF-NEXT: ret %1 = fcmp oeq float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -60,6 +72,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB2_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ogt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa1, fa0 +; CHECKIF-NEXT: bnez a0, .LBB2_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB2_2: +; CHECKIF-NEXT: ret %1 = fcmp ogt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -83,6 +103,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB3_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_oge: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa1, fa0 +; CHECKIF-NEXT: bnez a0, .LBB3_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB3_2: +; CHECKIF-NEXT: ret %1 = fcmp oge float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -106,6 +134,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB4_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_olt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB4_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB4_2: +; CHECKIF-NEXT: ret %1 = fcmp olt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -129,6 +165,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB5_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ole: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB5_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB5_2: +; CHECKIF-NEXT: ret %1 = fcmp ole float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -156,6 +200,16 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB6_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_one: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: flt.s a1, fa1, fa0 +; CHECKIF-NEXT: or a0, a1, a0 +; CHECKIF-NEXT: bnez a0, .LBB6_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB6_2: +; CHECKIF-NEXT: ret %1 = fcmp one float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -183,6 +237,16 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB7_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ord: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa1, fa1 +; CHECKIF-NEXT: feq.s a1, fa0, fa0 +; CHECKIF-NEXT: and a0, a1, a0 +; CHECKIF-NEXT: bnez a0, .LBB7_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB7_2: +; CHECKIF-NEXT: ret %1 = fcmp ord float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -210,6 +274,16 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB8_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ueq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: flt.s a1, fa1, fa0 +; CHECKIF-NEXT: or a0, a1, a0 +; CHECKIF-NEXT: beqz a0, .LBB8_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB8_2: +; CHECKIF-NEXT: ret %1 = fcmp ueq float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -233,6 +307,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB9_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ugt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB9_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB9_2: +; CHECKIF-NEXT: ret %1 = fcmp ugt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -256,6 +338,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB10_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_uge: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB10_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB10_2: +; CHECKIF-NEXT: ret %1 = fcmp uge float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -279,6 +369,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB11_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ult: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa1, fa0 +; CHECKIF-NEXT: beqz a0, .LBB11_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB11_2: +; CHECKIF-NEXT: ret %1 = fcmp ult float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -302,6 +400,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB12_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ule: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa1, fa0 +; CHECKIF-NEXT: beqz a0, .LBB12_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB12_2: +; CHECKIF-NEXT: ret %1 = fcmp ule float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -325,6 +431,14 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB13_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_une: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB13_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB13_2: +; CHECKIF-NEXT: ret %1 = fcmp une float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -352,6 +466,16 @@ ; RV64IF-NEXT: fmv.s fa0, fa1 ; RV64IF-NEXT: .LBB14_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_uno: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa1, fa1 +; CHECKIF-NEXT: feq.s a1, fa0, fa0 +; CHECKIF-NEXT: and a0, a1, a0 +; CHECKIF-NEXT: beqz a0, .LBB14_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB14_2: +; CHECKIF-NEXT: ret %1 = fcmp uno float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -365,6 +489,9 @@ ; RV64IF-LABEL: select_fcmp_true: ; RV64IF: # %bb.0: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_true: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: ret %1 = fcmp true float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -389,6 +516,14 @@ ; RV64IF-NEXT: mv a0, a1 ; RV64IF-NEXT: .LBB16_2: ; RV64IF-NEXT: ret +; CHECKIF-LABEL: i32_select_fcmp_oeq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a2, fa0, fa1 +; CHECKIF-NEXT: bnez a2, .LBB16_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: mv a0, a1 +; CHECKIF-NEXT: .LBB16_2: +; CHECKIF-NEXT: ret %1 = fcmp oeq float %a, %b %2 = select i1 %1, i32 %c, i32 %d ret i32 %2