Index: lib/Basic/Targets.cpp =================================================================== --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -2981,7 +2981,8 @@ else if (SSELevel > NoSSE) MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); - SimdDefaultAlign = + // We now know the features we have: we can decide how to align vectors. + MaxVectorAlign = SimdDefaultAlign = hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; return true; } @@ -3632,17 +3633,6 @@ DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; HasAlignMac68kSupport = true; } - - bool handleTargetFeatures(std::vector &Features, - DiagnosticsEngine &Diags) override { - if (!DarwinTargetInfo::handleTargetFeatures(Features, - Diags)) - return false; - // We now know the features we have: we can decide how to align vectors. - MaxVectorAlign = - hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; - return true; - } }; // x86-32 Windows target @@ -3999,17 +3989,6 @@ UseSignedCharForObjCBool = false; DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; } - - bool handleTargetFeatures(std::vector &Features, - DiagnosticsEngine &Diags) override { - if (!DarwinTargetInfo::handleTargetFeatures(Features, - Diags)) - return false; - // We now know the features we have: we can decide how to align vectors. - MaxVectorAlign = - hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; - return true; - } }; class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo { Index: test/CodeGen/const-init.c =================================================================== --- test/CodeGen/const-init.c +++ test/CodeGen/const-init.c @@ -139,7 +139,7 @@ typedef long double v2f80 __attribute((vector_size(24))); // CHECK: @g28.a = internal global <1 x i64> // CHECK: @g28.b = internal global <12 x i16> - // CHECK: @g28.c = internal global <2 x x86_fp80> , align 32 + // CHECK: @g28.c = internal global <2 x x86_fp80> , align 16 static v1i64 a = (v1i64)10LL; static v12i16 b = (v2f80){1,2}; static v2f80 c = (v12i16){0,0,0,-32768,16383,0,0,0,0,-32768,16384,0}; Index: test/CodeGen/vector-alignment.c =================================================================== --- test/CodeGen/vector-alignment.c +++ test/CodeGen/vector-alignment.c @@ -1,61 +0,0 @@ -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 -target-feature +avx \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx512f \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 -target-feature +avx512f \ -// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 -// rdar://11759609 - -// At or below target max alignment with no aligned attribute should align based -// on the size of vector. -double __attribute__((vector_size(16))) v1; -// SSE: @v1 {{.*}}, align 16 -// AVX: @v1 {{.*}}, align 16 -// AVX512: @v1 {{.*}}, align 16 -double __attribute__((vector_size(32))) v2; -// SSE: @v2 {{.*}}, align 16 -// AVX: @v2 {{.*}}, align 32 -// AVX512: @v2 {{.*}}, align 32 - -// Alignment above target max alignment with no aligned attribute should align -// based on the target max. -double __attribute__((vector_size(64))) v3; -// SSE: @v3 {{.*}}, align 16 -// AVX: @v3 {{.*}}, align 32 -// AVX512: @v3 {{.*}}, align 64 -double __attribute__((vector_size(1024))) v4; -// SSE: @v4 {{.*}}, align 16 -// AVX: @v4 {{.*}}, align 32 -// AVX512: @v4 {{.*}}, align 64 - -// Aliged attribute should always override. -double __attribute__((vector_size(16), aligned(16))) v5; -// ALL: @v5 {{.*}}, align 16 -double __attribute__((vector_size(16), aligned(64))) v6; -// ALL: @v6 {{.*}}, align 64 -double __attribute__((vector_size(32), aligned(16))) v7; -// ALL: @v7 {{.*}}, align 16 -double __attribute__((vector_size(32), aligned(64))) v8; -// ALL: @v8 {{.*}}, align 64 - -// Check non-power of 2 widths. -double __attribute__((vector_size(24))) v9; -// SSE: @v9 {{.*}}, align 16 -// AVX: @v9 {{.*}}, align 32 -// AVX512: @v9 {{.*}}, align 32 -double __attribute__((vector_size(40))) v10; -// SSE: @v10 {{.*}}, align 16 -// AVX: @v10 {{.*}}, align 32 -// AVX512: @v10 {{.*}}, align 64 - -// Check non-power of 2 widths with aligned attribute. -double __attribute__((vector_size(24), aligned(64))) v11; -// ALL: @v11 {{.*}}, align 64 -double __attribute__((vector_size(80), aligned(16))) v12; -// ALL: @v12 {{.*}}, align 16 Index: test/CodeGen/x86-vector-alignment.c =================================================================== --- test/CodeGen/x86-vector-alignment.c +++ test/CodeGen/x86-vector-alignment.c @@ -1,16 +1,15 @@ -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 \ +// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 \ +// RUN: %clang_cc1 -w -triple i386-unknown-unknown \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx \ +// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown -target-feature +avx \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 -target-feature +avx \ +// RUN: %clang_cc1 -w -triple i386-unknown-unknown -target-feature +avx \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX -// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx512f \ +// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown -target-feature +avx512f \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 -// RUN: %clang_cc1 -w -triple i386-apple-darwin10 -target-feature +avx512f \ +// RUN: %clang_cc1 -w -triple i386-unknown-unknown -target-feature +avx512f \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 -// rdar://11759609 // At or below target max alignment with no aligned attribute should align based // on the size of vector. Index: test/CodeGen/x86_64-arguments.c =================================================================== --- test/CodeGen/x86_64-arguments.c +++ test/CodeGen/x86_64-arguments.c @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | \ // RUN: FileCheck %s -check-prefix=CHECK -check-prefix=SSE -check-prefix=NO-AVX512 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | \ -// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=NO-AVX512 +// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=AVXUP -check-prefix=NO-AVX512 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx512f | \ -// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=AVX512 +// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVXUP -check-prefix=AVX512 #include // CHECK-LABEL: define signext i8 @f0() @@ -197,7 +197,7 @@ }; struct v8f32wrapper f27a(struct v8f32wrapper X) { - // AVX-LABEL: define <8 x float> @f27a(<8 x float> %X.coerce) + // AVXUP-LABEL: define <8 x float> @f27a(<8 x float> %X.coerce) return X; } @@ -206,7 +206,7 @@ }; struct v8f32wrapper_wrapper f27b(struct v8f32wrapper_wrapper X) { - // AVX-LABEL: define <8 x float> @f27b(<8 x float> %X.coerce) + // AVXUP-LABEL: define <8 x float> @f27b(<8 x float> %X.coerce) return X; } @@ -290,10 +290,10 @@ typedef unsigned v2i32 __attribute((__vector_size__(8))); v2i32 f36(v2i32 arg) { return arg; } -// AVX: declare void @f38(<8 x float>) -// AVX: declare void @f37(<8 x float>) -// SSE: declare void @f38(%struct.s256* byval align 32) -// SSE: declare void @f37(<8 x float>* byval align 32) +// AVXUP: declare void @f38(<8 x float>) +// AVXUP: declare void @f37(<8 x float>) +// SSE: declare void @f38(%struct.s256* byval align 16) +// SSE: declare void @f37(<8 x float>* byval align 16) typedef float __m256 __attribute__ ((__vector_size__ (32))); typedef struct { __m256 m; @@ -336,7 +336,8 @@ // CHECK-LABEL: define i32 @f44 // CHECK: ptrtoint -// CHECK-NEXT: and {{.*}}, -32 +// SSE-NEXT: and {{.*}}, -16 +// AVXUP-NEXT: and {{.*}}, -32 // CHECK-NEXT: inttoptr typedef int T44 __attribute((vector_size(32))); struct s44 { T44 x; int y; }; @@ -349,7 +350,7 @@ } // Text that vec3 returns the correct LLVM IR type. -// AVX-LABEL: define i32 @foo(<3 x i64> %X) +// AVXUP-LABEL: define i32 @foo(<3 x i64> %X) typedef long long3 __attribute((ext_vector_type(3))); int foo(long3 X) { @@ -358,8 +359,8 @@ // Make sure we don't use a varargs convention for a function without a // prototype where AVX types are involved. -// AVX: @test45 -// AVX: call i32 bitcast (i32 (...)* @f45 to i32 (<8 x float>)*) +// AVXUP: @test45 +// AVXUP: call i32 bitcast (i32 (...)* @f45 to i32 (<8 x float>)*) int f45(); __m256 x45; void test45() { f45(x45); } @@ -443,14 +444,14 @@ void test52() { test52_helper(0, x52, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); } -// AVX: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) +// AVXUP: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) void test53(__m256 *m, __builtin_va_list argList) { *m = __builtin_va_arg(argList, __m256); } -// AVX-LABEL: define void @test53 -// AVX-NOT: br i1 -// AVX: ret void +// AVXUP-LABEL: define void @test53 +// AVXUP-NOT: br i1 +// AVXUP: ret void void test54_helper(__m256, ...); __m256 x54; @@ -458,8 +459,8 @@ test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); } -// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) -// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval align 8 {{%[a-zA-Z0-9]+}}) +// AVXUP: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) +// AVXUP: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval align 8 {{%[a-zA-Z0-9]+}}) typedef float __m512 __attribute__ ((__vector_size__ (64))); typedef struct { @@ -472,20 +473,24 @@ // Even on AVX512, aggregates of size larger than four eightbytes have class // MEMORY (AVX512 draft 0.3 3.2.3p2 Rule 1). // -// CHECK: declare void @f55(%struct.s512* byval align 64) +// SSE: declare void @f55(%struct.s512* byval align 16) +// AVX: declare void @f55(%struct.s512* byval align 32) +// AVX512: declare void @f55(%struct.s512* byval align 64) void f55(s512 x); // However, __m512 has type SSE/SSEUP on AVX512. // +// SSE: declare void @f56(<16 x float>* byval align 16) +// AVX: declare void @f56(<16 x float>* byval align 32) // AVX512: declare void @f56(<16 x float>) -// NO-AVX512: declare void @f56(<16 x float>* byval align 64) void f56(__m512 x); void f57() { f55(x55); f56(x56); } // Like for __m128 on AVX, check that the struct below is passed // in the same way regardless of AVX512 being used. // -// CHECK: declare void @f58(%struct.t256* byval align 32) +// SSE: declare void @f58(%struct.t256* byval align 16) +// AVXUP: declare void @f58(%struct.t256* byval align 32) typedef struct t256 { __m256 m; __m256 n; @@ -496,7 +501,8 @@ f58(s); } -// CHECK: declare void @f60(%struct.sat256* byval align 32) +// SSE: declare void @f60(%struct.sat256* byval align 16) +// AVXUP: declare void @f60(%struct.sat256* byval align 32) typedef struct at256 { __m256 array[2]; } Atwo256;