diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -1132,8 +1132,8 @@
 
   /// Return a BitVector marking all sub or super registers of \p Reg, including
   /// itself.
-  virtual const BitVector &getAliases(MCPhysReg Reg,
-                                      bool OnlySmaller = false) const;
+  virtual const BitVector &getAliases(MCPhysReg Reg, bool OnlySmaller = false,
+                                      bool Cache = true) const;
 
   /// Change \p Regs setting all registers used to pass parameters according
   /// to the host abi. Do nothing if not implemented.
diff --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp
--- a/bolt/lib/Core/MCPlusBuilder.cpp
+++ b/bolt/lib/Core/MCPlusBuilder.cpp
@@ -439,17 +439,22 @@
   return false;
 }
 
-const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
-                                           bool OnlySmaller) const {
+const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg, bool OnlySmaller,
+                                           bool Cache) const {
   // AliasMap caches a mapping of registers to the set of registers that
   // alias (are sub or superregs of itself, including itself).
   static std::vector<BitVector> AliasMap;
   static std::vector<BitVector> SmallerAliasMap;
 
-  if (AliasMap.size() > 0) {
-    if (OnlySmaller)
-      return SmallerAliasMap[Reg];
-    return AliasMap[Reg];
+  if (Cache) {
+    if (AliasMap.size() > 0) {
+      if (OnlySmaller)
+        return SmallerAliasMap[Reg];
+      return AliasMap[Reg];
+    }
+  } else {
+    AliasMap.clear();
+    SmallerAliasMap.clear();
   }
 
   // Build alias map
diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp
--- a/bolt/unittests/Core/MCPlusBuilder.cpp
+++ b/bolt/unittests/Core/MCPlusBuilder.cpp
@@ -62,7 +62,8 @@
     if (GetParam() != Arch)
       GTEST_SKIP();
 
-    const BitVector &BV = BC->MIB->getAliases(Register, OnlySmaller);
+    const BitVector &BV =
+        BC->MIB->getAliases(Register, OnlySmaller, /* Cache = */ false);
     ASSERT_EQ(BV.count(), Count);
     for (size_t I = 0; I < Count; ++I)
       ASSERT_TRUE(BV[Aliases[I]]);