Index: llvm/test/Transforms/SLPVectorizer/X86/slp-reduc-fma-loss.ll
===================================================================
--- /dev/null
+++ llvm/test/Transforms/SLPVectorizer/X86/slp-reduc-fma-loss.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -S -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; This test checks for a case when a horizontal reduction of floating-point
+; adds may look profitable, but is not because it eliminates generation of
+; floating-point FMAs that would be more profitable.
+; FIXME: We currently generate the horizontal reduction.
+
+define void @foo() #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[OP_RDX:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[CVT0:%.*]] = uitofp i16 undef to double
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fmul fast <4 x double> poison, [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> [[TMP2]])
+; CHECK-NEXT:    [[OP_RDX]] = fadd fast double [[TMP3]], [[PHI0]]
+; CHECK-NEXT:    br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+  br label %loop
+
+loop:
+  %phi0 = phi double [ 0.000000e+00, %0 ], [ %add3, %loop ]
+  %cvt0 = uitofp i16 undef to double
+  %mul0 = fmul fast double undef, %cvt0
+  %add0 = fadd fast double %mul0, %phi0
+  %mul1 = fmul fast double undef, undef
+  %add1 = fadd fast double %mul1, %add0
+  %mul2 = fmul fast double undef, undef
+  %add2 = fadd fast double %mul2, %add1
+  %mul3 = fmul fast double undef, undef
+  %add3 = fadd fast double %mul3, %add2
+  br i1 undef, label %exit, label %loop
+
+exit:
+  ret void
+}