diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
--- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -278,18 +278,32 @@
 }
 
 let DecoderNamespace = "MicroMips",  DecoderMethod = "DecodeFMemMMR2" in {
-  def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
-                LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 {
+  def LDC1_MM_D32 : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
+                    LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 {
     let BaseOpcode = "LDC132";
   }
-  def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
-                LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32;
+  def SDC1_MM_D32 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
+                    LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32 {
+    let BaseOpcode = "SDC164";
+  }
   def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
                 LW_FM_MM<0x27>, ISA_MICROMIPS;
   def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
                 LW_FM_MM<0x26>, ISA_MICROMIPS;
 }
 
+let DecoderNamespace = "Mips64", DecoderMethod = "DecodeFMemMMR2" in {
+  def LDC1_MM_D64 : MMRel, LW_FT<"ldc1", FGR64Opnd, mem_mm_16, II_LDC1, load>,
+                    LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_64 {
+    let BaseOpcode = "LDC164";
+  }
+  def SDC1_MM_D64 : MMRel, SW_FT<"sdc1", FGR64Opnd, mem_mm_16, II_SDC1, store>,
+                    LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_64 {
+    let BaseOpcode = "SDC164";
+  }
+}
+
+
 multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
                      InstrItinClass itin> {
   def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
@@ -400,8 +414,10 @@
 
 // Patterns for loads/stores with a reg+imm operand.
 let AddedComplexity = 40 in {
-  def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32;
-  def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32;
+  def : LoadRegImmPat<LDC1_MM_D32, f64, load>, ISA_MICROMIPS, FGR_32;
+  def : StoreRegImmPat<SDC1_MM_D32, f64>, ISA_MICROMIPS, FGR_32;
+  def : LoadRegImmPat<LDC1_MM_D64, f64, load>, ISA_MICROMIPS, FGR_64;
+  def : StoreRegImmPat<SDC1_MM_D64, f64>, ISA_MICROMIPS, FGR_64;
   def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS;
   def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS;
 }
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -957,13 +957,13 @@
 def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32_MM, RECIP_D64_MM,
                                      RSQRT_D32_MM, RSQRT_D64_MM)>;
 
-def : InstRW<[GenericWriteFPUStore], (instrs SDC1_MM, SWC1_MM, SUXC1_MM,
-                                      SWXC1_MM)>;
+def : InstRW<[GenericWriteFPUStore], (instrs SDC1_MM_D32, SDC1_MM_D64, SWC1_MM,
+                                      SUXC1_MM, SWXC1_MM)>;
 
 def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs CFC1_MM, CTC1_MM)>;
 
-def : InstRW<[GenericWriteFPULoad], (instrs LDC1_MM, LUXC1_MM, LWC1_MM,
-                                     LWXC1_MM)>;
+def : InstRW<[GenericWriteFPULoad], (instrs LDC1_MM_D32, LDC1_MM_D64, LUXC1_MM,
+                                     LWC1_MM, LWXC1_MM)>;
 
 // microMIPS32r6
 // =============
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load.ll b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
--- a/llvm/test/CodeGen/Mips/llvm-ir/load.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
@@ -6,13 +6,21 @@
 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3
 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
 ; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP64
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP643
 
-; Test subword and word loads.
+; Test subword and word loads. We use -asm-show-inst to test that the produced
+; instructions match the expected ISA.
+
+; NOTE: As the -asm-show-inst shows the internal numbering of instructions
+;       and registers, these numbers have been replaced with wildcard regexes.
 
 @a = common global i8 0, align 4
 @b = common global i16 0, align 4
 @c = common global i32 0, align 4
 @d = common global i64 0, align 8
+@e = common global float 0.0, align 4
+@f = common global double 0.0, align 8
 
 define i8 @f1() {
 ; MIPS32-LABEL: f1:
@@ -29,7 +37,7 @@
 ;
 ; MMR3-LABEL: f1:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -54,7 +62,7 @@
 ;
 ; MMR6-LABEL: f1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
@@ -148,6 +156,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR5FP64-LABEL: f1:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R5FP643-LABEL: f1:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
 entry:
   %0 = load i8, i8 * @a
   ret i8 %0
@@ -168,7 +200,7 @@
 ;
 ; MMR3-LABEL: f2:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -193,7 +225,7 @@
 ;
 ; MMR6-LABEL: f2:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
@@ -287,6 +319,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR5FP64-LABEL: f2:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R5FP643-LABEL: f2:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
 entry:
   %0 = load i8, i8 * @a
   %1 = sext i8 %0 to i32
@@ -308,7 +364,7 @@
 ;
 ; MMR3-LABEL: f3:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -333,7 +389,7 @@
 ;
 ; MMR6-LABEL: f3:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
@@ -427,6 +483,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR5FP64-LABEL: f3:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R5FP643-LABEL: f3:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
 entry:
   %0 = load i16, i16 * @b
   ret i16 %0
@@ -447,7 +527,7 @@
 ;
 ; MMR3-LABEL: f4:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -472,7 +552,7 @@
 ;
 ; MMR6-LABEL: f4:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
@@ -566,6 +646,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR5FP64-LABEL: f4:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R5FP643-LABEL: f4:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
 entry:
   %0 = load i16, i16 * @b
   %1 = sext i16 %0 to i32
@@ -587,7 +691,7 @@
 ;
 ; MMR3-LABEL: f5:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -612,7 +716,7 @@
 ;
 ; MMR6-LABEL: f5:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
@@ -706,6 +810,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR5FP64-LABEL: f5:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R5FP643-LABEL: f5:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
 entry:
   %0 = load i32, i32 * @c
   ret i32 %0
@@ -730,7 +858,7 @@
 ;
 ; MMR3-LABEL: f6:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR3-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
@@ -762,7 +890,7 @@
 ;
 ; MMR6-LABEL: f6:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
@@ -859,6 +987,37 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR5FP64-LABEL: f6:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR5FP64-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Imm:0>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R5FP643-LABEL: f6:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R5FP643-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Imm:0>>
 entry:
   %0 = load i32, i32 * @c
   %1 = zext i32 %0 to i64
@@ -884,7 +1043,7 @@
 ;
 ; MMR3-LABEL: f7:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
@@ -917,7 +1076,7 @@
 ;
 ; MMR6-LABEL: f7:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
@@ -1015,8 +1174,366 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR5FP64-LABEL: f7:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR5FP64-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Imm:31>>
+;
+; MIPS32R5FP643-LABEL: f7:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R5FP643-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Imm:31>>
 entry:
   %0 = load i32, i32 * @c
   %1 = sext i32 %0 to i64
   ret i64 %1
 }
+
+define float @f8() {
+; MIPS32-LABEL: f8:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR3-LABEL: f8:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR3-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS32R6-LABEL: f8:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR6-LABEL: f8:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+;
+; MIPS3-LABEL: f8:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(e))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(e))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS3-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS64-LABEL: f8:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(e))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(e))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS64R6-LABEL: f8:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(e))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(e))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64R6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR5FP64-LABEL: f8:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS32R5FP643-LABEL: f8:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(e))>>
+entry:
+  %0 = load float, float * @e
+  ret float %0
+}
+
+define double @f9() {
+; MIPS32-LABEL: f9:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR3-LABEL: f9:
+; MMR3:       # %bb.0: # %entry
+; MMR3-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR3-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D32
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS32R6-LABEL: f9:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR6-LABEL: f9:
+; MMR6:       # %bb.0: # %entry
+; MMR6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_D64_MMR6
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+;
+; MIPS3-LABEL: f9:
+; MIPS3:       # %bb.0: # %entry
+; MIPS3-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%highest(f))>>
+; MIPS3-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%higher(f))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Imm:16>>
+; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS3-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS64-LABEL: f9:
+; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%highest(f))>>
+; MIPS64-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%higher(f))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Imm:16>>
+; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS64R6-LABEL: f9:
+; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(f))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(f))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64R6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR5FP64-LABEL: f9:
+; MMR5FP64:       # %bb.0: # %entry
+; MMR5FP64-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D64
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS32R5FP643-LABEL: f9:
+; MIPS32R5FP643:       # %bb.0: # %entry
+; MIPS32R5FP643-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(f))>>
+entry:
+  %0 = load double, double * @f
+  ret double %0
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
--- a/llvm/test/CodeGen/Mips/llvm-ir/store.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
@@ -5,13 +5,21 @@
 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
 ; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP64
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP643
 
-; Test subword and word stores.
+; Test subword and word stores. We use -asm-show-inst to test that the produced
+; instructions match the expected ISA.
+
+; NOTE: As the -asm-show-inst shows the internal numbering of instructions
+;       and registers, these numbers have been replaced with wildcard regexes.
 
 @a = common global i8 0, align 4
 @b = common global i16 0, align 4
 @c = common global i32 0, align 4
 @d = common global i64 0, align 8
+@e = common global float 0.0, align 4
+@f = common global double 0.0, align 8
 
 define void @f1(i8 %a) {
 ; MIPS32-LABEL: f1:
@@ -28,7 +36,7 @@
 ;
 ; MMR3-LABEL: f1:
 ; MMR3:       # %bb.0:
-; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -53,7 +61,7 @@
 ;
 ; MMR6-LABEL: f1:
 ; MMR6:       # %bb.0:
-; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
@@ -119,6 +127,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MMR5FP64-LABEL: f1:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
+;
+; MIPS32R5FP643-LABEL: f1:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
   store i8 %a, i8 * @a
   ret void
 }
@@ -138,7 +170,7 @@
 ;
 ; MMR3-LABEL: f2:
 ; MMR3:       # %bb.0:
-; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -163,7 +195,7 @@
 ;
 ; MMR6-LABEL: f2:
 ; MMR6:       # %bb.0:
-; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
@@ -229,6 +261,30 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MMR5FP64-LABEL: f2:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
+;
+; MIPS32R5FP643-LABEL: f2:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
   store i16 %a, i16 * @b
   ret void
 }
@@ -248,7 +304,7 @@
 ;
 ; MMR3-LABEL: f3:
 ; MMR3:       # %bb.0:
-; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
@@ -273,7 +329,7 @@
 ;
 ; MMR6-LABEL: f3:
 ; MMR6:       # %bb.0:
-; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
@@ -306,7 +362,7 @@
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS4-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
 ; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%lo(c))>>
@@ -335,10 +391,34 @@
 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS64R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MMR5FP64-LABEL: f3:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
+;
+; MIPS32R5FP643-LABEL: f3:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
   store i32 %a, i32 * @c
   ret void
 }
@@ -366,14 +446,14 @@
 ;
 ; MMR3-LABEL: f4:
 ; MMR3:       # %bb.0:
-; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MMR3-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
-; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
@@ -407,14 +487,14 @@
 ;
 ; MMR6-LABEL: f4:
 ; MMR6:       # %bb.0:
-; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MMR6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
-; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
@@ -481,6 +561,314 @@
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
+;
+; MMR5FP64-LABEL: f4:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MMR5FP64-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR5FP64-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MMR5FP64-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Imm:4>>
+; MMR5FP64-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+;
+; MIPS32R5FP643-LABEL: f4:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(d))>>
+; MIPS32R5FP643-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32R5FP643-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(d))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Imm:4>>
   store i64 %a, i64 * @d
   ret void
 }
+
+define void @f5(float %e) {
+; MIPS32-LABEL: f5:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR3-LABEL: f5:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR3-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS32R6-LABEL: f5:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR6-LABEL: f5:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+;
+; MIPS4-LABEL: f5:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(e))>>
+; MIPS4-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(e))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS4-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS64R6-LABEL: f5:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(e))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(e))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64R6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MMR5FP64-LABEL: f5:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(e))>>
+;
+; MIPS32R5FP643-LABEL: f5:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(e))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(e))>>
+  store float %e, float * @e
+  ret void
+}
+
+define void @f6(double %f) {
+; MIPS32-LABEL: f6:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR3-LABEL: f6:
+; MMR3:       # %bb.0:
+; MMR3-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR3-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D32
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS32R6-LABEL: f6:
+; MIPS32R6:       # %bb.0:
+; MIPS32R6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR6-LABEL: f6:
+; MMR6:       # %bb.0:
+; MMR6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_D64_MMR6
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+;
+; MIPS4-LABEL: f6:
+; MIPS4:       # %bb.0:
+; MIPS4-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%highest(f))>>
+; MIPS4-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%higher(f))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Imm:16>>
+; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS4-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS64R6-LABEL: f6:
+; MIPS64R6:       # %bb.0:
+; MIPS64R6-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(f))>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(f))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
+; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS64R6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MMR5FP64-LABEL: f6:
+; MMR5FP64:       # %bb.0:
+; MMR5FP64-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D64
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(f))>>
+;
+; MIPS32R5FP643-LABEL: f6:
+; MIPS32R5FP643:       # %bb.0:
+; MIPS32R5FP643-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(f))>>
+; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
+; MIPS32R5FP643-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(f))>>
+  store double %f, double * @f
+  ret void
+}
diff --git a/llvm/test/CodeGen/Mips/pr49200.ll b/llvm/test/CodeGen/Mips/pr49200.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/pr49200.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-unknown-linux-musl-gnu < %s | FileCheck %s
+
+; Check that in microMIPSr5 with a 64 bit fpu configuration, the following
+; code can be compiled. This previously failed due to missing load/store
+; patterns and instructions to handle the 64 bit FPU case for microMIPS.
+
+%union.anon = type { { double, double } }
+
+define dso_local void @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiusp -24
+; CHECK-NEXT:    li16 $2, 0
+; CHECK-NEXT:    sw $2, 4($sp)
+; CHECK-NEXT:    sw $2, 0($sp)
+; CHECK-NEXT:    sw $2, 12($sp)
+; CHECK-NEXT:    sw $2, 8($sp)
+; CHECK-NEXT:    ldc1 $f0, 0($sp)
+; CHECK-NEXT:    sdc1 $f0, 16($sp)
+; CHECK-NEXT:    addiusp 24
+; CHECK-NEXT:    jrc $ra
+entry:
+  %bleh = alloca double, align 8
+  %.compoundliteral = alloca %union.anon, align 8
+  %arrayinit.begin = getelementptr inbounds [2 x double], ptr %.compoundliteral, i32 0, i32 0
+  store double 0.000000e+00, ptr %arrayinit.begin, align 8
+  %arrayinit.element = getelementptr inbounds double, ptr %arrayinit.begin, i32 1
+  store double 0.000000e+00, ptr %arrayinit.element, align 8
+  %.compoundliteral.realp = getelementptr inbounds { double, double }, ptr %.compoundliteral, i32 0, i32 0
+  %.compoundliteral.real = load double, ptr %.compoundliteral.realp, align 8
+  store double %.compoundliteral.real, ptr %bleh, align 8
+  ret void
+}
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="mips32r5" "target-features"="+dspr2,+fp64,+mips32r5,-noabicalls,+micromips" }