diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -143,9 +143,13 @@
   /// Indicate that this basic block is entered via an exception handler.
   bool IsEHPad = false;
 
-  /// Indicate that this basic block is potentially the target of an indirect
-  /// branch.
-  bool AddressTaken = false;
+  /// Indicate that this MachineBasicBlock is referenced somewhere other than
+  /// as predecessor/successor, a terminator MachineInstr, or a jump table.
+  bool MachineBlockAddressTaken = false;
+
+  /// Indicate that this basic block is the MachineBasicBlock which corresponds
+  /// to an IR-level "blockaddress" constant.
+  bool IRBlockAddressTaken = false;
 
   /// Indicate that this basic block needs its symbol be emitted regardless of
   /// whether the flow just falls-through to it.
@@ -216,12 +220,32 @@
   /// Return a formatted string to identify this block and its parent function.
   std::string getFullName() const;
 
-  /// Test whether this block is potentially the target of an indirect branch.
-  bool hasAddressTaken() const { return AddressTaken; }
+  /// Test whether this block is used as as something other than the target
+  /// of a terminator, exception-handling target, or jump table. This is
+  /// either the result of an IR-level "blockaddress", or some form
+  /// of target-specific branch lowering.
+  bool hasAddressTaken() const {
+    return MachineBlockAddressTaken || IRBlockAddressTaken;
+  }
+
+  /// Test whether this block is used as something other than the target of a
+  /// terminator, exception-handling target, jump table, or IR blockaddress.
+  /// For example, its address might be loaded into a register, or
+  /// stored in some branch table that isn't part of MachineJumpTableInfo.
+  bool isMachineBlockAddressTaken() const { return MachineBlockAddressTaken; }
+
+  /// Test whether this block is the target of an IR BlockAddress.  (There can
+  /// more than one MBB associated with an IR BB where the address is taken.)
+  bool isIRBlockAddressTaken() const { return IRBlockAddressTaken; }
+
+  /// Set this block to indicate that its address is used as something other
+  /// than the target of a terminator, exception-handling target, jump table,
+  /// or IR-level "blockaddress".
+  void setMachineBlockAddressTaken() { MachineBlockAddressTaken = true; }
 
-  /// Set this block to reflect that it potentially is the target of an indirect
-  /// branch.
-  void setHasAddressTaken() { AddressTaken = true; }
+  /// Set this block to reflect that it corresponds to an IR-level basic block
+  /// with a BlockAddress.
+  void setIsIRBlockAddressTaken() { IRBlockAddressTaken = true; }
 
   /// Test whether this block must have its label emitted.
   bool hasLabelMustBeEmitted() const { return LabelMustBeEmitted; }
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -3475,15 +3475,15 @@
   // here, because multiple LLVM BB's may have been RAUW'd to this block after
   // the references were generated.
   const BasicBlock *BB = MBB.getBasicBlock();
-  if (MBB.hasAddressTaken()) {
+  if (MBB.isIRBlockAddressTaken()) {
     if (isVerbose())
       OutStreamer->AddComment("Block address taken");
 
-    // MBBs can have their address taken as part of CodeGen without having
-    // their corresponding BB's address taken in IR
-    if (BB && BB->hasAddressTaken())
-      for (MCSymbol *Sym : getAddrLabelSymbolToEmit(BB))
-        OutStreamer->emitLabel(Sym);
+    assert(BB && BB->hasAddressTaken() && "Missing BB");
+    for (MCSymbol *Sym : getAddrLabelSymbolToEmit(BB))
+      OutStreamer->emitLabel(Sym);
+  } else if (isVerbose() && MBB.isMachineBlockAddressTaken()) {
+    OutStreamer->AddComment("Block address taken");
   }
 
   // Print some verbose block comments.
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3395,7 +3395,7 @@
     MF->push_back(MBB);
 
     if (BB.hasAddressTaken())
-      MBB->setHasAddressTaken();
+      MBB->setIsIRBlockAddressTaken();
 
     if (!HasMustTailInVarArgFn)
       HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -114,7 +114,6 @@
     kw_call_entry,
     kw_custom,
     kw_liveout,
-    kw_address_taken,
     kw_landing_pad,
     kw_inlineasm_br_indirect_target,
     kw_ehfunclet_entry,
@@ -129,6 +128,8 @@
     kw_bbsections,
     kw_unknown_size,
     kw_unknown_address,
+    kw_ir_block_address_taken,
+    kw_machine_block_address_taken,
 
     // Metadata types.
     kw_distinct,
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -258,7 +258,6 @@
       .Case("call-entry", MIToken::kw_call_entry)
       .Case("custom", MIToken::kw_custom)
       .Case("liveout", MIToken::kw_liveout)
-      .Case("address-taken", MIToken::kw_address_taken)
       .Case("landing-pad", MIToken::kw_landing_pad)
       .Case("inlineasm-br-indirect-target",
             MIToken::kw_inlineasm_br_indirect_target)
@@ -275,6 +274,8 @@
       .Case("unknown-size", MIToken::kw_unknown_size)
       .Case("unknown-address", MIToken::kw_unknown_address)
       .Case("distinct", MIToken::kw_distinct)
+      .Case("ir-block-address-taken", MIToken::kw_ir_block_address_taken)
+      .Case("machine-block-address-taken", MIToken::kw_machine_block_address_taken)
       .Default(MIToken::Identifier);
 }
 
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -669,7 +669,8 @@
   auto Loc = Token.location();
   auto Name = Token.stringValue();
   lex();
-  bool HasAddressTaken = false;
+  bool MachineBlockAddressTaken = false;
+  bool IsIRBlockAddressTaken = false;
   bool IsLandingPad = false;
   bool IsInlineAsmBrIndirectTarget = false;
   bool IsEHFuncletEntry = false;
@@ -680,8 +681,12 @@
     do {
       // TODO: Report an error when multiple same attributes are specified.
       switch (Token.kind()) {
-      case MIToken::kw_address_taken:
-        HasAddressTaken = true;
+      case MIToken::kw_machine_block_address_taken:
+        MachineBlockAddressTaken = true;
+        lex();
+        break;
+      case MIToken::kw_ir_block_address_taken:
+        IsIRBlockAddressTaken = true;
         lex();
         break;
       case MIToken::kw_landing_pad:
@@ -701,6 +706,7 @@
           return true;
         break;
       case MIToken::IRBlock:
+      case MIToken::NamedIRBlock:
         // TODO: Report an error when both name and ir block are specified.
         if (parseIRBlock(BB, MF.getFunction()))
           return true;
@@ -736,8 +742,10 @@
                           Twine(ID));
   if (Alignment)
     MBB->setAlignment(Align(Alignment));
-  if (HasAddressTaken)
-    MBB->setHasAddressTaken();
+  if (MachineBlockAddressTaken)
+    MBB->setMachineBlockAddressTaken();
+  if (IsIRBlockAddressTaken)
+    MBB->setIsIRBlockAddressTaken();
   MBB->setIsEHPad(IsLandingPad);
   MBB->setIsInlineAsmBrIndirectTarget(IsInlineAsmBrIndirectTarget);
   MBB->setIsEHFuncletEntry(IsEHFuncletEntry);
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -503,9 +503,14 @@
   }
 
   if (printNameFlags & PrintNameAttributes) {
-    if (hasAddressTaken()) {
+    if (isMachineBlockAddressTaken()) {
       os << (hasAttributes ? ", " : " (");
-      os << "address-taken";
+      os << "machine-block-address-taken";
+      hasAttributes = true;
+    }
+    if (isIRBlockAddressTaken()) {
+      os << (hasAttributes ? ", " : " (");
+      os << "ir-block-address-taken";
       hasAttributes = true;
     }
     if (isEHPad()) {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -629,6 +629,16 @@
     }
   }
 
+  if (MBB->isIRBlockAddressTaken()) {
+    if (!MBB->getBasicBlock())
+      report("ir-block-address-taken block is missing associated basic block.",
+             MBB);
+    else if (!MBB->getBasicBlock()->hasAddressTaken())
+      report("ir-block-address-taken is associated with basic block not used by "
+             "a blockaddress.",
+             MBB);
+  }
+
   // Count the number of landing pad successors.
   SmallPtrSet<const MachineBasicBlock*, 4> LandingPadSuccs;
   for (const auto *succ : MBB->successors()) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -270,7 +270,7 @@
     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
     // the first one should be marked.
     if (BB.hasAddressTaken())
-      MBB->setHasAddressTaken();
+      MBB->setIsIRBlockAddressTaken();
 
     // Mark landing pad blocks.
     if (BB.isEHPad())
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1263,13 +1263,8 @@
         .addMBB(LoopStart).addImm(CountImm);
   }
 
-  // Make sure the loop start always has a reference in the CFG.  We need
-  // to create a BlockAddress operand to get this mechanism to work both the
-  // MachineBasicBlock and BasicBlock objects need the flag set.
-  LoopStart->setHasAddressTaken();
-  // This line is needed to set the hasAddressTaken flag on the BasicBlock
-  // object.
-  BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
+  // Make sure the loop start always has a reference in the CFG.
+  LoopStart->setMachineBlockAddressTaken();
 
   // Replace the loop branch with an endloop instruction.
   DebugLoc LastIDL = LastI->getDebugLoc();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -2084,7 +2084,7 @@
   MF->insert(I, MainMBB);
   MF->insert(I, SinkMBB);
   MF->push_back(RestoreMBB);
-  RestoreMBB->setHasAddressTaken();
+  RestoreMBB->setMachineBlockAddressTaken();
 
   // Transfer the remainder of BB and its successor edges to SinkMBB.
   SinkMBB->splice(SinkMBB->begin(), MBB,
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -2777,7 +2777,7 @@
 
   // Record that we've taken the address of CatchRetTarget and no longer just
   // reference it in a terminator.
-  CatchRetTarget->setHasAddressTaken();
+  CatchRetTarget->setMachineBlockAddressTaken();
 }
 
 bool X86FrameLowering::restoreCalleeSavedRegisters(
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35124,7 +35124,7 @@
   MF->insert(I, mainMBB);
   MF->insert(I, sinkMBB);
   MF->push_back(restoreMBB);
-  restoreMBB->setHasAddressTaken();
+  restoreMBB->setMachineBlockAddressTaken();
 
   MachineInstrBuilder MIB;
 
diff --git a/llvm/lib/Target/X86/X86IndirectThunks.cpp b/llvm/lib/Target/X86/X86IndirectThunks.cpp
--- a/llvm/lib/Target/X86/X86IndirectThunks.cpp
+++ b/llvm/lib/Target/X86/X86IndirectThunks.cpp
@@ -234,11 +234,11 @@
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
   BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
-  CaptureSpec->setHasAddressTaken();
+  CaptureSpec->setMachineBlockAddressTaken();
   CaptureSpec->addSuccessor(CaptureSpec);
 
   CallTarget->addLiveIn(ThunkReg);
-  CallTarget->setHasAddressTaken();
+  CallTarget->setMachineBlockAddressTaken();
   CallTarget->setAlignment(Align(16));
 
   // Insert return address clobber
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1144,7 +1144,7 @@
     // Insert a comparison of the incoming target register with this block's
     // address. This also requires us to mark the block as having its address
     // taken explicitly.
-    MBB.setHasAddressTaken();
+    MBB.setMachineBlockAddressTaken();
     auto InsertPt = MBB.SkipPHIsLabelsAndDebug(MBB.begin());
     if (MF.getTarget().getCodeModel() == CodeModel::Small &&
         !Subtarget->isPositionIndependent()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -137,13 +137,13 @@
 ; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
 ;
 ; Check basic block L1 has 2 successors: BBL1 and BBL2
-; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):
+; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (ir-block-address-taken):
 ; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
 ; CHECK:                  %[[BB_L2:bb.[0-9]+]](0x40000000)
 ; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
 ;
 ; Check basic block L2 is the return basic block
-; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken):
+; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (ir-block-address-taken):
 ; CHECK-NEXT: RET_ReallyLR
 
 @indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
@@ -25,20 +25,21 @@
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
-  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @addr
-  ; CHECK:   [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @addr
-  ; CHECK:   G_STORE [[BLOCK_ADDR]](p0), [[ADD_LOW]](p0) :: (store (p0) into @addr)
-  ; CHECK:   G_BRINDIRECT [[BLOCK_ADDR]](p0)
-  ; CHECK: bb.1.block (address-taken):
-  ; CHECK:   RET_ReallyLR
+  ; CHECK-NEXT:   [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
+  ; CHECK-NEXT:   [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @addr
+  ; CHECK-NEXT:   [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @addr
+  ; CHECK-NEXT:   G_STORE [[BLOCK_ADDR]](p0), [[ADD_LOW]](p0) :: (store (p0) into @addr)
+  ; CHECK-NEXT:   G_BRINDIRECT [[BLOCK_ADDR]](p0)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.block (ir-block-address-taken):
+  ; CHECK-NEXT:   RET_ReallyLR
   bb.1 (%ir-block.0):
     %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
     %1:_(p0) = G_GLOBAL_VALUE @addr
     G_STORE %0(p0), %1(p0) :: (store (p0) into @addr)
     G_BRINDIRECT %0(p0)
 
-  bb.2.block (address-taken):
+  bb.2.block (ir-block-address-taken):
     RET_ReallyLR
 
 ...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
@@ -30,32 +30,34 @@
 body:             |
   ; CHECK-LABEL: name: test_blockaddress
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
-  ; CHECK:   [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
-  ; CHECK:   STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
-  ; CHECK:   BR [[MOVaddrBA]]
-  ; CHECK: bb.1.block (address-taken):
+  ; CHECK-NEXT:   [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
+  ; CHECK-NEXT:   [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
+  ; CHECK-NEXT:   STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
+  ; CHECK-NEXT:   BR [[MOVaddrBA]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.block (ir-block-address-taken):
   ; LARGE-LABEL: name: test_blockaddress
   ; LARGE: bb.0 (%ir-block.0):
-  ; LARGE:   [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
-  ; LARGE:   [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
-  ; LARGE:   [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
-  ; LARGE:   [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48
-  ; LARGE:   [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
-  ; LARGE:   [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16
-  ; LARGE:   [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32
-  ; LARGE:   [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48
-  ; LARGE:   STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store (p0) into @addr)
-  ; LARGE:   BR [[MOVKXi2]]
-  ; LARGE: bb.1.block (address-taken):
+  ; LARGE-NEXT:   [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0
+  ; LARGE-NEXT:   [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16
+  ; LARGE-NEXT:   [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32
+  ; LARGE-NEXT:   [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48
+  ; LARGE-NEXT:   [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
+  ; LARGE-NEXT:   [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16
+  ; LARGE-NEXT:   [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32
+  ; LARGE-NEXT:   [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48
+  ; LARGE-NEXT:   STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store (p0) into @addr)
+  ; LARGE-NEXT:   BR [[MOVKXi2]]
+  ; LARGE-NEXT: {{  $}}
+  ; LARGE-NEXT: bb.1.block (ir-block-address-taken):
   bb.1 (%ir-block.0):
     %0:gpr(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
     %1:gpr(p0) = G_GLOBAL_VALUE @addr
     G_STORE %0(p0), %1(p0) :: (store (p0) into @addr)
     G_BRINDIRECT %0(p0)
 
-  bb.2.block (address-taken):
+  bb.2.block (ir-block-address-taken):
     RET_ReallyLR
 
 ...
diff --git a/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
--- a/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
+++ b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
@@ -79,24 +79,6 @@
     ret i32 %merge2
   }
 
-  define hidden i32 @label_address_entry() "branch-target-enforcement"="true" {
-  entry:
-    %0 = load i8*, i8** @label_address.addr, align 8
-    indirectbr i8* %0, [label %return, label %lab2]
-
-  lab2:                                             ; preds = %entry
-    br label %.split
-
-  return:                                           ; preds = %entry
-    br label %.split
-
-  .split:                                           ; preds = %lab2, %return
-    %merge = phi i8* [ blockaddress(@label_address, %lab2), %return ], [ blockaddress(@label_address, %return), %lab2 ]
-    %merge2 = phi i32 [ 1, %return ], [ 2, %lab2 ]
-    store i8* %merge, i8** @label_address.addr, align 8
-    ret i32 %merge2
-  }
-
   define hidden i32 @debug_ptr_auth() "branch-target-enforcement"="true" {
   entry:
     tail call void asm sideeffect "", "~{lr}"()
@@ -116,7 +98,7 @@
     RET undef $lr, implicit killed $w0
 
 ---
-# Internal function, not address-taken in this module, however the compiler
+# Internal function, not ir-block-address-taken in this module, however the compiler
 # cannot 100% ensure that later parts of the toolchain won't add indirect
 # jumps. E.g. a linker adding a thunk to extend the range of a direct jump.
 # Therefore, even this case needs a BTI.
@@ -270,8 +252,8 @@
     renamable $x9 = LDRXui renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (dereferenceable load (s64) from @label_address.addr)
     BR killed renamable $x9
 
-  bb.1.return (address-taken):
-    ; CHECK: bb.1.return (address-taken):
+  bb.1.return (ir-block-address-taken):
+    ; CHECK: bb.1.return (ir-block-address-taken):
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
@@ -281,8 +263,8 @@
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store (s64) into @label_address.addr)
     RET undef $lr, implicit killed $w0
 
-  bb.2.lab2 (address-taken):
-    ; CHECK: bb.2.lab2 (address-taken):
+  bb.2.lab2 (ir-block-address-taken):
+    ; CHECK: bb.2.lab2 (ir-block-address-taken):
     ; CHECK-NEXT: HINT 36
     liveins: $x8
 
@@ -293,52 +275,6 @@
     RET undef $lr, implicit killed $w0
 
 ---
-# Function takes address of the entry block, so the entry block needs a BTI JC.
-name:            label_address_entry
-stack:
-  - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
-      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-body:             |
-  bb.0.entry (address-taken):
-    ; CHECK-LABEL: label_address_entry
-    ; CHECK: bb.0.entry (address-taken):
-    ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
-    ; CHECK-NEXT: {{  }}
-    ; CHECK-NEXT: HINT 38
-    ; CHECK: BR killed renamable $x9
-    successors: %bb.1(0x40000000), %bb.2(0x40000000)
-
-    renamable $x8 = ADRP target-flags(aarch64-page) @label_address.addr
-    renamable $x9 = LDRXui renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (dereferenceable load (s64) from @label_address.addr)
-    BR killed renamable $x9
-
-  bb.1.return (address-taken):
-    ; CHECK: bb.1.return (address-taken):
-    ; CHECK-NEXT: HINT 36
-    liveins: $x8
-    frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
-    frame-setup CFI_INSTRUCTION negate_ra_sign_state
-    early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store (s64) into %stack.0)
-    INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
-    $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.entry)
-    renamable $w0 = ORRWri $wzr, 0
-    renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.entry), 0
-    STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store (s64) into @label_address.addr)
-    early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.0)
-    RETAA implicit $sp, implicit $lr, implicit killed $w0
-
-  bb.2.lab2:
-    ; CHECK: bb.2.lab2:
-    ; CHECK-NOT: HINT
-    liveins: $x8
-
-    $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.return)
-    renamable $w0 = ORRWri $wzr, 1984
-    renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.return), 0
-    STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store (s64) into @label_address.addr)
-    RET undef $lr, implicit killed $w0
----
 # When PACIASP is the first real instruction in the functions then BTI should not be inserted.
 name:            debug_ptr_auth
 stack:
diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
--- a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
+++ b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
@@ -65,11 +65,11 @@
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (ir-block-address-taken):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (ir-block-address-taken):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
@@ -90,11 +90,11 @@
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (ir-block-address-taken):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (ir-block-address-taken):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
@@ -115,11 +115,11 @@
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (ir-block-address-taken):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (ir-block-address-taken):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
@@ -140,11 +140,11 @@
   ; ISBDSB-NEXT: isb
   ; SB-NEXT:     {{ sb$}}
 
-  bb.1.l2 (address-taken):
+  bb.1.l2 (ir-block-address-taken):
     renamable $w0 = MOVZWi 1, 0
     RET undef $lr, implicit $w0
 
-  bb.2.return (address-taken):
+  bb.2.return (ir-block-address-taken):
     $w0 = ORRWrs $wzr, $wzr, 0
     RET undef $lr, implicit $w0
 ...
diff --git a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
--- a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
@@ -6,9 +6,11 @@
 --- |
   target triple = "thumbv7-unknown-linux-gnueabi"
 
-  define dso_local void @fn1() {
+  define dso_local i8* @fn1() {
+  entry:
+    br label %l_yes
   l_yes:
-    ret void
+    ret i8* blockaddress(@fn1, %l_yes)
   }
 
   declare dso_local i32 @fn2(...)
@@ -20,22 +22,25 @@
 body:             |
   ; CHECK-LABEL: name: fn1
   ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r4, $lr
-  ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
-  ; CHECK:   t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
-  ; CHECK:   $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
-  ; CHECK:   $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
-  ; CHECK:   tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
-  ; CHECK:   t2CMPri $sp, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
-  ; CHECK:   t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
-  ; CHECK:   t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
-  ; CHECK:   t2B %bb.1, 14 /* CC::al */, $noreg
-  ; CHECK: bb.1:
-  ; CHECK:   INLINEASM &"", 1
-  ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
-  ; CHECK: bb.2.l_yes (address-taken):
-  ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $r0, $r1, $r2, $r4, $lr
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
+  ; CHECK-NEXT:   t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT:   $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
+  ; CHECK-NEXT:   $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
+  ; CHECK-NEXT:   tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
+  ; CHECK-NEXT:   t2CMPri $sp, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT:   t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
+  ; CHECK-NEXT:   t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
+  ; CHECK-NEXT:   t2B %bb.1, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */
+  ; CHECK-NEXT:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.l_yes (ir-block-address-taken):
+  ; CHECK-NEXT:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $r0, $r1, $r2, $r4, $lr
@@ -70,7 +75,7 @@
     INLINEASM &"", 1
     $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
 
-  bb.4.l_yes (address-taken):
+  bb.4.l_yes (ir-block-address-taken):
     $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
 
 ...
diff --git a/llvm/test/CodeGen/ARM/ifcvt-size.mir b/llvm/test/CodeGen/ARM/ifcvt-size.mir
--- a/llvm/test/CodeGen/ARM/ifcvt-size.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt-size.mir
@@ -553,7 +553,7 @@
     INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
     tBX_RET 14, $noreg, implicit $r2
     
-  bb.5.lab1 (address-taken):
+  bb.5.lab1 (ir-block-address-taken):
     liveins: $r0
 
     renamable $r0, dead $cpsr = nsw tADDi8 killed renamable $r0, 5, 14, $noreg
diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir
--- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir
+++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir
@@ -107,7 +107,7 @@
     $r4 = A2_tfrsi 10
     J2_loop0r %bb.1, killed $r0, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.1 (address-taken):
+  bb.1 (machine-block-address-taken):
     successors: %bb.2(0x80000000)
     liveins: $lc0:0x00000004, $r2:0x00000001, $r3:0x00000001, $r4:0x00000001, $sa0:0x00000004
 
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir b/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
--- a/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
+++ b/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
@@ -10,7 +10,7 @@
 # CHECK:  [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920
 # CHECK:  J2_loop0r %bb.1, [[R0]]
 #
-# CHECK: bb.1.b1 (address-taken):
+# CHECK: bb.1.b1 (machine-block-address-taken):
 # CHECK:   ENDLOOP0 %bb.1
 
 
diff --git a/llvm/test/CodeGen/Hexagon/loop_correctness.ll b/llvm/test/CodeGen/Hexagon/loop_correctness.ll
--- a/llvm/test/CodeGen/Hexagon/loop_correctness.ll
+++ b/llvm/test/CodeGen/Hexagon/loop_correctness.ll
@@ -8,8 +8,8 @@
 ; CHECK-NEXT:     loop0(.LBB0_1,#3)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp0: // Block address taken
-; CHECK-NEXT:  .LBB0_1: // %b2
+; CHECK-NEXT:  .LBB0_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
@@ -42,8 +42,8 @@
 ; CHECK-NEXT:     loop0(.LBB1_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp1: // Block address taken
-; CHECK-NEXT:  .LBB1_1: // %b2
+; CHECK-NEXT:  .LBB1_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
@@ -76,8 +76,8 @@
 ; CHECK-NEXT:     loop0(.LBB2_1,#1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp2: // Block address taken
-; CHECK-NEXT:  .LBB2_1: // %b2
+; CHECK-NEXT:  .LBB2_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
@@ -110,8 +110,8 @@
 ; CHECK-NEXT:     loop0(.LBB3_1,#4)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp3: // Block address taken
-; CHECK-NEXT:  .LBB3_1: // %b2
+; CHECK-NEXT:  .LBB3_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
@@ -144,8 +144,8 @@
 ; CHECK-NEXT:     loop0(.LBB4_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp4: // Block address taken
-; CHECK-NEXT:  .LBB4_1: // %b2
+; CHECK-NEXT:  .LBB4_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
@@ -178,8 +178,8 @@
 ; CHECK-NEXT:     loop0(.LBB5_1,#2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .Ltmp5: // Block address taken
-; CHECK-NEXT:  .LBB5_1: // %b2
+; CHECK-NEXT:  .LBB5_1: // Block address taken
+; CHECK-NEXT:    // %b2
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     nop
diff --git a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
--- a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
+++ b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
@@ -132,7 +132,7 @@
     %14:intregs = COPY %10
     J2_loop0r %bb.3, %14, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.3.b2 (address-taken):
+  bb.3.b2 (machine-block-address-taken):
     successors: %bb.3(0x7c000000), %bb.4(0x04000000)
 
     %1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>
diff --git a/llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir b/llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
--- a/llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
@@ -80,7 +80,7 @@
     %23:intregs = COPY %0
     J2_loop0r %bb.2, %23, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.2 (address-taken):
+  bb.2 (machine-block-address-taken):
     successors: %bb.3, %bb.2
 
     %3:intregs = PHI %2, %bb.1, %10, %bb.2
diff --git a/llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir b/llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
--- a/llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
@@ -52,7 +52,7 @@
     %11:intregs = IMPLICIT_DEF
     J2_loop0i %bb.1, 6, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
 
-  bb.1 (address-taken):
+  bb.1 (machine-block-address-taken):
     successors: %bb.1, %bb.2
 
     %0:intregs = PHI %11, %bb.0, %6, %bb.1
diff --git a/llvm/test/CodeGen/MIR/Generic/basic-blocks.mir b/llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
--- a/llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
+++ b/llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
@@ -31,19 +31,19 @@
 # CHECK-LABEL: name: bar
 # CHECK: body:
 # CHECK-NEXT: bb.0.start (align 4):
-# CHECK:      bb.1 (address-taken):
+# CHECK:      bb.1 (machine-block-address-taken):
 name:            bar
 body: |
   bb.0.start (align 4):
-  bb.1 (address-taken):
+  bb.1 (machine-block-address-taken):
 ...
 ---
 # CHECK-LABEL: name: test
 # CHECK: body:
-# CHECK-NEXT: bb.0.start (address-taken, align 4):
-# CHECK:      bb.1 (address-taken, align 4):
+# CHECK-NEXT: bb.0.start (machine-block-address-taken, align 4):
+# CHECK:      bb.1 (machine-block-address-taken, align 4):
 name:            test
 body: |
-  bb.0.start (align 4, address-taken):
-  bb.1 (address-taken, align 4):
+  bb.0.start (align 4, machine-block-address-taken):
+  bb.1 (machine-block-address-taken, align 4):
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
--- a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
@@ -62,7 +62,7 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
 ---
@@ -76,7 +76,7 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (%ir-block."quoted block", ir-block-address-taken):
     RET64
 ...
 ---
@@ -103,7 +103,7 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (%ir-block.0, ir-block-address-taken):
     RET64
 ...
 ---
@@ -116,6 +116,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
--- a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
@@ -1,4 +1,5 @@
 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+#
 
 --- |
 
@@ -25,6 +26,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
--- a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
@@ -25,6 +25,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
--- a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
@@ -25,6 +25,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
--- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
@@ -25,6 +25,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1.block (address-taken):
+  bb.1.block (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
--- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
@@ -24,6 +24,6 @@
     MOV64mr $rip, 1, _, @addr, _, killed $rax
     JMP64m $rip, 1, _, @addr, _
 
-  bb.1 (address-taken):
+  bb.1 (ir-block-address-taken):
     RET64
 ...
diff --git a/llvm/test/CodeGen/X86/callbr-asm-kill.mir b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
--- a/llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -57,7 +57,7 @@
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY killed $rdi
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr64 = COPY killed [[COPY1]]
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT: bb.1.loop (address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT: bb.1.loop (ir-block-address-taken, inlineasm-br-indirect-target):
   ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr64 = COPY killed [[COPY2]]
@@ -78,7 +78,7 @@
     %3:gr64 = COPY killed $rsi
     %2:gr64 = COPY killed $rdi
 
-  bb.1.loop (address-taken, inlineasm-br-indirect-target):
+  bb.1.loop (ir-block-address-taken, inlineasm-br-indirect-target):
     successors: %bb.2(0x80000000), %bb.1(0x00000000)
 
     %0:gr64 = PHI %2, %bb.0, %1, %bb.1
diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
--- a/llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
@@ -17,12 +17,12 @@
 
 ; Check the second INLINEASM_BR target block is preceded by the block with the
 ; second INLINEASM_BR.
-; CHECK: bb.2 (%ir-block.7, address-taken, inlineasm-br-indirect-target):
+; CHECK: bb.2 (%ir-block.7, ir-block-address-taken, inlineasm-br-indirect-target):
 ; CHECK-NEXT: predecessors: %bb.1
 
 ; Check the first INLINEASM_BR target block is predecessed by the block with
 ; the first INLINEASM_BR.
-; CHECK: bb.4 (%ir-block.11, address-taken, inlineasm-br-indirect-target):
+; CHECK: bb.4 (%ir-block.11, ir-block-address-taken, inlineasm-br-indirect-target):
 ; CHECK-NEXT: predecessors: %bb.0
 
 @.str = private unnamed_addr constant [26 x i8] c"inline asm#1 returned %d\0A\00", align 1
diff --git a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
--- a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
+++ b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
@@ -8,33 +8,43 @@
 define i8* @test1(i8** %arg1, i8* %arg2) {
   ; CHECK-LABEL: name: test1
   ; CHECK: bb.0.bb:
-  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
-  ; CHECK:   liveins: $rdi, $rsi
-  ; CHECK:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
-  ; CHECK:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
-  ; CHECK:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1)
-  ; CHECK:   [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags
-  ; CHECK:   JCC_1 %bb.2, 4, implicit $eflags
-  ; CHECK:   JMP_1 %bb.1
-  ; CHECK: bb.1.bb100:
-  ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1)
-  ; CHECK:   JMP_1 %bb.3
-  ; CHECK: bb.2.bb106:
-  ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-  ; CHECK:   CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
-  ; CHECK:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-  ; CHECK: bb.3.bb110:
-  ; CHECK:   successors: %bb.5(0x80000000), %bb.4(0x00000000)
-  ; CHECK:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.2, [[MOV64rm]], %bb.1
-  ; CHECK:   INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, blockaddress(@test1, %ir-block.bb17.i.i.i), 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
-  ; CHECK:   JMP_1 %bb.5
-  ; CHECK: bb.4.bb17.i.i.i (address-taken, inlineasm-br-indirect-target):
-  ; CHECK:   successors: %bb.5(0x80000000)
-  ; CHECK: bb.5.kmem_cache_has_cpu_partial.exit:
-  ; CHECK:   $rax = COPY [[PHI]]
-  ; CHECK:   RET 0, $rax
+  ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK-NEXT:   liveins: $rdi, $rsi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+  ; CHECK-NEXT:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.arg1)
+  ; CHECK-NEXT:   [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[MOV64rm]], [[COPY]], implicit-def $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.bb100:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg1)
+  ; CHECK-NEXT:   JMP_1 %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.bb106:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT:   CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
+  ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.bb110:
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000), %bb.4(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.2, [[MOV64rm]], %bb.1
+  ; CHECK-NEXT:   INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, blockaddress(@test1, %ir-block.bb17.i.i.i), 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.bb17.i.i.i (ir-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.kmem_cache_has_cpu_partial.exit:
+  ; CHECK-NEXT:   $rax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $rax
 bb:
   %i28.i = load i8*, i8** %arg1, align 8
   %if = icmp ne i8* %i28.i, %arg2
diff --git a/llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir b/llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
--- a/llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
+++ b/llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
@@ -168,7 +168,7 @@
     TEST8rr killed renamable $r8b, renamable $r8b, implicit-def $eflags
     JCC_1 %bb.6, 5, implicit $eflags
 
-  bb.8.return (address-taken):
+  bb.8.return (machine-block-address-taken):
     $eax = MOV32rm $rbp, 1, $noreg, -12, $noreg :: (load (s32) from %stack.0)
     SEH_Epilogue
     $rsp = frame-destroy ADD64ri8 $rsp, 48, implicit-def dead $eflags
diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir b/llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
--- a/llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
+++ b/llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
@@ -8,7 +8,7 @@
 # RESULT: bb.0.entry:
 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-# RESULT: bb.1 (address-taken, align 8):
+# RESULT: bb.1 (ir-block-address-taken, align 8):
 # RESULT: bb.2 (landing-pad, align 16):
 # RESULT: bb.3 (inlineasm-br-indirect-target):
 # RESULT: bb.4 (ehfunclet-entry):
@@ -19,6 +19,7 @@
 # RESULT-NEXT: successors: %bb.9(0x66666666), %bb.10(0x1999999a)
 # RESULT: bb.9:
 # RESULT: bb.10.exitblock:
+# RESULT: bb.11 (machine-block-address-taken):
 
 --- |
   define void @func(i32 %size)  {
@@ -48,7 +49,7 @@
     S_NOP 0
     %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-  bb.1 (address-taken, align 8):
+  bb.1 (ir-block-address-taken, align 8):
 
   bb.2 (landing-pad, align 16):
 
@@ -69,4 +70,6 @@
 
   bb.10.exitblock:
     S_ENDPGM 0, implicit %0
+
+  bb.11 (machine-block-address-taken):
 ...
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -199,8 +199,10 @@
         DstMF->CreateMachineBasicBlock(SrcMBB.getBasicBlock());
     Src2DstMBB[&SrcMBB] = DstMBB;
 
-    if (SrcMBB.hasAddressTaken())
-      DstMBB->setHasAddressTaken();
+    if (SrcMBB.isIRBlockAddressTaken())
+      DstMBB->setIsIRBlockAddressTaken();
+    if (SrcMBB.isMachineBlockAddressTaken())
+      DstMBB->setMachineBlockAddressTaken();
 
     // FIXME: This is not serialized
     if (SrcMBB.hasLabelMustBeEmitted())