diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -6224,9 +6224,9 @@ std::swap(N1, N2); } else { switch (Opcode) { - case ISD::SIGN_EXTEND_INREG: case ISD::SUB: return getUNDEF(VT); // fold op(undef, arg2) -> undef + case ISD::SIGN_EXTEND_INREG: case ISD::UDIV: case ISD::SDIV: case ISD::UREM: diff --git a/llvm/test/CodeGen/AArch64/pr55178.ll b/llvm/test/CodeGen/AArch64/pr55178.ll --- a/llvm/test/CodeGen/AArch64/pr55178.ll +++ b/llvm/test/CodeGen/AArch64/pr55178.ll @@ -10,8 +10,9 @@ ; CHECK-NEXT: mov w8, #-113 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: lsl w8, w8, w0 -; CHECK-NEXT: cmp w8, w8, sxtb -; CHECK-NEXT: cset w0, lt +; CHECK-NEXT: sxtb w8, w8 +; CHECK-NEXT: cmp w8, #0 +; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret %1 = shl i8 -113, %X %cmp = icmp slt i8 undef, %1 diff --git a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll --- a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll +++ b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll @@ -11,18 +11,19 @@ @g_151 = external dso_local global i32, align 4 @g_222 = external dso_local unnamed_addr global [7 x [10 x i8]], align 2 -define void @main() { +define void @main(i16 %in) { ; CHECK-LABEL: main: ; CHECK: # %bb.0: -; CHECK-NEXT: lhi %r0, 1 +; CHECK-NEXT: lhr %r2, %r2 ; CHECK-NEXT: larl %r1, g_151 ; CHECK-NEXT: lghi %r3, 0 -; CHECK-NEXT: chi %r0, 0 +; CHECK-NEXT: chi %r2, 0 +; CHECK-NEXT: lhi %r0, 1 ; CHECK-NEXT: locghile %r3, 1 ; CHECK-NEXT: o %r0, 0(%r1) -; CHECK-NEXT: dsgfr %r2, %r0 ; CHECK-NEXT: larl %r1, g_222 ; CHECK-NEXT: lghi %r5, 0 +; CHECK-NEXT: dsgfr %r2, %r0 ; CHECK-NEXT: stgrl %r2, g_39 ; CHECK-NEXT: stc %r5, 19(%r1) ; CHECK-NEXT: br %r14 @@ -32,7 +33,7 @@ %tmp5 = srem i64 0, %tmp4 %tmp6 = trunc i64 %tmp5 to i8 store i8 %tmp6, i8* getelementptr inbounds ([7 x [10 x i8]], [7 x [10 x i8]]* @g_222, i64 0, i64 1, i64 9), align 1 - %tmp7 = icmp slt i16 undef, 1 + %tmp7 = icmp slt i16 %in, 1 %tmp8 = zext i1 %tmp7 to i64 %tmp9 = srem i64 %tmp8, %tmp4 store i64 %tmp9, i64* @g_39, align 8