diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7416,21 +7416,6 @@
     OptionalIdx[Op.getImmTy()] = i;
   }
 
-  // This is a workaround for an llvm quirk which may result in an
-  // incorrect instruction selection. Lds and non-lds versions of
-  // MUBUF instructions are identical except that lds versions
-  // have mandatory 'lds' modifier. However this modifier follows
-  // optional modifiers and llvm asm matcher regards this 'lds'
-  // modifier as an optional one. As a result, an lds version
-  // of opcode may be selected even if it has no 'lds' modifier.
-  if (IsLdsOpcode && !HasLdsModifier) {
-    int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode());
-    if (NoLdsOpcode != -1) { // Got lds version - correct it.
-      Inst.setOpcode(NoLdsOpcode);
-      IsLdsOpcode = false;
-    }
-  }
-
   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
 
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -320,7 +320,7 @@
   bits<1> idxen       = 0;
   bits<1> addr64      = 0;
   bits<1> lds         = 0;
-  bits<1> has_vdata   = 1;
+  bits<1> has_vdata   = !not(lds);
   bits<1> has_vaddr   = 1;
   bits<1> has_glc     = 1;
   bits<1> has_dlc     = 1;
@@ -373,7 +373,7 @@
 
   // GFX90A+ only: instruction uses AccVGPR for data
   // Bit supersedes tfe.
-  bits<1> acc = !if(ps.has_vdata, vdata{9}, 0);
+  bits<1> acc = !if(ps.has_vdata, vdata{9}, !if(ps.lds, ?, 0));
 }
 
 
@@ -494,10 +494,10 @@
                          RegisterClass vdata_rc = getVregSrcForVT<vdata_vt>.ret,
                          RegisterOperand vdata_op = getLdStRegisterOperand<vdata_rc>.ret>
   : MUBUF_Pseudo<opName,
-                 (outs vdata_op:$vdata),
+                 !if(isLds, (outs), (outs vdata_op:$vdata)),
                  !con(getMUBUFIns<addrKindCopy, [], isLds>.ret,
                       !if(HasTiedDest, (ins vdata_op:$vdata_in), (ins))),
-                 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol" #
+                 !if(isLds, " ", " $vdata, ") # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol" #
                    !if(isLds, " lds", "$tfe") # "$swz",
                  pattern>,
     MUBUF_SetupAddr<addrKindCopy> {
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
@@ -99,9 +99,6 @@
 buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
 
@@ -894,9 +891,6 @@
 buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x21,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
 
@@ -996,9 +990,6 @@
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x25,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
 
@@ -1098,9 +1089,6 @@
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x29,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
 
@@ -1200,9 +1188,6 @@
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x2d,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_dword v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x03]
 
@@ -1302,9 +1287,6 @@
 buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x42,0x03]
 
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x31,0xe0,0x00,0x05,0x02,0x03]
-
 buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x03]
 
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
@@ -96,8 +96,8 @@
 buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_format_x off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
@@ -1635,8 +1635,8 @@
 buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ubyte off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
@@ -1734,8 +1734,8 @@
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
@@ -1833,8 +1833,8 @@
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ushort off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
@@ -1932,8 +1932,8 @@
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sshort off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_dword v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
@@ -2031,8 +2031,8 @@
 buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_dword off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
--- a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
@@ -2685,10 +2685,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_format_x a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_format_x a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095
@@ -3777,10 +3773,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_sbyte a5, off, s[8:11], s3 offset:4095
@@ -3849,10 +3841,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_ushort a5, off, s[8:11], s3 offset:4095
@@ -3921,10 +3909,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_ushort a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_ushort a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_sshort a5, off, s[8:11], s3 offset:4095
@@ -3993,10 +3977,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_sshort a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_sshort a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_dword a5, off, s[8:11], s3 offset:4095
@@ -4065,10 +4045,6 @@
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_dword a5, off, s[8:11], s3 offset:4095 slc
 
-// GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x82,0x03]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-buffer_load_dword a5, off, s[8:11], s3 offset:4095 lds
-
 // GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x03]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
--- a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
@@ -84,8 +84,8 @@
 buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_format_x off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
@@ -1431,8 +1431,8 @@
 buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ubyte off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
@@ -1518,8 +1518,8 @@
 buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
@@ -1605,8 +1605,8 @@
 buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ushort off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
@@ -1692,8 +1692,8 @@
 buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sshort off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_dword v5, off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
@@ -1779,8 +1779,8 @@
 buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
 // CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
 
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_dword off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
 // CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/mubuf-gfx10.s b/llvm/test/MC/AMDGPU/mubuf-gfx10.s
--- a/llvm/test/MC/AMDGPU/mubuf-gfx10.s
+++ b/llvm/test/MC/AMDGPU/mubuf-gfx10.s
@@ -1,10 +1,10 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
 
-buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
-// GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x05,0x42,0x03]
+buffer_load_sbyte off, s[8:11], s3 glc slc lds
+// GFX10: buffer_load_sbyte off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x00,0x42,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc
-// GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc lds ; encoding: [0x00,0xc0,0x25,0xe0,0x00,0x05,0x42,0x03]
+buffer_load_sbyte off, s[8:11], s3 glc slc lds dlc
+// GFX10: buffer_load_sbyte off, s[8:11], s3 glc slc dlc lds ; encoding: [0x00,0xc0,0x25,0xe0,0x00,0x00,0x42,0x03]
 
 buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc
 // GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc ; encoding: [0x00,0xc0,0x24,0xe0,0x00,0x05,0x42,0x03]
diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s
--- a/llvm/test/MC/AMDGPU/mubuf.s
+++ b/llvm/test/MC/AMDGPU/mubuf.s
@@ -779,57 +779,57 @@
 // Lds support
 //===----------------------------------------------------------------------===//
 
-buffer_load_sbyte v5, off, s[8:11], s3 lds
-// SICI: buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x25,0xe0,0x00,0x05,0x02,0x03]
-// VI:   buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte off, s[8:11], s3 lds
+// SICI: buffer_load_sbyte off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x25,0xe0,0x00,0x00,0x02,0x03]
+// VI:   buffer_load_sbyte off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
-// SICI: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte off, s[8:11], s3 glc slc lds
+// SICI: buffer_load_sbyte off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sbyte off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds
-// SICI: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x25,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte off, s[8:11], s3 offset:4095 glc slc lds
+// SICI: buffer_load_sbyte off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x25,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sbyte off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds
-// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x25,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte v0, s[8:11], s3 offen offset:4095 slc lds
+// SICI: buffer_load_sbyte v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x25,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sbyte v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, v0, s[8:11], s3 offen lds
-// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x25,0xe0,0x00,0x05,0x02,0x03]
-// VI:   buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte v0, s[8:11], s3 offen lds
+// SICI: buffer_load_sbyte v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x25,0xe0,0x00,0x00,0x02,0x03]
+// VI:   buffer_load_sbyte v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds
-// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x25,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte v0, s[8:11], s3 idxen glc slc lds
+// SICI: buffer_load_sbyte v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x25,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sbyte v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds
-// SICI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x25,0xe0,0x00,0x05,0x02,0x03]
-// VI:   buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 lds
+// SICI: buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x25,0xe0,0x00,0x00,0x02,0x03]
+// VI:   buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
-// SICI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x25,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
+// SICI: buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x25,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// SICI: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x21,0xe0,0x00,0x05,0x02,0x03]
-// VI:   buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ubyte off, s[8:11], s3 offset:4095 lds
+// SICI: buffer_load_ubyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x21,0xe0,0x00,0x00,0x02,0x03]
+// VI:   buffer_load_ubyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds
-// SICI: buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x2d,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_sshort v0, s[8:11], s3 offen offset:4095 glc slc lds
+// SICI: buffer_load_sshort v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x2d,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_sshort v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds
-// SICI: buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x29,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_ushort v0, s[8:11], s3 idxen offset:4095 glc slc lds
+// SICI: buffer_load_ushort v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x29,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_ushort v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x00,0x02,0x03]
 
-buffer_load_dword v5, v0, s[8:11], s101 offen lds
-// SICI: buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x31,0xe0,0x00,0x05,0x02,0x65]
-// VI:   buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65]
+buffer_load_dword v0, s[8:11], s101 offen lds
+// SICI: buffer_load_dword v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x31,0xe0,0x00,0x00,0x02,0x65]
+// VI:   buffer_load_dword v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x00,0x02,0x65]
 
-buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
-// SICI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x01,0xe0,0x00,0x05,0x42,0x03]
-// VI:   buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_format_x v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
+// SICI: buffer_load_format_x v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x01,0xe0,0x00,0x00,0x42,0x03]
+// VI:   buffer_load_format_x v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x00,0x02,0x03]
 
 buffer_store_lds_dword s[4:7], s0 lds
 // NOSICI: error: instruction not supported on this GPU
@@ -843,26 +843,26 @@
 // NOSICI: error: instruction not supported on this GPU
 // VI: buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc ; encoding: [0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08]
 
-buffer_load_dwordx2 v[1:2], off, s[4:7], s1 lds
+buffer_load_dwordx2 off, s[4:7], s1 lds
 // NOSICI: error: operands are not valid for this GPU or mode
-// VI:   buffer_load_dwordx2 v[1:2], off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x55,0xe0,0x00,0x01,0x01,0x01]
+// VI:   buffer_load_dwordx2 off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x55,0xe0,0x00,0x00,0x01,0x01]
 
-buffer_load_dwordx3 v[0:2], off, s[4:7], s0 offset:4095 lds
-// NOSICI: error: operands are not valid for this GPU or mode
-// VI:   buffer_load_dwordx3 v[0:2], off, s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0x59,0xe0,0x00,0x00,0x01,0x00]
+buffer_load_dwordx3 off, s[4:7], s0 offset:4095 lds
+// NOSICI: error: not a valid operand
+// VI:   buffer_load_dwordx3 off, s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0x59,0xe0,0x00,0x00,0x01,0x00]
 
-buffer_load_dwordx4 v[1:4], off, s[4:7], s1 lds
+buffer_load_dwordx4 off, s[4:7], s1 lds
 // NOSICI: error: operands are not valid for this GPU or mode
-// VI:   buffer_load_dwordx4 v[1:4], off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x5d,0xe0,0x00,0x01,0x01,0x01]
+// VI:   buffer_load_dwordx4 off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x5d,0xe0,0x00,0x00,0x01,0x01]
 
 //===----------------------------------------------------------------------===//
 // Errors handling
 //===----------------------------------------------------------------------===//
 
-buffer_load_sbyte v5, off, s[8:11], s3 lds tfe
+buffer_load_sbyte off, s[8:11], s3 lds tfe
 // NOSICIVI: error: invalid operand for instruction
 
-buffer_load_dword v5, off, s[8:11], s3 tfe lds
+buffer_load_dword off, s[8:11], s3 tfe lds
 // NOSICIVI: error: invalid operand for instruction
 
 buffer_store_lds_dword s[4:7], s8 offset:4 lds tfe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -6702,8 +6702,8 @@
 # CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_format_x off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03
@@ -7521,8 +7521,8 @@
 # CHECK: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_ubyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03
@@ -7575,8 +7575,8 @@
 # CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_sbyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03
@@ -7629,8 +7629,8 @@
 # CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_ushort off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03
@@ -7683,8 +7683,8 @@
 # CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_sshort off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03
@@ -7737,8 +7737,8 @@
 # CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_dword off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
@@ -2013,9 +2013,6 @@
 # GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x02,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_format_x a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x01,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_format_xy a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x03]
 0xff,0x0f,0x04,0xe0,0x00,0x06,0x82,0x03
 
@@ -2832,9 +2829,6 @@
 # GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x42,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_ubyte a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x41,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x44,0xe0,0x00,0x05,0x82,0x03
 
@@ -2886,9 +2880,6 @@
 # GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x46,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_sbyte a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x45,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x48,0xe0,0x00,0x05,0x82,0x03
 
@@ -2940,9 +2931,6 @@
 # GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x4a,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_ushort a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x49,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x4c,0xe0,0x00,0x05,0x82,0x03
 
@@ -2994,9 +2982,6 @@
 # GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x4e,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_sshort a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x4d,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03
 
@@ -3048,9 +3033,6 @@
 # GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x82,0x03]
 0xff,0x0f,0x52,0xe0,0x00,0x05,0x82,0x03
 
-# GFX90A: buffer_load_dword a5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x82,0x03]
-0xff,0x0f,0x51,0xe0,0x00,0x05,0x82,0x03
-
 # GFX90A: buffer_load_dwordx2 a[6:7], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x03]
 0xff,0x0f,0x54,0xe0,0x00,0x06,0x82,0x03
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -6975,8 +6975,8 @@
 # CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_format_x off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x01,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03
@@ -7746,8 +7746,8 @@
 # CHECK: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_ubyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03
@@ -7797,8 +7797,8 @@
 # CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_sbyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x45,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03
@@ -7848,8 +7848,8 @@
 # CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_ushort off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x49,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03
@@ -7899,8 +7899,8 @@
 # CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_sshort off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x4d,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03
@@ -7950,8 +7950,8 @@
 # CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03
 
-# CHECK: buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03
+# CHECK: buffer_load_dword off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x51,0xe0,0x00,0x00,0x02,0x03
 
 # CHECK: buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
 0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/mubuf_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/mubuf_vi.txt
--- a/llvm/test/MC/Disassembler/AMDGPU/mubuf_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/mubuf_vi.txt
@@ -364,44 +364,47 @@
 # Lds support
 #===------------------------------------------------------------------------===#
 
-# VI:   buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03]
+# VI:   buffer_load_sbyte off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x00,0x02,0x03]
+0x00,0x00,0x45,0xe0,0x00,0x00,0x02,0x03
+
+# VI:   buffer_load_sbyte off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x00,0x02,0x03]
 0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03]
-0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x00,0x02,0x03]
+0x00,0x40,0x47,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x4f,0x47,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x1f,0x47,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03]
-0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x00,0x02,0x03]
+0x00,0x10,0x45,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03]
-0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x00,0x02,0x03]
+0x00,0x60,0x47,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x3f,0x45,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sbyte v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x7f,0x47,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_ubyte off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x0f,0x41,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_sshort v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x5f,0x4f,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_ushort v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x6f,0x4b,0xe0,0x00,0x00,0x02,0x03
 
-# VI:   buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65]
-0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65
+# VI:   buffer_load_dword v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x00,0x02,0x65]
+0x00,0x10,0x51,0xe0,0x00,0x00,0x02,0x65
 
-# VI:   buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
-0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03
+# VI:   buffer_load_format_x v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x00,0x02,0x03]
+0xff,0x7f,0x03,0xe0,0x00,0x00,0x02,0x03
 
 # VI:   buffer_store_lds_dword s[4:7], s0 lds ; encoding: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
 0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00