diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -509,7 +509,7 @@ (ops node:$src1, node:$src2), (select SCC, $src1, $src2), [{ return Subtarget->hasScalarCompareEq64() && - N->getOperand(0)->hasOneUse() && !N->isDivergent(); }] + !N->isDivergent(); }] >; let Uses = [SCC] in { diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll --- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll @@ -20,14 +20,13 @@ ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 -; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base ; GFX9: s_cmp_lg_u32 [[PTR]], -1 -; GFX9: s_cselect_b64 vcc, -1, 0 -; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc -; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] +; GFX9-DAG: s_cselect_b32 [[PTR]], [[PTR]], 0 +; GFX9-DAG: s_cselect_b32 [[SSRC_SHARED_BASE]], [[SSRC_SHARED_BASE]], 0 +; GFX9: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]] +; GFX9: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]] @@ -87,16 +86,15 @@ ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} ; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16 -; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]] ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; GFX9: s_cmp_lg_u32 [[PTR]], -1 -; GFX9: s_cselect_b64 vcc, -1, 0 -; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc -; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] +; GFX9-DAG: s_cselect_b32 [[PTR]], [[PTR]], 0 +; GFX9-DAG: s_cselect_b32 [[SSRC_PRIVATE_BASE]], [[SSRC_PRIVATE_BASE]], 0 +; GFX9: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]] +; GFX9: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_PRIVATE_BASE]] ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]] diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll @@ -551,10 +551,10 @@ ; GFX908-NEXT: v_mul_lo_u32 v5, v4, s1 ; GFX908-NEXT: v_add_u32_e32 v6, 1, v4 ; GFX908-NEXT: v_sub_u32_e32 v5, s0, v5 +; GFX908-NEXT: v_subrev_u32_e32 v7, s1, v5 ; GFX908-NEXT: v_cmp_le_u32_e32 vcc, s1, v5 ; GFX908-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX908-NEXT: v_subrev_u32_e32 v6, s1, v5 -; GFX908-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc +; GFX908-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX908-NEXT: v_add_u32_e32 v7, 1, v4 ; GFX908-NEXT: v_cmp_le_u32_e32 vcc, s1, v5 ; GFX908-NEXT: s_waitcnt vmcnt(0) @@ -696,10 +696,10 @@ ; GFX90A-NEXT: v_mul_lo_u32 v8, v0, s7 ; GFX90A-NEXT: v_sub_u32_e32 v8, s6, v8 ; GFX90A-NEXT: v_add_u32_e32 v9, 1, v0 +; GFX90A-NEXT: v_subrev_u32_e32 v11, s7, v8 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s7, v8 ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc -; GFX90A-NEXT: v_subrev_u32_e32 v9, s7, v8 -; GFX90A-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; GFX90A-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc ; GFX90A-NEXT: v_add_u32_e32 v9, 1, v0 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s7, v8 ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -85,10 +85,10 @@ ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 +; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -296,10 +296,10 @@ ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 +; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -1288,62 +1288,62 @@ ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_mul_f32_e32 v3, s12, v5 +; GFX9-NEXT: v_mul_f32_e32 v2, s12, v5 +; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GFX9-NEXT: v_mul_lo_u32 v3, v0, s8 +; GFX9-NEXT: v_add_u32_e32 v6, 1, v0 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1 -; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8 -; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s11 +; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX9-NEXT: v_add_u32_e32 v6, 1, v0 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, s2, v2 +; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11 +; GFX9-NEXT: v_mul_lo_u32 v5, v1, s9 +; GFX9-NEXT: v_add_u32_e32 v7, 1, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6 +; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_mul_f32_e32 v3, s12, v6 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: v_add_u32_e32 v7, 1, v0 -; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc -; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v5 -; GFX9-NEXT: v_mul_lo_u32 v6, v1, s9 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc -; GFX9-NEXT: v_add_u32_e32 v7, 1, v0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc +; GFX9-NEXT: s_sub_i32 s2, 0, s11 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3 -; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6 -; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6 -; GFX9-NEXT: v_mul_f32_e32 v2, s12, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc +; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v3, v7 -; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX9-NEXT: s_sub_i32 s2, 0, s11 -; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v6 +; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 +; GFX9-NEXT: v_mul_lo_u32 v8, v2, s10 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2 -; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX9-NEXT: v_add_u32_e32 v7, 1, v1 -; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, v3, s10 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc -; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_mul_hi_u32 v5, s7, v2 +; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 ; GFX9-NEXT: v_sub_u32_e32 v6, s6, v8 -; GFX9-NEXT: v_add_u32_e32 v7, 1, v3 +; GFX9-NEXT: v_subrev_u32_e32 v8, s10, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc -; GFX9-NEXT: v_subrev_u32_e32 v3, s10, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, v5, s11 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc +; GFX9-NEXT: v_mul_lo_u32 v6, v3, s11 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v2 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc -; GFX9-NEXT: v_sub_u32_e32 v3, s7, v6 -; GFX9-NEXT: v_add_u32_e32 v6, 1, v5 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v3 +; GFX9-NEXT: v_add_u32_e32 v7, 1, v2 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5 +; GFX9-NEXT: v_sub_u32_e32 v5, s7, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc +; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 +; GFX9-NEXT: v_subrev_u32_e32 v7, s11, v5 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; GFX9-NEXT: v_add_u32_e32 v6, 1, v5 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: s_endpgm %r = udiv <4 x i32> %x, %y @@ -1940,9 +1940,9 @@ ; GFX9-NEXT: s_add_i32 s3, s8, s2 ; GFX9-NEXT: s_xor_b32 s3, s3, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 -; GFX9-NEXT: s_ashr_i32 s12, s9, 31 -; GFX9-NEXT: s_add_i32 s9, s9, s12 -; GFX9-NEXT: s_xor_b32 s9, s9, s12 +; GFX9-NEXT: s_ashr_i32 s13, s9, 31 +; GFX9-NEXT: s_add_i32 s9, s9, s13 +; GFX9-NEXT: s_xor_b32 s9, s9, s13 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX9-NEXT: s_sub_i32 s14, 0, s3 @@ -1955,97 +1955,97 @@ ; GFX9-NEXT: v_mul_lo_u32 v2, s14, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s15, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: s_sub_i32 s14, 0, s9 +; GFX9-NEXT: s_xor_b32 s2, s8, s2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 -; GFX9-NEXT: s_ashr_i32 s13, s5, 31 -; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1 -; GFX9-NEXT: s_add_i32 s5, s5, s13 +; GFX9-NEXT: s_sub_i32 s8, 0, s9 +; GFX9-NEXT: s_ashr_i32 s12, s5, 31 +; GFX9-NEXT: s_add_i32 s5, s5, s12 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0 -; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3 -; GFX9-NEXT: s_xor_b32 s5, s5, s13 -; GFX9-NEXT: s_xor_b32 s2, s8, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, s8, v1 +; GFX9-NEXT: s_xor_b32 s5, s5, s12 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s3 +; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 +; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 +; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: s_ashr_i32 s4, s10, 31 +; GFX9-NEXT: s_add_i32 s8, s10, s4 +; GFX9-NEXT: s_xor_b32 s8, s8, s4 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 +; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s8 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1 -; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: v_subrev_u32_e32 v6, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 -; GFX9-NEXT: s_ashr_i32 s3, s10, 31 -; GFX9-NEXT: s_add_i32 s4, s10, s3 -; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 -; GFX9-NEXT: s_xor_b32 s4, s4, s3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s4 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, s9 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 +; GFX9-NEXT: v_mul_f32_e32 v2, s15, v2 +; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GFX9-NEXT: v_mul_lo_u32 v3, v1, s9 +; GFX9-NEXT: s_sub_i32 s3, 0, s8 +; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 +; GFX9-NEXT: v_mul_lo_u32 v7, s3, v2 +; GFX9-NEXT: v_sub_u32_e32 v3, s5, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; GFX9-NEXT: v_mul_hi_u32 v6, v2, v7 +; GFX9-NEXT: s_ashr_i32 s3, s6, 31 +; GFX9-NEXT: s_add_i32 s5, s6, s3 +; GFX9-NEXT: s_ashr_i32 s6, s11, 31 +; GFX9-NEXT: s_add_i32 s10, s11, s6 +; GFX9-NEXT: s_xor_b32 s10, s10, s6 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s10 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 -; GFX9-NEXT: s_ashr_i32 s8, s11, 31 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3 -; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: v_subrev_u32_e32 v5, s9, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: s_sub_i32 s5, 0, s4 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, s5, v3 -; GFX9-NEXT: s_add_i32 s9, s11, s8 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 -; GFX9-NEXT: s_xor_b32 s9, s9, s8 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX9-NEXT: v_mul_hi_u32 v2, v3, v2 -; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s9 -; GFX9-NEXT: s_ashr_i32 s5, s6, 31 -; GFX9-NEXT: s_add_i32 s6, s6, s5 -; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v5 -; GFX9-NEXT: s_xor_b32 s6, s6, s5 -; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v6 +; GFX9-NEXT: s_xor_b32 s5, s5, s3 +; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 -; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GFX9-NEXT: v_mul_f32_e32 v5, s15, v5 +; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0 -; GFX9-NEXT: s_xor_b32 s2, s13, s12 -; GFX9-NEXT: v_mul_lo_u32 v5, v2, s4 +; GFX9-NEXT: s_xor_b32 s2, s12, s13 ; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 +; GFX9-NEXT: v_mul_lo_u32 v3, v2, s8 ; GFX9-NEXT: v_subrev_u32_e32 v1, s2, v1 -; GFX9-NEXT: s_xor_b32 s2, s5, s3 -; GFX9-NEXT: s_sub_i32 s3, 0, s9 -; GFX9-NEXT: v_mul_lo_u32 v7, s3, v3 -; GFX9-NEXT: v_sub_u32_e32 v5, s6, v5 +; GFX9-NEXT: s_xor_b32 s2, s3, s4 +; GFX9-NEXT: s_sub_i32 s3, 0, s10 +; GFX9-NEXT: v_mul_lo_u32 v8, s3, v5 +; GFX9-NEXT: v_sub_u32_e32 v3, s5, v3 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v2 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX9-NEXT: v_subrev_u32_e32 v6, s4, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_mul_hi_u32 v6, v3, v7 +; GFX9-NEXT: v_mul_hi_u32 v6, v5, v8 ; GFX9-NEXT: s_ashr_i32 s3, s7, 31 -; GFX9-NEXT: s_add_i32 s5, s7, s3 -; GFX9-NEXT: s_xor_b32 s5, s5, s3 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 -; GFX9-NEXT: v_mul_hi_u32 v3, s5, v3 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5 +; GFX9-NEXT: s_add_i32 s4, s7, s3 +; GFX9-NEXT: s_xor_b32 s4, s4, s3 +; GFX9-NEXT: v_add_u32_e32 v5, v5, v6 +; GFX9-NEXT: v_mul_hi_u32 v5, s4, v5 +; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 +; GFX9-NEXT: v_mul_lo_u32 v3, v5, s10 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v5, v3, s9 -; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 +; GFX9-NEXT: v_add_u32_e32 v6, 1, v5 +; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: v_subrev_u32_e32 v7, s10, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2 +; GFX9-NEXT: v_add_u32_e32 v6, 1, v5 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2 -; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 -; GFX9-NEXT: s_xor_b32 s2, s3, s8 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; GFX9-NEXT: s_xor_b32 s2, s3, s6 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc ; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v3 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] @@ -5735,23 +5735,23 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX9-NEXT: s_movk_i32 s2, 0x1000 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshl_b32 s6, s2, s6 -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 -; GFX9-NEXT: s_lshl_b32 s7, s2, s7 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 -; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe +; GFX9-NEXT: s_lshl_b32 s3, s2, s7 +; GFX9-NEXT: s_lshl_b32 s2, s2, s6 +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GFX9-NEXT: s_mov_b32 s6, 0x4f7ffffe +; GFX9-NEXT: s_sub_i32 s7, 0, s3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX9-NEXT: s_sub_i32 s3, 0, s7 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, s6, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX9-NEXT: v_mul_f32_e32 v1, s6, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: s_sub_i32 s2, 0, s6 -; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 -; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: s_sub_i32 s6, 0, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, s6, v0 +; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 @@ -5759,28 +5759,27 @@ ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: v_mul_lo_u32 v3, v0, s6 +; GFX9-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 -; GFX9-NEXT: v_mul_lo_u32 v4, v1, s7 +; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 +; GFX9-NEXT: v_subrev_u32_e32 v7, s2, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc -; GFX9-NEXT: v_subrev_u32_e32 v5, s6, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 -; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1] -; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GFX9-NEXT: v_add_u32_e32 v7, 1, v0 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 +; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: s_endpgm %shl.y = shl <2 x i32> , %y %r = udiv <2 x i32> %x, %shl.y @@ -6268,13 +6267,13 @@ ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 +; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 +; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: s_xor_b32 s2, s5, s4 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0 @@ -6597,11 +6596,11 @@ ; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4 ; GFX9-NEXT: s_xor_b32 s4, s5, s9 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v4 ; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1 +; GFX9-NEXT: v_subrev_u32_e32 v6, s1, v4 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc -; GFX9-NEXT: v_subrev_u32_e32 v5, s1, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc @@ -6610,10 +6609,10 @@ ; GFX9-NEXT: s_xor_b32 s1, s9, s8 ; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: v_subrev_u32_e32 v5, s0, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX9-NEXT: v_subrev_u32_e32 v4, s0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc @@ -7298,12 +7297,13 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v5, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], 2, v0 +; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], 1, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v0 +; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v8, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v9, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2 @@ -7313,9 +7313,8 @@ ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v5, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: s_endpgm %r = udiv i64 %x, 1235195949943 @@ -7615,9 +7614,9 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX9-NEXT: s_movk_i32 s0, 0xfff ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 12 +; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 12 +; GFX9-NEXT: s_movk_i32 s4, 0xfff ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc @@ -7639,36 +7638,36 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0 -; GFX9-NEXT: v_mul_lo_u32 v4, v1, s0 -; GFX9-NEXT: v_mul_hi_u32 v6, v0, s0 -; GFX9-NEXT: v_mul_lo_u32 v9, v0, s0 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 1, v0 +; GFX9-NEXT: v_mul_lo_u32 v4, v1, s4 +; GFX9-NEXT: v_mul_hi_u32 v6, v0, s4 +; GFX9-NEXT: v_mul_lo_u32 v9, v0, s4 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 2, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4 ; GFX9-NEXT: v_mov_b32_e32 v6, s7 ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s6, v9 ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v6, v4, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s0, v9 +; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s4, v9 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc -; GFX9-NEXT: s_movk_i32 s0, 0xffe -; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6 +; GFX9-NEXT: s_movk_i32 s4, 0xffe +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s4, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc -; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, -1, v6, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s4, v9 +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, -1, v6, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[2:3] ; GFX9-NEXT: s_endpgm %r = udiv <2 x i64> %x, @@ -7958,19 +7957,19 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v5, s7 -; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] +; GFX9-NEXT: v_mov_b32_e32 v4, s7 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: s_endpgm %r = urem i64 %x, 1235195393993 @@ -8298,18 +8297,18 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 -; GFX9-NEXT: s_mov_b32 s2, 0xffed2705 +; GFX9-NEXT: s_mov_b32 s4, 0xffed2705 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, s2 -; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 -; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 @@ -8328,12 +8327,12 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc -; GFX9-NEXT: v_mul_lo_u32 v2, v1, s2 -; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 -; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_ashr_i32 s2, s7, 31 -; GFX9-NEXT: s_add_u32 s0, s6, s2 +; GFX9-NEXT: s_ashr_i32 s4, s3, 31 +; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 @@ -8351,59 +8350,59 @@ ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 -; GFX9-NEXT: s_mov_b32 s3, s2 -; GFX9-NEXT: s_addc_u32 s1, s7, s2 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc -; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] -; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1 -; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1 -; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 +; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0 -; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0 -; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb +; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 +; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0 -; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mul_hi_u32 v6, v0, s3 -; GFX9-NEXT: v_mul_lo_u32 v9, v0, s3 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 1, v0 +; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5 +; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5 +; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 2, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4 -; GFX9-NEXT: v_mov_b32_e32 v6, s1 -; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s0, v9 +; GFX9-NEXT: v_mov_b32_e32 v6, s3 +; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s2, v9 ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v6, v4, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s3, v9 +; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s5, v9 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc -; GFX9-NEXT: s_mov_b32 s0, 0x12d8fa -; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6 +; GFX9-NEXT: s_mov_b32 s2, 0x12d8fa +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc -; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, -1, v6, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 -; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 -; GFX9-NEXT: v_mov_b32_e32 v2, s2 -; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v9 +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, -1, v6, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0 +; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0 ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] +; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1] ; GFX9-NEXT: s_endpgm %r = sdiv i64 %x, 1235195 store i64 %r, i64 addrspace(1)* %out @@ -8705,12 +8704,13 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v0 +; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 1, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v0 +; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 @@ -8720,10 +8720,9 @@ ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[2:3] -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 @@ -8949,9 +8948,14 @@ ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_ashr_i32 s2, s5, 31 +; GFX9-NEXT: s_lshr_b32 s2, s2, 20 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8 +; GFX9-NEXT: s_add_u32 s2, s4, s2 +; GFX9-NEXT: s_addc_u32 s3, s5, 0 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 @@ -8963,6 +8967,8 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 +; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 12 +; GFX9-NEXT: s_ashr_i32 s4, s7, 31 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc @@ -8973,9 +8979,8 @@ ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8 -; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_ashr_i32 s2, s5, 31 +; GFX9-NEXT: s_add_u32 s6, s6, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 @@ -8987,19 +8992,12 @@ ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: s_lshr_b32 s2, s2, 20 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX9-NEXT: s_add_u32 s2, s4, s2 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc -; GFX9-NEXT: s_addc_u32 s3, s5, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc -; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 12 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 -; GFX9-NEXT: s_ashr_i32 s4, s7, 31 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX9-NEXT: s_add_u32 s6, s6, s4 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 -; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s7, s7, s4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] @@ -9012,40 +9010,41 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 -; GFX9-NEXT: s_movk_i32 s0, 0xfff +; GFX9-NEXT: s_movk_i32 s5, 0xfff +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0 -; GFX9-NEXT: v_mul_lo_u32 v5, v1, s0 -; GFX9-NEXT: v_mul_hi_u32 v6, v0, s0 -; GFX9-NEXT: v_mul_lo_u32 v9, v0, s0 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 1, v0 +; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5 +; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5 +; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 2, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_mov_b32_e32 v6, s7 ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s6, v9 ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v6, v5, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s0, v9 +; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s5, v9 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v5, vcc -; GFX9-NEXT: s_movk_i32 s0, 0xffe -; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6 +; GFX9-NEXT: s_movk_i32 s5, 0xffe +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s5, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc -; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v5, -1, v6, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s5, v9 +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v5, -1, v6, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, s4 @@ -9053,7 +9052,8 @@ ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: s_endpgm %r = sdiv <2 x i64> %x, store <2 x i64> %r, <2 x i64> addrspace(1)* %out @@ -9425,7 +9425,6 @@ ; GFX9-NEXT: v_mul_lo_u32 v5, s5, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13] ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v4, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v0, vcc @@ -9449,70 +9448,71 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v1 +; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 1, v1 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v1 +; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v1 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1] -; GFX9-NEXT: s_ashr_i32 s4, s11, 31 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] +; GFX9-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13] +; GFX9-NEXT: s_ashr_i32 s4, s11, 31 ; GFX9-NEXT: s_add_u32 s10, s10, s4 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s11, s11, s4 ; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[4:5] -; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s10 -; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s11 ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc +; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s10 +; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s11 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v4 +; GFX9-NEXT: v_mac_f32_e32 v7, s16, v8 +; GFX9-NEXT: v_rcp_f32_e32 v7, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 -; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc -; GFX9-NEXT: v_rcp_f32_e32 v4, v9 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1] -; GFX9-NEXT: v_mul_f32_e32 v4, s17, v4 -; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4 -; GFX9-NEXT: v_trunc_f32_e32 v5, v5 -; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5 +; GFX9-NEXT: v_mul_f32_e32 v3, s17, v7 +; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3 +; GFX9-NEXT: v_trunc_f32_e32 v4, v4 +; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4 +; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GFX9-NEXT: s_sub_u32 s0, 0, s10 -; GFX9-NEXT: s_subb_u32 s1, 0, s11 -; GFX9-NEXT: v_mul_hi_u32 v6, s0, v4 -; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_mul_lo_u32 v3, s0, v4 +; GFX9-NEXT: s_sub_u32 s8, 0, s10 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX9-NEXT: s_subb_u32 s9, 0, s11 +; GFX9-NEXT: v_mul_hi_u32 v6, s8, v3 +; GFX9-NEXT: v_mul_lo_u32 v7, s8, v4 +; GFX9-NEXT: v_mul_lo_u32 v8, s9, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s8, v3 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v7 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 -; GFX9-NEXT: v_mul_lo_u32 v7, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v8, v4, v3 -; GFX9-NEXT: v_mul_hi_u32 v9, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6 -; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 +; GFX9-NEXT: v_mul_lo_u32 v7, v3, v6 +; GFX9-NEXT: v_mul_hi_u32 v8, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v9, v3, v6 +; GFX9-NEXT: v_mul_hi_u32 v10, v4, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc -; GFX9-NEXT: v_mul_lo_u32 v9, v5, v3 -; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3 -; GFX9-NEXT: s_ashr_i32 s8, s7, 31 -; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: v_mul_lo_u32 v9, v4, v5 +; GFX9-NEXT: v_mul_hi_u32 v5, v4, v5 +; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 +; GFX9-NEXT: v_xor_b32_e32 v2, s1, v2 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4 -; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3 -; GFX9-NEXT: v_mul_lo_u32 v7, s1, v3 -; GFX9-NEXT: v_mul_lo_u32 v8, s0, v3 -; GFX9-NEXT: s_add_u32 s0, s6, s8 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s8, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s8, v3 +; GFX9-NEXT: v_mul_lo_u32 v7, s9, v3 +; GFX9-NEXT: v_mul_lo_u32 v8, s8, v3 +; GFX9-NEXT: s_ashr_i32 s8, s7, 31 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5 @@ -9529,10 +9529,12 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v0, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX9-NEXT: s_add_u32 s6, s6, s8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 -; GFX9-NEXT: s_addc_u32 s1, s7, s8 +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_addc_u32 s7, s7, s8 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc -; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9] +; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9] ; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, s6, v4 @@ -9542,8 +9544,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 -; GFX9-NEXT: v_xor_b32_e32 v1, s12, v1 -; GFX9-NEXT: v_xor_b32_e32 v2, s13, v2 +; GFX9-NEXT: v_mov_b32_e32 v7, s1 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v0, vcc @@ -9552,8 +9553,7 @@ ; GFX9-NEXT: v_mul_lo_u32 v5, s10, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3 -; GFX9-NEXT: v_mov_b32_e32 v7, s13 -; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v1 +; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v1 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s10, v3 ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc @@ -9570,12 +9570,13 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v3 +; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v3 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 1, v3 +; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 2, v3 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 -; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, v11, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v9, s7 ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5 @@ -9585,10 +9586,9 @@ ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX9-NEXT: v_xor_b32_e32 v4, s1, v4 ; GFX9-NEXT: v_mov_b32_e32 v5, s1 @@ -9729,18 +9729,18 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 -; GFX9-NEXT: s_mov_b32 s2, 0xffed2705 +; GFX9-NEXT: s_mov_b32 s4, 0xffed2705 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, s2 -; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 -; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 @@ -9759,12 +9759,12 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc -; GFX9-NEXT: v_mul_lo_u32 v2, v1, s2 -; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 -; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_ashr_i32 s2, s7, 31 -; GFX9-NEXT: s_add_u32 s0, s6, s2 +; GFX9-NEXT: s_ashr_i32 s4, s3, 31 +; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 @@ -9782,57 +9782,57 @@ ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 -; GFX9-NEXT: s_mov_b32 s3, s2 -; GFX9-NEXT: s_addc_u32 s1, s7, s2 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc -; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] -; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1 -; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1 -; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 +; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0 -; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0 -; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb +; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 +; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc -; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3 -; GFX9-NEXT: v_mul_hi_u32 v2, v0, s3 -; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3 +; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5 +; GFX9-NEXT: v_mul_hi_u32 v2, v0, s5 +; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0 ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s3, v0 +; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s5, v0 ; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s3, v2 +; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s5, v2 ; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc -; GFX9-NEXT: s_mov_b32 s0, 0x12d8fa -; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2 +; GFX9-NEXT: s_mov_b32 s2, 0x12d8fa +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 -; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 -; GFX9-NEXT: v_mov_b32_e32 v2, s2 -; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0 +; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0 +; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0 ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] +; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1] ; GFX9-NEXT: s_endpgm %r = srem i64 %x, 1235195 store i64 %r, i64 addrspace(1)* %out @@ -10140,19 +10140,19 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v6, s7 -; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v6, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[0:1] +; GFX9-NEXT: v_mov_b32_e32 v5, s7 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, s10, v0 ; GFX9-NEXT: v_xor_b32_e32 v1, s10, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, s10 @@ -10619,66 +10619,66 @@ ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v5 +; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] -; GFX9-NEXT: s_ashr_i32 s2, s11, 31 -; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1] -; GFX9-NEXT: s_add_u32 s10, s10, s2 ; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s12, v5 -; GFX9-NEXT: s_mov_b32 s3, s2 -; GFX9-NEXT: s_addc_u32 s11, s11, s2 +; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1] -; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[2:3] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 -; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s10 -; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s11 +; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v6, s15 -; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v6, v2, vcc +; GFX9-NEXT: s_ashr_i32 s0, s11, 31 +; GFX9-NEXT: s_add_u32 s2, s10, s0 +; GFX9-NEXT: s_mov_b32 s1, s0 +; GFX9-NEXT: s_addc_u32 s3, s11, s0 +; GFX9-NEXT: v_mov_b32_e32 v5, s15 +; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[0:1] +; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc +; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10 +; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 -; GFX9-NEXT: v_mac_f32_e32 v7, s16, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v1 -; GFX9-NEXT: v_rcp_f32_e32 v7, v7 -; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GFX9-NEXT: v_mac_f32_e32 v5, s16, v6 +; GFX9-NEXT: v_rcp_f32_e32 v5, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] -; GFX9-NEXT: v_mul_f32_e32 v4, s17, v7 -; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4 +; GFX9-NEXT: v_mul_f32_e32 v3, s17, v5 +; GFX9-NEXT: v_mul_f32_e32 v5, s18, v3 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5 -; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5 -; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GFX9-NEXT: v_mac_f32_e32 v3, s19, v5 +; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: s_sub_u32 s0, 0, s10 ; GFX9-NEXT: s_subb_u32 s1, 0, s11 -; GFX9-NEXT: v_mul_hi_u32 v6, s0, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_mul_lo_u32 v3, s0, v4 +; GFX9-NEXT: v_mul_lo_u32 v8, s1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GFX9-NEXT: v_mul_lo_u32 v4, s0, v3 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v7 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 -; GFX9-NEXT: v_mul_lo_u32 v7, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v8, v4, v3 -; GFX9-NEXT: v_mul_hi_u32 v9, v4, v6 +; GFX9-NEXT: v_mul_lo_u32 v7, v3, v6 +; GFX9-NEXT: v_mul_hi_u32 v8, v3, v4 +; GFX9-NEXT: v_mul_hi_u32 v9, v3, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc -; GFX9-NEXT: v_mul_lo_u32 v9, v5, v3 -; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3 +; GFX9-NEXT: v_mul_lo_u32 v9, v5, v4 +; GFX9-NEXT: v_mul_hi_u32 v4, v5, v4 ; GFX9-NEXT: s_ashr_i32 s12, s7, 31 ; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3 @@ -10746,19 +10746,19 @@ ; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v8, s7 -; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v8, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1] +; GFX9-NEXT: v_mov_b32_e32 v7, s7 +; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3 ; GFX9-NEXT: v_xor_b32_e32 v4, s12, v4 ; GFX9-NEXT: v_mov_b32_e32 v5, s12 diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll --- a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll @@ -40,10 +40,10 @@ } ; GCN-LABEL: {{^}}select_and_v4: -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0 ; GCN-NOT: v_and_b32 ; GCN: store_dword define amdgpu_kernel void @select_and_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) { @@ -94,10 +94,10 @@ } ; GCN-LABEL: {{^}}select_or_v4: -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, -; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1 ; GCN-NOT: v_or_b32 ; GCN: store_dword define amdgpu_kernel void @select_or_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) { @@ -147,10 +147,10 @@ } ; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v4i32: -; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9, -; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 6, 5, -; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 10, 6, -; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 14, 7, +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 9, 2 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 5, 6 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 6, 10 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 7, 14 define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(<4 x i32> addrspace(1)* %p, i1 %cond) { %sel = select i1 %cond, <4 x i32> , <4 x i32> %bo = sub <4 x i32> , %sel @@ -261,14 +261,11 @@ } ; GCN-LABEL: {{^}}fsub_constant_sel_constants_v4f32: -; GCN-DAG: v_mov_b32_e32 [[T2:v[0-9]+]], 0x40a00000 -; GCN-DAG: v_mov_b32_e32 [[T3:v[0-9]+]], 0x41100000 -; GCN-DAG: v_mov_b32_e32 [[T4:v[0-9]+]], 0x41500000 -; GCN-DAG: v_mov_b32_e32 [[F4:v[0-9]+]], 0x40c00000 -; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, -; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, [[T2]], -; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, [[T3]], -; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, [[F4]], [[T4]], +; GCN-DAG: s_mov_b32 [[T4:s[0-9]+]], 0x41500000 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 1.0, 0 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 0x40a00000, 2.0 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, 0x41100000, 4.0 +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, [[T4]], 0x40c00000 define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(<4 x float> addrspace(1)* %p, i1 %cond) { %sel = select i1 %cond, <4 x float> , <4 x float> %bo = fsub <4 x float> , %sel diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -30,11 +30,12 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX9-NEXT: s_addc_u32 s4, s6, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 +; GFX9-NEXT: s_addc_u32 s7, s6, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 +; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec +; GFX9-NEXT: s_cselect_b32 s4, s7, 0 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -50,10 +51,11 @@ ; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0 ; GFX10-NEXT: s_addc_u32 s5, s4, 0 ; GFX10-NEXT: s_cselect_b32 s6, -1, 0 +; GFX10-NEXT: s_and_b32 s6, s6, exec_lo +; GFX10-NEXT: s_cselect_b32 s5, s5, 0 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] bb: %i = load volatile i32, i32 addrspace(4)* null, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll --- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll +++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll @@ -38,15 +38,15 @@ ; GCN-LABEL: {{^}}double4_extelt: ; GCN-NOT: buffer_ -; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 -; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 -; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3 -; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] +; GCN: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} +; GCN: s_cmp_eq_u32 [[IDX]], 2 +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cmp_eq_u32 [[IDX]], 3 +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @double4_extelt(double addrspace(1)* %out, i32 %sel) { entry: @@ -55,20 +55,24 @@ ret void } +; FIXME: Compares and selects are being reordered, generating ugly code to copy +; scc into an sgpr pair. + ; GCN-LABEL: {{^}}double5_extelt: ; GCN-NOT: buffer_ -; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 -; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 -; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3 -; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 -; GCN-DAG: s_cmp_eq_u32 [[IDX]], 4 -; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C4]] +; GCN: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} +; GCN: s_cmp_eq_u32 [[IDX]], 2 +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cmp_eq_u32 [[IDX]], 3 +; GCN: s_cselect_b64 s[{{[0-9]+:[0-9]+}}], -1, 0 +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cmp_eq_u32 [[IDX]], 4 +; GCN: s_cselect_b64 s[{{[0-9]+:[0-9]+}}], -1, 0 +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} +; GCN: s_cselect_b32 s{{[0-9]+}}, {{[^,]+}}, s{{[0-9]+}} ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @double5_extelt(double addrspace(1)* %out, i32 %sel) { entry: @@ -108,9 +112,8 @@ ; GCN-LABEL: {{^}}double2_extelt: ; GCN-NOT: buffer_ ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} +; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, {{[^,]+}} ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @double2_extelt(double addrspace(1)* %out, i32 %sel) { entry: diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll --- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll +++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2: ; GCN: buffer_load_dwordx4 @@ -15,13 +15,15 @@ ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3f64: ; GCN-NOT: buffer_load ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @dyn_extract_vector_elt_v3f64(double addrspace(1)* %out, <3 x double> %foo, i32 %elt) #0 { %dynelt = extractelement <3 x double> %foo, i32 %elt @@ -32,17 +34,20 @@ ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4f64: ; GCN-NOT: buffer_load ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3 -; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] +; SI-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @dyn_extract_vector_elt_v4f64(double addrspace(1)* %out, <4 x double> %foo, i32 %elt) #0 { %dynelt = extractelement <4 x double> %foo, i32 %elt diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll --- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; How the replacement of i64 stores with v2i32 stores resulted in ; breaking other users of the bitcast if they already existed @@ -32,9 +32,10 @@ ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64: ; GCN-NOT: buffer_load ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @dyn_extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo, i32 %elt) #0 { %dynelt = extractelement <2 x i64> %foo, i32 %elt @@ -61,13 +62,15 @@ ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3i64: ; GCN-NOT: buffer_load ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @dyn_extract_vector_elt_v3i64(i64 addrspace(1)* %out, <3 x i64> %foo, i32 %elt) #0 { %dynelt = extractelement <3 x i64> %foo, i32 %elt @@ -78,17 +81,20 @@ ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4i64: ; GCN-NOT: buffer_load ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1 -; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2 -; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; SI-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3 -; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] -; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] +; SI-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0 +; VI-COUNT-2: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] +; SI-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN: store_dwordx2 v[{{[0-9:]+}}] define amdgpu_kernel void @dyn_extract_vector_elt_v4i64(i64 addrspace(1)* %out, <4 x i64> %foo, i32 %elt) #0 { %dynelt = extractelement <4 x i64> %foo, i32 %elt diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll --- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll +++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll @@ -29,9 +29,9 @@ ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 +; GFX9-NEXT: v_add_u32_e32 v5, s2, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX9-NEXT: v_add_u32_e32 v4, s2, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: s_add_u32 s2, s2, 1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 @@ -227,10 +227,10 @@ ; GFX9-NEXT: v_mul_lo_u32 v3, v2, s3 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 +; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 1, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc diff --git a/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll b/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll --- a/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll +++ b/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll @@ -16,17 +16,15 @@ ; GFX8V3-NEXT: v_mov_b32_e32 v4, 1 ; GFX8V3-NEXT: s_waitcnt lgkmcnt(0) ; GFX8V3-NEXT: s_cmp_lg_u32 s0, -1 -; GFX8V3-NEXT: v_mov_b32_e32 v0, s2 -; GFX8V3-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V3-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc -; GFX8V3-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V3-NEXT: s_cselect_b32 s2, s2, 0 +; GFX8V3-NEXT: s_cselect_b32 s0, s0, 0 ; GFX8V3-NEXT: s_cmp_lg_u32 s1, -1 -; GFX8V3-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX8V3-NEXT: v_mov_b32_e32 v2, s3 -; GFX8V3-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V3-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX8V3-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V3-NEXT: v_mov_b32_e32 v1, s2 +; GFX8V3-NEXT: s_cselect_b32 s0, s3, 0 +; GFX8V3-NEXT: s_cselect_b32 s1, s1, 0 ; GFX8V3-NEXT: v_mov_b32_e32 v2, s1 -; GFX8V3-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8V3-NEXT: v_mov_b32_e32 v3, s0 ; GFX8V3-NEXT: flat_store_dword v[0:1], v4 ; GFX8V3-NEXT: s_waitcnt vmcnt(0) ; GFX8V3-NEXT: v_mov_b32_e32 v0, 2 @@ -42,17 +40,15 @@ ; GFX8V4-NEXT: v_mov_b32_e32 v4, 1 ; GFX8V4-NEXT: s_waitcnt lgkmcnt(0) ; GFX8V4-NEXT: s_cmp_lg_u32 s0, -1 -; GFX8V4-NEXT: v_mov_b32_e32 v0, s2 -; GFX8V4-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V4-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc -; GFX8V4-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V4-NEXT: s_cselect_b32 s2, s2, 0 +; GFX8V4-NEXT: s_cselect_b32 s0, s0, 0 ; GFX8V4-NEXT: s_cmp_lg_u32 s1, -1 -; GFX8V4-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX8V4-NEXT: v_mov_b32_e32 v2, s3 -; GFX8V4-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V4-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX8V4-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V4-NEXT: v_mov_b32_e32 v1, s2 +; GFX8V4-NEXT: s_cselect_b32 s0, s3, 0 +; GFX8V4-NEXT: s_cselect_b32 s1, s1, 0 ; GFX8V4-NEXT: v_mov_b32_e32 v2, s1 -; GFX8V4-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8V4-NEXT: v_mov_b32_e32 v3, s0 ; GFX8V4-NEXT: flat_store_dword v[0:1], v4 ; GFX8V4-NEXT: s_waitcnt vmcnt(0) ; GFX8V4-NEXT: v_mov_b32_e32 v0, 2 @@ -68,17 +64,15 @@ ; GFX8V5-NEXT: v_mov_b32_e32 v4, 1 ; GFX8V5-NEXT: s_waitcnt lgkmcnt(0) ; GFX8V5-NEXT: s_cmp_lg_u32 s0, -1 -; GFX8V5-NEXT: v_mov_b32_e32 v0, s2 -; GFX8V5-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V5-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc -; GFX8V5-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V5-NEXT: s_cselect_b32 s2, s2, 0 +; GFX8V5-NEXT: s_cselect_b32 s0, s0, 0 ; GFX8V5-NEXT: s_cmp_lg_u32 s1, -1 -; GFX8V5-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX8V5-NEXT: v_mov_b32_e32 v2, s3 -; GFX8V5-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX8V5-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX8V5-NEXT: v_mov_b32_e32 v0, s0 +; GFX8V5-NEXT: v_mov_b32_e32 v1, s2 +; GFX8V5-NEXT: s_cselect_b32 s0, s3, 0 +; GFX8V5-NEXT: s_cselect_b32 s1, s1, 0 ; GFX8V5-NEXT: v_mov_b32_e32 v2, s1 -; GFX8V5-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8V5-NEXT: v_mov_b32_e32 v3, s0 ; GFX8V5-NEXT: flat_store_dword v[0:1], v4 ; GFX8V5-NEXT: s_waitcnt vmcnt(0) ; GFX8V5-NEXT: v_mov_b32_e32 v0, 2 @@ -91,22 +85,20 @@ ; GFX9V3-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9V3-NEXT: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9V3-NEXT: s_lshl_b32 s2, s2, 16 -; GFX9V3-NEXT: v_mov_b32_e32 v0, s2 ; GFX9V3-NEXT: v_mov_b32_e32 v4, 1 ; GFX9V3-NEXT: s_waitcnt lgkmcnt(0) ; GFX9V3-NEXT: s_cmp_lg_u32 s0, -1 -; GFX9V3-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V3-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX9V3-NEXT: s_cselect_b32 s0, s0, 0 ; GFX9V3-NEXT: v_mov_b32_e32 v0, s0 ; GFX9V3-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9V3-NEXT: s_cselect_b32 s2, s2, 0 ; GFX9V3-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9V3-NEXT: s_cmp_lg_u32 s1, -1 -; GFX9V3-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX9V3-NEXT: v_mov_b32_e32 v2, s0 -; GFX9V3-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V3-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX9V3-NEXT: v_mov_b32_e32 v1, s2 +; GFX9V3-NEXT: s_cselect_b32 s0, s0, 0 +; GFX9V3-NEXT: s_cselect_b32 s1, s1, 0 ; GFX9V3-NEXT: v_mov_b32_e32 v2, s1 -; GFX9V3-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9V3-NEXT: v_mov_b32_e32 v3, s0 ; GFX9V3-NEXT: flat_store_dword v[0:1], v4 ; GFX9V3-NEXT: s_waitcnt vmcnt(0) ; GFX9V3-NEXT: v_mov_b32_e32 v0, 2 @@ -119,22 +111,20 @@ ; GFX9V4-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9V4-NEXT: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9V4-NEXT: s_lshl_b32 s2, s2, 16 -; GFX9V4-NEXT: v_mov_b32_e32 v0, s2 ; GFX9V4-NEXT: v_mov_b32_e32 v4, 1 ; GFX9V4-NEXT: s_waitcnt lgkmcnt(0) ; GFX9V4-NEXT: s_cmp_lg_u32 s0, -1 -; GFX9V4-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V4-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX9V4-NEXT: s_cselect_b32 s0, s0, 0 ; GFX9V4-NEXT: v_mov_b32_e32 v0, s0 ; GFX9V4-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9V4-NEXT: s_cselect_b32 s2, s2, 0 ; GFX9V4-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9V4-NEXT: s_cmp_lg_u32 s1, -1 -; GFX9V4-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX9V4-NEXT: v_mov_b32_e32 v2, s0 -; GFX9V4-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V4-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX9V4-NEXT: v_mov_b32_e32 v1, s2 +; GFX9V4-NEXT: s_cselect_b32 s0, s0, 0 +; GFX9V4-NEXT: s_cselect_b32 s1, s1, 0 ; GFX9V4-NEXT: v_mov_b32_e32 v2, s1 -; GFX9V4-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9V4-NEXT: v_mov_b32_e32 v3, s0 ; GFX9V4-NEXT: flat_store_dword v[0:1], v4 ; GFX9V4-NEXT: s_waitcnt vmcnt(0) ; GFX9V4-NEXT: v_mov_b32_e32 v0, 2 @@ -147,22 +137,20 @@ ; GFX9V5-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9V5-NEXT: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9V5-NEXT: s_lshl_b32 s2, s2, 16 -; GFX9V5-NEXT: v_mov_b32_e32 v0, s2 ; GFX9V5-NEXT: v_mov_b32_e32 v4, 1 ; GFX9V5-NEXT: s_waitcnt lgkmcnt(0) ; GFX9V5-NEXT: s_cmp_lg_u32 s0, -1 -; GFX9V5-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V5-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX9V5-NEXT: s_cselect_b32 s0, s0, 0 ; GFX9V5-NEXT: v_mov_b32_e32 v0, s0 ; GFX9V5-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) +; GFX9V5-NEXT: s_cselect_b32 s2, s2, 0 ; GFX9V5-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9V5-NEXT: s_cmp_lg_u32 s1, -1 -; GFX9V5-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc -; GFX9V5-NEXT: v_mov_b32_e32 v2, s0 -; GFX9V5-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9V5-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc +; GFX9V5-NEXT: v_mov_b32_e32 v1, s2 +; GFX9V5-NEXT: s_cselect_b32 s0, s0, 0 +; GFX9V5-NEXT: s_cselect_b32 s1, s1, 0 ; GFX9V5-NEXT: v_mov_b32_e32 v2, s1 -; GFX9V5-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9V5-NEXT: v_mov_b32_e32 v3, s0 ; GFX9V5-NEXT: flat_store_dword v[0:1], v4 ; GFX9V5-NEXT: s_waitcnt vmcnt(0) ; GFX9V5-NEXT: v_mov_b32_e32 v0, 2 diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll b/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll --- a/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll @@ -12,65 +12,32 @@ ; CHECK: ; %bb.0: ; %bb ; CHECK-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 -; CHECK-NEXT: s_mov_b64 s[4:5], 0 -; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0 ; CHECK-NEXT: s_add_u32 s0, s0, s7 ; CHECK-NEXT: s_addc_u32 s1, s1, 0 -; CHECK-NEXT: s_mov_b32 s33, s6 -; CHECK-NEXT: v_mov_b32_e32 v31, v0 -; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: s_bitcmp1_b32 s4, 0 -; CHECK-NEXT: s_cselect_b64 vcc, -1, 0 +; CHECK-NEXT: s_mov_b64 s[4:5], 0 +; CHECK-NEXT: s_load_dword s7, s[4:5], 0x0 ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, wobble@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, wobble@gotpcrel32@hi+12 -; CHECK-NEXT: s_getpc_b64 s[6:7] -; CHECK-NEXT: s_add_u32 s6, s6, snork@gotpcrel32@lo+4 -; CHECK-NEXT: s_addc_u32 s7, s7, snork@gotpcrel32@hi+12 -; CHECK-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0 -; CHECK-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x0 -; CHECK-NEXT: s_mov_b32 s32, 0 -; CHECK-NEXT: s_mov_b64 s[4:5], exec +; CHECK-NEXT: s_getpc_b64 s[8:9] +; CHECK-NEXT: s_add_u32 s8, s8, snork@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s9, s9, snork@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0 +; CHECK-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0 +; CHECK-NEXT: s_mov_b64 s[8:9], 0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: v_mov_b32_e32 v0, s9 -; CHECK-NEXT: v_mov_b32_e32 v1, s11 -; CHECK-NEXT: v_mov_b32_e32 v2, s8 -; CHECK-NEXT: v_mov_b32_e32 v4, s10 -; CHECK-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc -; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; CHECK-NEXT: s_and_b32 s4, 1, s7 +; CHECK-NEXT: s_cmp_eq_u32 s4, 1 +; CHECK-NEXT: v_mov_b32_e32 v31, v0 +; CHECK-NEXT: s_cselect_b32 s5, s13, s11 +; CHECK-NEXT: s_cselect_b32 s4, s12, s10 +; CHECK-NEXT: s_mov_b32 s12, s6 ; CHECK-NEXT: v_mov_b32_e32 v1, 0 -; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: v_readfirstlane_b32 s4, v2 -; CHECK-NEXT: v_readfirstlane_b32 s5, v3 -; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[2:3] -; CHECK-NEXT: s_and_saveexec_b64 s[34:35], vcc -; CHECK-NEXT: s_mov_b64 s[8:9], 0 -; CHECK-NEXT: s_mov_b32 s12, s33 -; CHECK-NEXT: v_mov_b32_e32 v4, v1 +; CHECK-NEXT: v_mov_b32_e32 v4, 0 +; CHECK-NEXT: s_mov_b32 s32, 0 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5] -; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3 -; CHECK-NEXT: ; implicit-def: $vgpr31 -; CHECK-NEXT: ; implicit-def: $vgpr1 -; CHECK-NEXT: s_xor_b64 exec, exec, s[34:35] -; CHECK-NEXT: s_cbranch_execnz .LBB0_1 -; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: s_endpgm -; CHECK: .amdhsa_kernarg_size 0 -; CHECK-NEXT: .amdhsa_user_sgpr_count 6 -; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 -; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 -; CHECK-NEXT: .amdhsa_user_sgpr_queue_ptr 0 -; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 -; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0 -; CHECK-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1 -; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0 -; CHECK-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1 -; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 -; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 -; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 -; CHECK-NEXT: .amdhsa_system_sgpr_workgroup_info 0 -; CHECK-NEXT: .amdhsa_system_vgpr_workitem_id 0 bb: %cond = load i1, i1 addrspace(4)* null %tmp = select i1 %cond, void (i8*, i32, i8*)* bitcast (void ()* @wobble to void (i8*, i32, i8*)*), void (i8*, i32, i8*)* bitcast (void ()* @snork to void (i8*, i32, i8*)*) diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll --- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll +++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll @@ -617,21 +617,19 @@ ; GCN-NEXT: s_load_dword s2, s[0:1], 0x44 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GCN-NEXT: v_mov_b32_e32 v0, 0x3ff00000 +; GCN-NEXT: s_mov_b32 s3, 0x3ff00000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s2, 1 -; GCN-NEXT: v_mov_b32_e32 v1, s7 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc -; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: s_cselect_b32 s7, s3, s7 +; GCN-NEXT: s_cselect_b32 s6, 0, s6 ; GCN-NEXT: s_cmp_eq_u32 s2, 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 0, vcc -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: s_cselect_b32 s2, s3, s5 +; GCN-NEXT: s_cselect_b32 s3, 0, s4 ; GCN-NEXT: v_mov_b32_e32 v5, s1 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; GCN-NEXT: v_mov_b32_e32 v0, s3 +; GCN-NEXT: v_mov_b32_e32 v1, s2 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s7 ; GCN-NEXT: v_mov_b32_e32 v4, s0 ; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GCN-NEXT: s_endpgm @@ -648,51 +646,46 @@ ; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x84 ; GCN-NEXT: s_load_dwordx2 s[10:11], s[0:1], 0x24 ; GCN-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x64 -; GCN-NEXT: v_mov_b32_e32 v4, 0x3ff00000 +; GCN-NEXT: s_mov_b32 s13, 0x3ff00000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s12, 4 -; GCN-NEXT: v_mov_b32_e32 v0, s9 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v9, v0, v4, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: s_cselect_b32 s9, s13, s9 +; GCN-NEXT: s_cselect_b32 s8, 0, s8 ; GCN-NEXT: s_cmp_eq_u32 s12, 1 -; GCN-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s3 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: s_cselect_b32 s3, s13, s3 +; GCN-NEXT: s_cselect_b32 s2, 0, s2 ; GCN-NEXT: s_cmp_eq_u32 s12, 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s1 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s8 +; GCN-NEXT: v_mov_b32_e32 v5, s9 +; GCN-NEXT: s_cselect_b32 s8, s13, s1 +; GCN-NEXT: s_cselect_b32 s9, 0, s0 ; GCN-NEXT: s_cmp_eq_u32 s12, 3 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc -; GCN-NEXT: v_mov_b32_e32 v5, s7 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc -; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: s_cselect_b32 s0, s13, s7 +; GCN-NEXT: s_cselect_b32 s1, 0, s6 ; GCN-NEXT: s_cmp_eq_u32 s12, 2 -; GCN-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: s_cselect_b32 s5, s13, s5 +; GCN-NEXT: s_cselect_b32 s4, 0, s4 +; GCN-NEXT: v_mov_b32_e32 v3, s0 ; GCN-NEXT: s_add_u32 s0, s10, 16 -; GCN-NEXT: v_mov_b32_e32 v5, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s1 ; GCN-NEXT: s_addc_u32 s1, s11, 0 -; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc -; GCN-NEXT: v_mov_b32_e32 v4, s4 -; GCN-NEXT: v_mov_b32_e32 v11, s1 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GCN-NEXT: v_mov_b32_e32 v10, s0 -; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7] +; GCN-NEXT: v_mov_b32_e32 v7, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: flat_store_dwordx4 v[6:7], v[0:3] +; GCN-NEXT: v_mov_b32_e32 v6, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s9 +; GCN-NEXT: v_mov_b32_e32 v1, s8 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: v_mov_b32_e32 v7, s11 ; GCN-NEXT: s_add_u32 s0, s10, 32 -; GCN-NEXT: v_mov_b32_e32 v4, s10 -; GCN-NEXT: v_mov_b32_e32 v5, s11 -; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; GCN-NEXT: flat_store_dwordx4 v[6:7], v[0:3] ; GCN-NEXT: s_addc_u32 s1, s11, 0 ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 -; GCN-NEXT: flat_store_dwordx2 v[0:1], v[8:9] +; GCN-NEXT: flat_store_dwordx2 v[0:1], v[4:5] ; GCN-NEXT: s_endpgm entry: %v = insertelement <5 x double> %vec, double 1.000000e+00, i32 %sel diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll --- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll +++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll @@ -1628,25 +1628,23 @@ ; VI-LABEL: dynamic_insertelement_v2f64: ; VI: ; %bb.0: ; VI-NEXT: s_load_dword s8, s[4:5], 0x60 -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x30 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40200000 -; VI-NEXT: s_mov_b32 s7, 0x1100f000 +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x30 +; VI-NEXT: s_mov_b32 s9, 0x40200000 +; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_cmp_eq_u32 s8, 1 -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_cselect_b32 s7, s9, s7 +; VI-NEXT: s_cselect_b32 s6, 0, s6 ; VI-NEXT: s_cmp_eq_u32 s8, 0 -; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc -; VI-NEXT: v_mov_b32_e32 v0, s1 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: s_mov_b32 s6, -1 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc -; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; VI-NEXT: s_cselect_b32 s5, s9, s5 +; VI-NEXT: s_cselect_b32 s4, 0, s4 +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_mov_b32_e32 v2, s6 +; VI-NEXT: v_mov_b32_e32 v3, s7 +; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: s_endpgm %vecins = insertelement <2 x double> %a, double 8.0, i32 %b store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 @@ -1679,24 +1677,22 @@ ; ; VI-LABEL: dynamic_insertelement_v2i64: ; VI: ; %bb.0: -; VI-NEXT: s_load_dword s10, s[4:5], 0x20 +; VI-NEXT: s_load_dword s8, s[4:5], 0x20 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; VI-NEXT: s_mov_b32 s7, 0x1100f000 ; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_cmp_eq_u32 s10, 1 -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: s_cselect_b64 s[8:9], -1, 0 -; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[8:9] -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: s_cmp_eq_u32 s10, 0 -; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[8:9] -; VI-NEXT: v_mov_b32_e32 v0, s1 -; VI-NEXT: s_cselect_b64 s[2:3], -1, 0 -; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[2:3] +; VI-NEXT: s_cmp_eq_u32 s8, 1 +; VI-NEXT: s_cselect_b32 s3, 0, s3 +; VI-NEXT: s_cselect_b32 s2, 5, s2 +; VI-NEXT: s_cmp_eq_u32 s8, 0 +; VI-NEXT: s_cselect_b32 s1, 0, s1 +; VI-NEXT: s_cselect_b32 s0, 5, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[2:3] +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s3 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; VI-NEXT: s_endpgm %vecins = insertelement <2 x i64> %a, i64 5, i32 %b @@ -1738,32 +1734,29 @@ ; ; VI-LABEL: dynamic_insertelement_v3i64: ; VI: ; %bb.0: -; VI-NEXT: s_load_dword s12, s[4:5], 0x40 +; VI-NEXT: s_load_dword s6, s[4:5], 0x40 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x30 ; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_cmp_eq_u32 s12, 1 -; VI-NEXT: s_cselect_b64 s[6:7], -1, 0 -; VI-NEXT: v_mov_b32_e32 v0, s11 -; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[6:7] -; VI-NEXT: v_mov_b32_e32 v0, s10 -; VI-NEXT: s_cmp_eq_u32 s12, 0 -; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[6:7] -; VI-NEXT: v_mov_b32_e32 v0, s9 -; VI-NEXT: s_cselect_b64 s[6:7], -1, 0 -; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[6:7] -; VI-NEXT: v_mov_b32_e32 v0, s8 -; VI-NEXT: s_cmp_eq_u32 s12, 2 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[6:7] -; VI-NEXT: v_mov_b32_e32 v4, s5 -; VI-NEXT: s_cselect_b64 s[6:7], -1, 0 -; VI-NEXT: v_cndmask_b32_e64 v5, v4, 0, s[6:7] -; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: s_cmp_eq_u32 s6, 1 ; VI-NEXT: s_mov_b32 s2, -1 -; VI-NEXT: v_cndmask_b32_e64 v4, v4, 5, s[6:7] -; VI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16 +; VI-NEXT: s_cselect_b32 s7, 0, s11 +; VI-NEXT: s_cselect_b32 s10, 5, s10 +; VI-NEXT: s_cmp_eq_u32 s6, 0 +; VI-NEXT: s_cselect_b32 s9, 0, s9 +; VI-NEXT: s_cselect_b32 s8, 5, s8 +; VI-NEXT: s_cmp_eq_u32 s6, 2 +; VI-NEXT: s_cselect_b32 s5, 0, s5 +; VI-NEXT: s_cselect_b32 s4, 5, s4 +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:16 +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_mov_b32_e32 v2, s10 +; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: s_endpgm %vecins = insertelement <3 x i64> %a, i64 5, i32 %b @@ -1813,36 +1806,33 @@ ; VI: ; %bb.0: ; VI-NEXT: s_load_dword s6, s[4:5], 0x40 ; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 -; VI-NEXT: v_mov_b32_e32 v4, 0x40200000 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; VI-NEXT: s_mov_b32 s4, 0x40200000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_cmp_eq_u32 s6, 1 -; VI-NEXT: v_mov_b32_e32 v0, s11 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc -; VI-NEXT: v_mov_b32_e32 v0, s10 +; VI-NEXT: s_cselect_b32 s5, s4, s11 +; VI-NEXT: s_cselect_b32 s7, 0, s10 ; VI-NEXT: s_cmp_eq_u32 s6, 0 -; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc -; VI-NEXT: v_mov_b32_e32 v0, s9 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc -; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: s_cselect_b32 s9, s4, s9 +; VI-NEXT: s_cselect_b32 s8, 0, s8 ; VI-NEXT: s_cmp_eq_u32 s6, 3 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc -; VI-NEXT: v_mov_b32_e32 v5, s15 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc -; VI-NEXT: v_mov_b32_e32 v5, s14 +; VI-NEXT: s_cselect_b32 s10, s4, s15 +; VI-NEXT: s_cselect_b32 s11, 0, s14 ; VI-NEXT: s_cmp_eq_u32 s6, 2 -; VI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc -; VI-NEXT: v_mov_b32_e32 v5, s13 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc -; VI-NEXT: v_mov_b32_e32 v4, s12 +; VI-NEXT: s_cselect_b32 s4, s4, s13 +; VI-NEXT: s_cselect_b32 s6, 0, s12 ; VI-NEXT: s_mov_b32 s2, -1 -; VI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 +; VI-NEXT: v_mov_b32_e32 v0, s6 +; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_mov_b32_e32 v2, s11 +; VI-NEXT: v_mov_b32_e32 v3, s10 +; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_mov_b32_e32 v2, s7 +; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: s_endpgm %vecins = insertelement <4 x double> %a, double 8.0, i32 %b diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll @@ -248,13 +248,12 @@ ; GFX9-NEXT: s_addc_u32 s5, 0, s5 ; GFX9-NEXT: s_add_i32 s1, s8, s7 ; GFX9-NEXT: s_add_i32 s1, s1, s6 +; GFX9-NEXT: s_mul_i32 s0, s0, s2 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX9-NEXT: s_mul_i32 s2, s0, s2 -; GFX9-NEXT: v_mov_b32_e32 v0, s1 -; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GFX9-NEXT: s_cselect_b32 s1, 0, s1 +; GFX9-NEXT: s_cselect_b32 s0, 0, s0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: s_endpgm ; @@ -280,9 +279,10 @@ ; GFX10-NEXT: s_mul_i32 s0, s0, s2 ; GFX10-NEXT: s_add_i32 s1, s1, s6 ; GFX10-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX10-NEXT: s_cselect_b32 s2, -1, 0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, s2 -; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, s2 +; GFX10-NEXT: s_cselect_b32 s0, 0, s0 +; GFX10-NEXT: s_cselect_b32 s1, 0, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: s_endpgm bb: @@ -347,44 +347,38 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mul_i32 s7, s0, s3 ; GFX9-NEXT: s_mul_hi_u32 s8, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s6, s0, s3 +; GFX9-NEXT: s_mul_hi_u32 s5, s0, s3 ; GFX9-NEXT: s_add_u32 s9, s8, s7 -; GFX9-NEXT: s_mul_i32 s5, s1, s2 -; GFX9-NEXT: s_addc_u32 s6, 0, s6 +; GFX9-NEXT: s_mul_i32 s6, s1, s2 +; GFX9-NEXT: s_addc_u32 s5, 0, s5 ; GFX9-NEXT: s_mul_hi_u32 s4, s1, s2 -; GFX9-NEXT: s_add_u32 s9, s9, s5 +; GFX9-NEXT: s_add_u32 s9, s9, s6 ; GFX9-NEXT: s_mul_hi_i32 s10, s1, s3 -; GFX9-NEXT: s_addc_u32 s4, s6, s4 -; GFX9-NEXT: s_addc_u32 s6, s10, 0 +; GFX9-NEXT: s_addc_u32 s4, s5, s4 +; GFX9-NEXT: s_addc_u32 s5, s10, 0 ; GFX9-NEXT: s_mul_i32 s9, s1, s3 ; GFX9-NEXT: s_add_u32 s4, s4, s9 -; GFX9-NEXT: s_addc_u32 s6, 0, s6 +; GFX9-NEXT: s_addc_u32 s5, 0, s5 ; GFX9-NEXT: s_sub_u32 s9, s4, s2 -; GFX9-NEXT: s_subb_u32 s10, s6, 0 +; GFX9-NEXT: s_subb_u32 s10, s5, 0 ; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: v_mov_b32_e32 v0, s6 -; GFX9-NEXT: v_mov_b32_e32 v1, s10 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: v_mov_b32_e32 v2, s9 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v2 -; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v0, vcc +; GFX9-NEXT: s_cselect_b32 s4, s9, s4 +; GFX9-NEXT: s_cselect_b32 s1, s10, s5 +; GFX9-NEXT: s_sub_u32 s9, s4, s0 +; GFX9-NEXT: s_subb_u32 s5, s1, 0 ; GFX9-NEXT: s_cmp_lt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 +; GFX9-NEXT: s_cselect_b32 s5, s5, s1 +; GFX9-NEXT: s_cselect_b32 s4, s9, s4 ; GFX9-NEXT: s_add_i32 s1, s8, s7 -; GFX9-NEXT: s_add_i32 s1, s1, s5 -; GFX9-NEXT: s_ashr_i32 s4, s1, 31 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc -; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_add_i32 s1, s1, s6 +; GFX9-NEXT: s_ashr_i32 s6, s1, 31 +; GFX9-NEXT: s_mov_b32 s7, s6 ; GFX9-NEXT: s_mul_i32 s0, s0, s2 -; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], s[6:7] +; GFX9-NEXT: s_cselect_b32 s1, 0, s1 +; GFX9-NEXT: s_cselect_b32 s0, 0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: s_endpgm ; @@ -394,40 +388,38 @@ ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_mul_i32 s7, s0, s3 ; GFX10-NEXT: s_mul_hi_u32 s8, s0, s2 -; GFX10-NEXT: s_mul_hi_u32 s6, s0, s3 -; GFX10-NEXT: s_mul_i32 s5, s1, s2 +; GFX10-NEXT: s_mul_hi_u32 s5, s0, s3 +; GFX10-NEXT: s_mul_i32 s6, s1, s2 ; GFX10-NEXT: s_add_u32 s11, s8, s7 ; GFX10-NEXT: s_mul_hi_u32 s4, s1, s2 -; GFX10-NEXT: s_addc_u32 s6, 0, s6 +; GFX10-NEXT: s_addc_u32 s5, 0, s5 ; GFX10-NEXT: s_mul_hi_i32 s9, s1, s3 -; GFX10-NEXT: s_add_u32 s11, s11, s5 +; GFX10-NEXT: s_add_u32 s11, s11, s6 ; GFX10-NEXT: s_mul_i32 s10, s1, s3 -; GFX10-NEXT: s_addc_u32 s4, s6, s4 -; GFX10-NEXT: s_addc_u32 s6, s9, 0 +; GFX10-NEXT: s_addc_u32 s4, s5, s4 +; GFX10-NEXT: s_addc_u32 s5, s9, 0 ; GFX10-NEXT: s_add_u32 s4, s4, s10 -; GFX10-NEXT: s_addc_u32 s6, 0, s6 +; GFX10-NEXT: s_addc_u32 s5, 0, s5 ; GFX10-NEXT: s_sub_u32 s9, s4, s2 -; GFX10-NEXT: s_subb_u32 s10, s6, 0 -; GFX10-NEXT: v_mov_b32_e32 v1, s9 +; GFX10-NEXT: s_subb_u32 s10, s5, 0 ; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: v_mov_b32_e32 v0, s10 -; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 +; GFX10-NEXT: s_cselect_b32 s1, s9, s4 +; GFX10-NEXT: s_cselect_b32 s4, s10, s5 +; GFX10-NEXT: s_sub_u32 s9, s1, s0 +; GFX10-NEXT: s_subb_u32 s5, s4, 0 ; GFX10-NEXT: s_cmp_lt_i32 s3, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v2, s4, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo -; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, v2, s0 -; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v0, vcc_lo -; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX10-NEXT: s_add_i32 s1, s8, s7 ; GFX10-NEXT: s_mul_i32 s0, s0, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s5 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo -; GFX10-NEXT: s_ashr_i32 s4, s1, 31 -; GFX10-NEXT: s_mov_b32 s5, s4 -; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1] -; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, vcc_lo +; GFX10-NEXT: s_cselect_b32 s5, s5, s4 +; GFX10-NEXT: s_cselect_b32 s4, s9, s1 +; GFX10-NEXT: s_add_i32 s1, s8, s7 +; GFX10-NEXT: s_add_i32 s1, s1, s6 +; GFX10-NEXT: s_ashr_i32 s6, s1, 31 +; GFX10-NEXT: s_mov_b32 s7, s6 +; GFX10-NEXT: s_cmp_lg_u64 s[4:5], s[6:7] +; GFX10-NEXT: s_cselect_b32 s0, 0, s0 +; GFX10-NEXT: s_cselect_b32 s1, 0, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: s_endpgm bb: diff --git a/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll b/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll --- a/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll +++ b/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll @@ -9,8 +9,7 @@ ; GCN: s_load_dwordx2 ; GCN: s_cmp_eq_u32 -; GCN: v_cndmask_b32 -; GCN: v_cndmask_b32 +; GCN-COUNT-2: s_cselect_b32 ; GCN-NOT: load_dword ; GCN: flat_load_dwordx2 @@ -35,8 +34,7 @@ ; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} -; GCN: v_cndmask_b32 -; GCN: v_cndmask_b32 +; GCN-COUNT-2: s_cselect_b32 ; GCN: flat_store_dwordx2 define amdgpu_kernel void @select_ptr_crash_i64_global(i32 %tmp, [8 x i32], i64 addrspace(1)* %ptr0, [8 x i32], i64 addrspace(1)* %ptr1, [8 x i32], i64 addrspace(1)* %ptr2) { %tmp2 = icmp eq i32 %tmp, 0 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll --- a/llvm/test/CodeGen/AMDGPU/sdiv.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll @@ -92,15 +92,15 @@ ; TONGA-NEXT: v_mul_lo_u32 v4, v3, v1 ; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v3 ; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v4, v0 -; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 -; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] ; TONGA-NEXT: v_subrev_u32_e32 v4, vcc, v1, v0 -; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] +; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 +; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; TONGA-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; TONGA-NEXT: v_add_u32_e32 v4, vcc, 1, v3 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; TONGA-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v2 -; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v2 +; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v2, v0 ; TONGA-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; TONGA-NEXT: s_endpgm ; @@ -137,8 +137,8 @@ ; GFX9-NEXT: v_mul_lo_u32 v4, v3, v1 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v3 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4 -; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; GFX9-NEXT: v_sub_u32_e32 v4, v0, v1 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 1, v3 @@ -519,10 +519,10 @@ ; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 -; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v0, v2 -; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3] +; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; TONGA-NEXT: v_sub_u32_e32 v7, vcc, v1, v3 +; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3] ; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v4 ; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] @@ -591,11 +591,11 @@ ; GFX9-NEXT: v_add_u32_e32 v11, 1, v7 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v8 ; GFX9-NEXT: v_sub_u32_e32 v1, v1, v9 -; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_sub_u32_e32 v8, v0, v2 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc -; GFX9-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v3 ; GFX9-NEXT: v_sub_u32_e32 v9, v1, v3 +; GFX9-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[0:1] ; GFX9-NEXT: v_add_u32_e32 v8, 1, v6 @@ -1047,10 +1047,10 @@ ; TONGA-NEXT: v_xor_b32_e32 v6, v9, v14 ; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v5 ; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4 -; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v7 -; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1] -; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v3, v7 -; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] +; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v3, v7 +; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7 +; TONGA-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7 ; TONGA-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc @@ -2066,10 +2066,10 @@ ; TONGA-NEXT: v_mul_lo_u32 v1, v3, v2 ; TONGA-NEXT: v_add_u32_e32 v4, vcc, 1, v3 ; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v1, v5 -; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v2 -; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] -; TONGA-NEXT: v_subrev_u32_e32 v4, vcc, v2, v1 -; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] +; TONGA-NEXT: v_subrev_u32_e32 v5, vcc, v2, v1 +; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 +; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; TONGA-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; TONGA-NEXT: v_add_u32_e32 v4, vcc, 1, v3 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; TONGA-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc @@ -2114,10 +2114,10 @@ ; GFX9-NEXT: v_mul_lo_u32 v4, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v1, 1, v3 ; GFX9-NEXT: v_sub_u32_e32 v4, v5, v4 +; GFX9-NEXT: v_sub_u32_e32 v5, v4, v2 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX9-NEXT: v_sub_u32_e32 v3, v4, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc diff --git a/llvm/test/CodeGen/AMDGPU/select-vectors.ll b/llvm/test/CodeGen/AMDGPU/select-vectors.ll --- a/llvm/test/CodeGen/AMDGPU/select-vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/select-vectors.ll @@ -158,8 +158,8 @@ ; vector select with SGPR inputs. ; GCN-LABEL: {{^}}s_select_v2i32: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-2: v_cndmask_b32_e32 +; GFX89-COUNT-2: s_cselect_b32 ; GCN: buffer_store_dwordx2 define amdgpu_kernel void @s_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 @@ -169,10 +169,8 @@ } ; GCN-LABEL: {{^}}s_select_v4i32: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-4: v_cndmask_b32_e32 +; GFX89-COUNT-4: s_cselect_b32 ; GCN: buffer_store_dwordx4 define amdgpu_kernel void @s_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 @@ -200,14 +198,8 @@ } ; GCN-LABEL: {{^}}select_v8i32: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-8: v_cndmask_b32_e32 +; GFX89-COUNT-8: s_cselect_b32 define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b @@ -218,13 +210,15 @@ ; GCN-LABEL: {{^}}s_select_v2f32: ; GCN-DAG: s_load_dwordx4 s[[[ALO:[0-9]+]]:[[BHI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} -; GCN-DAG: v_cndmask_b32_e32 -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} -; GCN-DAG: v_cndmask_b32_e32 +; SI-DAG: v_cndmask_b32_e32 +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; SI-DAG: v_cndmask_b32_e32 +; GFX89-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s[[BHI]] +; GFX89-DAG: s_cselect_b32 s{{[0-9]+}}, s[[ALO]], s{{[0-9]+}} ; GCN: buffer_store_dwordx2 define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 @@ -236,9 +230,8 @@ ; GCN-LABEL: {{^}}s_select_v3f32: ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-3: v_cndmask_b32_e32 +; GFX89-COUNT-3: s_cselect_b32 ; GCN: buffer_store_dwordx define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 { @@ -252,10 +245,8 @@ ; GCN: s_load_dwordx8 ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-4: v_cndmask_b32_e32 +; GFX89-COUNT-4: s_cselect_b32 ; GCN: buffer_store_dwordx4 define amdgpu_kernel void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) #0 { @@ -286,11 +277,8 @@ ; GCN-LABEL: {{^}}s_select_v5f32: ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-5: v_cndmask_b32_e32 +; GFX89-COUNT-5: s_cselect_b32 ; GCN: buffer_store_dwordx define amdgpu_kernel void @s_select_v5f32(<5 x float> addrspace(1)* %out, <5 x float> %a, <5 x float> %b, i32 %c) #0 { @@ -317,10 +305,8 @@ } ; GCN-LABEL: {{^}}select_v2f64: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-4: v_cndmask_b32_e32 +; GFX89-COUNT-4: s_cselect_b32 define amdgpu_kernel void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x double> %a, <2 x double> %b @@ -329,14 +315,8 @@ } ; GCN-LABEL: {{^}}select_v4f64: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-8: v_cndmask_b32_e32 +; GFX89-COUNT-8: s_cselect_b32 define amdgpu_kernel void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x double> %a, <4 x double> %b @@ -345,22 +325,8 @@ } ; GCN-LABEL: {{^}}select_v8f64: -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e32 +; SI-COUNT-16: v_cndmask_b32_e32 +; GFX89-COUNT-16: s_cselect_b32 define amdgpu_kernel void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) #0 { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <8 x double> %a, <8 x double> %b diff --git a/llvm/test/CodeGen/AMDGPU/select64.ll b/llvm/test/CodeGen/AMDGPU/select64.ll --- a/llvm/test/CodeGen/AMDGPU/select64.ll +++ b/llvm/test/CodeGen/AMDGPU/select64.ll @@ -5,8 +5,8 @@ ; i64 select should be split into two i32 selects, and we shouldn't need ; to use a shfit to extract the hi dword of the input. ; GCN-NOT: s_lshr_b64 -; GCN: v_cndmask -; GCN: v_cndmask +; SI-COUNT-2: v_cndmask +; VI-COUNT-2: s_cselect define amdgpu_kernel void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) { entry: %0 = icmp ugt i32 %cond, 5 @@ -57,8 +57,10 @@ } ; GCN-LABEL: {{^}}v_select_i64_split_imm: -; GCN-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} -; GCN-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}} +; SI-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} +; SI-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}} +; VI-DAG: s_cselect_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0 +; VI-DAG: s_cselect_b32 {{s[0-9]+}}, {{s[0-9]+}}, 63 ; GCN: s_endpgm define amdgpu_kernel void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %cmp = icmp ugt i32 %cond, 5 diff --git a/llvm/test/CodeGen/AMDGPU/selectcc.ll b/llvm/test/CodeGen/AMDGPU/selectcc.ll --- a/llvm/test/CodeGen/AMDGPU/selectcc.ll +++ b/llvm/test/CodeGen/AMDGPU/selectcc.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI -check-prefix=FUNC %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI -check-prefix=FUNC %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI -check-prefix=FUNC %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}selectcc_i64: ; EG: XOR_INT @@ -9,9 +9,9 @@ ; EG: CNDE_INT ; EG: CNDE_INT ; SI: v_cmp_eq_u64 +; SI-COUNT-2: v_cndmask ; VI: s_cmp_eq_u64 -; GCN: v_cndmask -; GCN: v_cndmask +; VI-COUNT-2: s_cselect define amdgpu_kernel void @selectcc_i64(i64 addrspace(1) * %out, i64 %lhs, i64 %rhs, i64 %true, i64 %false) { entry: %0 = icmp eq i64 %lhs, %rhs diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll --- a/llvm/test/CodeGen/AMDGPU/udiv.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv.ll @@ -68,10 +68,10 @@ ; VI-NEXT: v_mul_lo_u32 v3, v2, v1 ; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v2 ; VI-NEXT: v_subrev_u32_e32 v0, vcc, v3, v0 -; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 -; VI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v3, vcc, v1, v0 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v2 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc @@ -100,10 +100,10 @@ ; GCN-NEXT: v_mul_lo_u32 v5, v4, v1 ; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4 ; GCN-NEXT: v_subrev_u32_e32 v0, vcc, v5, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1] ; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v1, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 +; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc @@ -211,60 +211,60 @@ ; ; VI-LABEL: s_udiv_i32: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c -; VI-NEXT: s_mov_b32 s7, 0xf000 -; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c +; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cvt_f32_u32_e32 v0, s3 -; VI-NEXT: s_sub_i32 s4, 0, s3 +; VI-NEXT: v_cvt_f32_u32_e32 v0, s5 +; VI-NEXT: s_sub_i32 s2, 0, s5 ; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 -; VI-NEXT: v_mul_lo_u32 v1, s4, v0 -; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; VI-NEXT: v_mul_lo_u32 v1, s2, v0 +; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: v_mul_hi_u32 v1, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0 -; VI-NEXT: v_mul_hi_u32 v0, s2, v0 -; VI-NEXT: v_mul_lo_u32 v1, v0, s3 +; VI-NEXT: v_mul_hi_u32 v0, s4, v0 +; VI-NEXT: v_mul_lo_u32 v1, v0, s5 ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0 -; VI-NEXT: v_sub_u32_e32 v1, vcc, s2, v1 -; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; VI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; VI-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1 -; VI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] +; VI-NEXT: v_sub_u32_e32 v1, vcc, s4, v1 +; VI-NEXT: v_subrev_u32_e32 v3, vcc, s5, v1 +; VI-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0 -; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 +; VI-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: s_endpgm ; ; GCN-LABEL: s_udiv_i32: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x8 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3 -; GCN-NEXT: s_sub_i32 s0, 0, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s1 +; GCN-NEXT: s_sub_i32 s2, 0, s1 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v1, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 -; GCN-NEXT: v_mul_lo_u32 v1, v0, s3 +; GCN-NEXT: v_mul_hi_u32 v0, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s1 ; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0 -; GCN-NEXT: v_sub_u32_e32 v1, vcc, s2, v1 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GCN-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] +; GCN-NEXT: v_sub_u32_e32 v1, vcc, s0, v1 +; GCN-NEXT: v_subrev_u32_e32 v3, vcc, s1, v1 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s1, v1 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s1, v1 ; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_mov_b32_e32 v1, s3 ; GCN-NEXT: flat_store_dword v[0:1], v2 ; GCN-NEXT: s_endpgm ; @@ -429,10 +429,10 @@ ; VI-NEXT: v_add_u32_e32 v9, vcc, 1, v5 ; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 -; VI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v6, vcc, v2, v0 -; VI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3] +; VI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v7, vcc, v3, v1 +; VI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3] ; VI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v4 ; VI-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] @@ -481,10 +481,10 @@ ; GCN-NEXT: v_subrev_u32_e32 v1, vcc, v10, v1 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1] ; GCN-NEXT: v_subrev_u32_e32 v8, vcc, v2, v0 -; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[2:3] +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1] ; GCN-NEXT: v_subrev_u32_e32 v9, vcc, v3, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1] ; GCN-NEXT: v_add_u32_e32 v8, vcc, 1, v6 ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[2:3] @@ -528,20 +528,20 @@ ; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5 ; GFX1030-NEXT: v_sub_nc_u32_e32 v1, v1, v8 ; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6 +; GFX1030-NEXT: v_sub_nc_u32_e32 v9, v0, v2 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 -; GFX1030-NEXT: v_sub_nc_u32_e32 v9, v1, v3 ; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v1, v3 ; GFX1030-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo -; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v0, v2 +; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v1, v3 +; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo ; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v8, s0 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo -; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5 -; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6 +; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v5 +; GFX1030-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo +; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v6 +; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo +; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo ; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] ; GFX1030-NEXT: s_endpgm ; @@ -766,14 +766,14 @@ ; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1 ; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2 ; VI-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3 -; VI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v12, vcc, v0, v4 -; VI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3] +; VI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v13, vcc, v1, v5 -; VI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5] +; VI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3] ; VI-NEXT: v_subrev_u32_e32 v14, vcc, v2, v6 -; VI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7] +; VI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5] ; VI-NEXT: v_subrev_u32_e32 v15, vcc, v3, v7 +; VI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7] ; VI-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1] ; VI-NEXT: v_add_u32_e32 v12, vcc, 1, v8 ; VI-NEXT: v_cndmask_b32_e64 v5, v5, v13, s[2:3] @@ -862,30 +862,30 @@ ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v5, v1 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3 +; GCN-NEXT: v_subrev_u32_e32 v18, vcc, v0, v4 ; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v15, s[0:1] -; GCN-NEXT: v_subrev_u32_e32 v15, vcc, v0, v4 +; GCN-NEXT: v_subrev_u32_e32 v15, vcc, v1, v5 ; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[2:3] -; GCN-NEXT: v_subrev_u32_e32 v17, vcc, v1, v5 +; GCN-NEXT: v_subrev_u32_e32 v17, vcc, v2, v6 ; GCN-NEXT: v_cndmask_b32_e64 v12, v12, v14, s[4:5] -; GCN-NEXT: v_subrev_u32_e32 v14, vcc, v2, v6 +; GCN-NEXT: v_subrev_u32_e32 v14, vcc, v3, v7 ; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[6:7] -; GCN-NEXT: v_subrev_u32_e32 v16, vcc, v3, v7 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v15, s[0:1] -; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10 -; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3] -; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v14, s[4:5] -; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12 -; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[6:7] -; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v18, s[0:1] +; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v10 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v15, s[2:3] +; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v11 +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v17, s[4:5] +; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v12 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v14, s[6:7] +; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v13 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v15, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v16, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v17, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v15, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v12, v14, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v12, v17, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v13, v14, vcc ; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3] ; GCN-NEXT: s_endpgm ; @@ -901,81 +901,81 @@ ; GFX1030-NEXT: s_waitcnt vmcnt(1) ; GFX1030-NEXT: v_cvt_f32_u32_e32 v9, v0 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v10, v1 -; GFX1030-NEXT: v_cvt_f32_u32_e32 v11, v2 ; GFX1030-NEXT: v_cvt_f32_u32_e32 v12, v3 +; GFX1030-NEXT: v_cvt_f32_u32_e32 v11, v2 ; GFX1030-NEXT: v_sub_nc_u32_e32 v13, 0, v0 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v9, v9 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v10, v10 -; GFX1030-NEXT: v_rcp_iflag_f32_e32 v11, v11 ; GFX1030-NEXT: v_rcp_iflag_f32_e32 v12, v12 +; GFX1030-NEXT: v_rcp_iflag_f32_e32 v11, v11 ; GFX1030-NEXT: v_sub_nc_u32_e32 v14, 0, v1 -; GFX1030-NEXT: v_sub_nc_u32_e32 v15, 0, v2 ; GFX1030-NEXT: v_sub_nc_u32_e32 v16, 0, v3 +; GFX1030-NEXT: v_sub_nc_u32_e32 v15, 0, v2 ; GFX1030-NEXT: v_mul_f32_e32 v9, s0, v9 ; GFX1030-NEXT: v_mul_f32_e32 v10, s0, v10 -; GFX1030-NEXT: v_mul_f32_e32 v11, s0, v11 ; GFX1030-NEXT: v_mul_f32_e32 v12, s0, v12 +; GFX1030-NEXT: v_mul_f32_e32 v11, s0, v11 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v9, v9 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v10, v10 -; GFX1030-NEXT: v_cvt_u32_f32_e32 v11, v11 ; GFX1030-NEXT: v_cvt_u32_f32_e32 v12, v12 +; GFX1030-NEXT: v_cvt_u32_f32_e32 v11, v11 ; GFX1030-NEXT: v_mul_lo_u32 v13, v13, v9 ; GFX1030-NEXT: v_mul_lo_u32 v14, v14, v10 -; GFX1030-NEXT: v_mul_lo_u32 v15, v15, v11 ; GFX1030-NEXT: v_mul_lo_u32 v16, v16, v12 +; GFX1030-NEXT: v_mul_lo_u32 v15, v15, v11 ; GFX1030-NEXT: v_mul_hi_u32 v13, v9, v13 ; GFX1030-NEXT: v_mul_hi_u32 v14, v10, v14 -; GFX1030-NEXT: v_mul_hi_u32 v15, v11, v15 ; GFX1030-NEXT: v_mul_hi_u32 v16, v12, v16 +; GFX1030-NEXT: v_mul_hi_u32 v15, v11, v15 ; GFX1030-NEXT: v_add_nc_u32_e32 v9, v9, v13 ; GFX1030-NEXT: v_add_nc_u32_e32 v10, v10, v14 -; GFX1030-NEXT: v_add_nc_u32_e32 v11, v11, v15 ; GFX1030-NEXT: v_add_nc_u32_e32 v12, v12, v16 +; GFX1030-NEXT: v_add_nc_u32_e32 v11, v11, v15 ; GFX1030-NEXT: s_waitcnt vmcnt(0) ; GFX1030-NEXT: v_mul_hi_u32 v9, v4, v9 ; GFX1030-NEXT: v_mul_hi_u32 v10, v5, v10 -; GFX1030-NEXT: v_mul_hi_u32 v11, v6, v11 ; GFX1030-NEXT: v_mul_hi_u32 v12, v7, v12 +; GFX1030-NEXT: v_mul_hi_u32 v11, v6, v11 ; GFX1030-NEXT: v_mul_lo_u32 v13, v9, v0 ; GFX1030-NEXT: v_mul_lo_u32 v14, v10, v1 -; GFX1030-NEXT: v_mul_lo_u32 v15, v11, v2 ; GFX1030-NEXT: v_mul_lo_u32 v16, v12, v3 +; GFX1030-NEXT: v_mul_lo_u32 v15, v11, v2 ; GFX1030-NEXT: v_add_nc_u32_e32 v17, 1, v9 ; GFX1030-NEXT: v_add_nc_u32_e32 v18, 1, v10 ; GFX1030-NEXT: v_add_nc_u32_e32 v19, 1, v11 ; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v13 ; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v5, v14 -; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v6, v15 ; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v7, v16 ; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12 -; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0 +; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v6, v15 ; GFX1030-NEXT: v_sub_nc_u32_e32 v14, v4, v0 -; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v5, v1 +; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0 ; GFX1030-NEXT: v_sub_nc_u32_e32 v15, v5, v1 -; GFX1030-NEXT: v_cmp_ge_u32_e64 s1, v6, v2 +; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v5, v1 +; GFX1030-NEXT: v_cmp_ge_u32_e64 s2, v7, v3 +; GFX1030-NEXT: v_sub_nc_u32_e32 v16, v6, v2 ; GFX1030-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo ; GFX1030-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo ; GFX1030-NEXT: v_cndmask_b32_e64 v10, v10, v18, s0 -; GFX1030-NEXT: v_sub_nc_u32_e32 v16, v6, v2 -; GFX1030-NEXT: v_cmp_ge_u32_e64 s2, v7, v3 -; GFX1030-NEXT: v_add_nc_u32_e32 v14, 1, v9 +; GFX1030-NEXT: v_cmp_ge_u32_e64 s1, v6, v2 +; GFX1030-NEXT: v_cndmask_b32_e64 v12, v12, v13, s2 +; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v9 ; GFX1030-NEXT: v_cndmask_b32_e64 v5, v5, v15, s0 ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0 ; GFX1030-NEXT: v_cndmask_b32_e64 v11, v11, v19, s1 -; GFX1030-NEXT: v_cndmask_b32_e64 v12, v12, v13, s2 -; GFX1030-NEXT: v_sub_nc_u32_e32 v13, v7, v3 -; GFX1030-NEXT: v_add_nc_u32_e32 v15, 1, v10 +; GFX1030-NEXT: v_sub_nc_u32_e32 v17, v7, v3 +; GFX1030-NEXT: v_add_nc_u32_e32 v14, 1, v10 ; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v16, s1 -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v9, v14, vcc_lo +; GFX1030-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v1 -; GFX1030-NEXT: v_add_nc_u32_e32 v16, 1, v11 -; GFX1030-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2 -; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo +; GFX1030-NEXT: v_add_nc_u32_e32 v15, 1, v11 +; GFX1030-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2 +; GFX1030-NEXT: v_add_nc_u32_e32 v16, 1, v12 +; GFX1030-NEXT: v_cndmask_b32_e32 v1, v10, v14, vcc_lo ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v6, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, v11, v16, vcc_lo +; GFX1030-NEXT: v_cndmask_b32_e32 v2, v11, v15, vcc_lo ; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v7, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc_lo +; GFX1030-NEXT: v_cndmask_b32_e32 v3, v12, v16, vcc_lo ; GFX1030-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] ; GFX1030-NEXT: s_endpgm ; @@ -1910,10 +1910,10 @@ ; VI-NEXT: v_mul_lo_u32 v3, v1, v0 ; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v1 ; VI-NEXT: v_subrev_u32_e32 v2, vcc, v3, v2 -; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v0 -; VI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] ; VI-NEXT: v_subrev_u32_e32 v3, vcc, v0, v2 -; VI-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v1 ; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 ; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc @@ -1965,10 +1965,10 @@ ; GCN-NEXT: v_mul_lo_u32 v5, v4, v3 ; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4 ; GCN-NEXT: v_subrev_u32_e32 v2, vcc, v5, v2 -; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v3 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1] ; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v3, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 +; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 ; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll --- a/llvm/test/CodeGen/AMDGPU/udivrem.ll +++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll @@ -74,38 +74,38 @@ ; ; GFX8-LABEL: test_udivrem: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_load_dword s6, s[0:1], 0x98 -; GFX8-NEXT: s_load_dword s7, s[0:1], 0x74 -; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c +; GFX8-NEXT: s_load_dword s4, s[0:1], 0x98 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x74 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6 -; GFX8-NEXT: s_sub_i32 s2, 0, s6 +; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX8-NEXT: s_sub_i32 s2, 0, s4 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, s2, v0 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x4c ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 -; GFX8-NEXT: v_mul_hi_u32 v2, s7, v0 +; GFX8-NEXT: v_mul_hi_u32 v2, s5, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: v_mul_lo_u32 v3, v2, s6 +; GFX8-NEXT: v_mul_lo_u32 v3, v2, s4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2 -; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3 -; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3 -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] -; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3 -; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] +; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s5, v3 +; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v3 +; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2 -; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3 -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] -; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3 +; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v3 +; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: flat_store_dword v[0:1], v2 -; GFX8-NEXT: v_mov_b32_e32 v0, s4 -; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] -; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm %result0 = udiv i32 %x, %y