diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -20,6 +20,8 @@ TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit") +TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit") // Zbc or Zbkc extension TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -19012,6 +19012,8 @@ case RISCV::BI__builtin_riscv_orc_b_64: case RISCV::BI__builtin_riscv_clz_32: case RISCV::BI__builtin_riscv_clz_64: + case RISCV::BI__builtin_riscv_ctz_32: + case RISCV::BI__builtin_riscv_ctz_64: case RISCV::BI__builtin_riscv_clmul: case RISCV::BI__builtin_riscv_clmulh: case RISCV::BI__builtin_riscv_clmulr: @@ -19062,6 +19064,11 @@ Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType()); return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)}); } + case RISCV::BI__builtin_riscv_ctz_32: + case RISCV::BI__builtin_riscv_ctz_64: { + Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType()); + return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)}); + } // Zbc case RISCV::BI__builtin_riscv_clmul: diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -24,4 +24,16 @@ // int clz_32(int a) { return __builtin_riscv_clz_32(a); +} + +// RV32ZBB-LABEL: @ctz_32( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) +// RV32ZBB-NEXT: ret i32 [[TMP1]] +// +int ctz_32(int a) { + return __builtin_riscv_ctz_32(a); } \ No newline at end of file diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -48,4 +48,16 @@ // long clz_64(long a) { return __builtin_riscv_clz_64(a); +} + +// RV64ZBB-LABEL: @ctz_64( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i64 [[TMP1]] +// +long ctz_64(long a) { + return __builtin_riscv_ctz_64(a); } \ No newline at end of file