diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -52,6 +52,8 @@ createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) { CPU = "generic"; + if (FS.empty()) + FS = "+v8a"; if (TT.isArm64e()) CPU = "apple-a12"; diff --git a/llvm/test/MC/AArch64/arm64-branch-encoding.s b/llvm/test/MC/AArch64/arm64-branch-encoding.s --- a/llvm/test/MC/AArch64/arm64-branch-encoding.s +++ b/llvm/test/MC/AArch64/arm64-branch-encoding.s @@ -137,17 +137,23 @@ ; CHECK: encoding: [0x41,0x00,0xa0,0xd4] dcps2 #3 ; CHECK: encoding: [0x62,0x00,0xa0,0xd4] + dcps3 #4 +; CHECK: encoding: [0x83,0x00,0xa0,0xd4] hlt #5 ; CHECK: encoding: [0xa0,0x00,0x40,0xd4] hvc #6 ; CHECK: encoding: [0xc2,0x00,0x00,0xd4] + smc #7 +; CHECK: encoding: [0xe3,0x00,0x00,0xd4] svc #8 ; CHECK: encoding: [0x01,0x01,0x00,0xd4] ; The immediate defaults to zero for DCPSn dcps1 dcps2 + dcps3 ; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4] ; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4] +; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4] diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s --- a/llvm/test/MC/AArch64/arm64-system-encoding.s +++ b/llvm/test/MC/AArch64/arm64-system-encoding.s @@ -123,6 +123,7 @@ msr TPIDR_EL2, x3 msr TPIDR_EL3, x3 msr TTBR0_EL1, x3 + msr TTBR0_EL2, x3 msr TTBR0_EL3, x3 msr TTBR1_EL1, x3 msr VBAR_EL1, x3 @@ -131,6 +132,7 @@ msr VMPIDR_EL2, x3 msr VPIDR_EL2, x3 msr VTCR_EL2, x3 + msr VTTBR_EL2, x3 msr SPSel, x3 msr S3_2_C11_C6_4, x1 msr S0_0_C0_C0_0, x0 @@ -200,6 +202,7 @@ ; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5] ; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5] ; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5] +; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5] ; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5] ; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5] ; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5] @@ -208,6 +211,7 @@ ; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5] ; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5] ; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5] +; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5] ; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5] ; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5] ; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5] @@ -309,6 +313,7 @@ mrs x3, TPIDR_EL2 mrs x3, TPIDR_EL3 mrs x3, TTBR0_EL1 + mrs x3, TTBR0_EL2 mrs x3, TTBR0_EL3 mrs x3, TTBR1_EL1 mrs x3, VBAR_EL1 @@ -317,6 +322,7 @@ mrs x3, VMPIDR_EL2 mrs x3, VPIDR_EL2 mrs x3, VTCR_EL2 + mrs x3, VTTBR_EL2 mrs x3, MDCCSR_EL0 mrs x3, MDCCINT_EL1 @@ -494,6 +500,7 @@ ; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5] ; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5] ; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5] +; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5] ; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5] ; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5] ; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5] @@ -502,6 +509,7 @@ ; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5] ; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5] ; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5] +; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5] ; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5] ; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5] ; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5] diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8a,+fp-armv8 %s | FileCheck %s .globl _func // Check that the assembler can handle the documented syntax from the ARM ARM. @@ -1694,21 +1694,27 @@ // CHECK: svc #{{65535|0xffff}} // encoding: [0xe1,0xff,0x1f,0xd4] hvc #1 + smc #12000 brk #12 hlt #123 // CHECK: hvc #{{1|0x1}} // encoding: [0x22,0x00,0x00,0xd4] +// CHECK: smc #{{12000|0x2ee0}} // encoding: [0x03,0xdc,0x05,0xd4] // CHECK: brk #{{12|0xc}} // encoding: [0x80,0x01,0x20,0xd4] // CHECK: hlt #{{123|0x7b}} // encoding: [0x60,0x0f,0x40,0xd4] dcps1 #42 dcps2 #9 + dcps3 #1000 // CHECK: dcps1 #{{42|0x2a}} // encoding: [0x41,0x05,0xa0,0xd4] // CHECK: dcps2 #{{9|0x9}} // encoding: [0x22,0x01,0xa0,0xd4] +// CHECK: dcps3 #{{1000|0x3e8}} // encoding: [0x03,0x7d,0xa0,0xd4] dcps1 dcps2 + dcps3 // CHECK: dcps1 // encoding: [0x01,0x00,0xa0,0xd4] // CHECK: dcps2 // encoding: [0x02,0x00,0xa0,0xd4] +// CHECK: dcps3 // encoding: [0x03,0x00,0xa0,0xd4] //------------------------------------------------------------------------------ // Extract (immediate) @@ -3779,11 +3785,13 @@ msr HACR_EL2, x12 msr MDCR_EL3, x12 msr TTBR0_EL1, x12 + msr TTBR0_EL2, x12 msr TTBR0_EL3, x12 msr TTBR1_EL1, x12 msr TCR_EL1, x12 msr TCR_EL2, x12 msr TCR_EL3, x12 + msr VTTBR_EL2, x12 msr VTCR_EL2, x12 msr DACR32_EL2, x12 msr SPSR_EL1, x12 @@ -4030,11 +4038,13 @@ // CHECK: msr {{hacr_el2|HACR_EL2}}, x12 // encoding: [0xec,0x11,0x1c,0xd5] // CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 // encoding: [0x2c,0x13,0x1e,0xd5] // CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 // encoding: [0x0c,0x20,0x18,0xd5] +// CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 // encoding: [0x0c,0x20,0x1c,0xd5] // CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 // encoding: [0x0c,0x20,0x1e,0xd5] // CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 // encoding: [0x2c,0x20,0x18,0xd5] // CHECK: msr {{tcr_el1|TCR_EL1}}, x12 // encoding: [0x4c,0x20,0x18,0xd5] // CHECK: msr {{tcr_el2|TCR_EL2}}, x12 // encoding: [0x4c,0x20,0x1c,0xd5] // CHECK: msr {{tcr_el3|TCR_EL3}}, x12 // encoding: [0x4c,0x20,0x1e,0xd5] +// CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 // encoding: [0x0c,0x21,0x1c,0xd5] // CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 // encoding: [0x4c,0x21,0x1c,0xd5] // CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 // encoding: [0x0c,0x30,0x1c,0xd5] // CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 // encoding: [0x0c,0x40,0x18,0xd5] @@ -4322,11 +4332,13 @@ mrs x9, HACR_EL2 mrs x9, MDCR_EL3 mrs x9, TTBR0_EL1 + mrs x9, TTBR0_EL2 mrs x9, TTBR0_EL3 mrs x9, TTBR1_EL1 mrs x9, TCR_EL1 mrs x9, TCR_EL2 mrs x9, TCR_EL3 + mrs x9, VTTBR_EL2 mrs x9, VTCR_EL2 mrs x9, DACR32_EL2 mrs x9, SPSR_EL1 @@ -4623,11 +4635,13 @@ // CHECK: mrs x9, {{hacr_el2|HACR_EL2}} // encoding: [0xe9,0x11,0x3c,0xd5] // CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} // encoding: [0x29,0x13,0x3e,0xd5] // CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} // encoding: [0x09,0x20,0x38,0xd5] +// CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} // encoding: [0x09,0x20,0x3c,0xd5] // CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} // encoding: [0x09,0x20,0x3e,0xd5] // CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} // encoding: [0x29,0x20,0x38,0xd5] // CHECK: mrs x9, {{tcr_el1|TCR_EL1}} // encoding: [0x49,0x20,0x38,0xd5] // CHECK: mrs x9, {{tcr_el2|TCR_EL2}} // encoding: [0x49,0x20,0x3c,0xd5] // CHECK: mrs x9, {{tcr_el3|TCR_EL3}} // encoding: [0x49,0x20,0x3e,0xd5] +// CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} // encoding: [0x09,0x21,0x3c,0xd5] // CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} // encoding: [0x49,0x21,0x3c,0xd5] // CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} // encoding: [0x09,0x30,0x3c,0xd5] // CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} // encoding: [0x09,0x40,0x38,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/arm64-branch.txt b/llvm/test/MC/Disassembler/AArch64/arm64-branch.txt --- a/llvm/test/MC/Disassembler/AArch64/arm64-branch.txt +++ b/llvm/test/MC/Disassembler/AArch64/arm64-branch.txt @@ -29,10 +29,14 @@ # CHECK: dcps1 #0x2 0x62 0x00 0xa0 0xd4 # CHECK: dcps2 #0x3 + 0x83 0x00 0xa0 0xd4 +# CHECK: dcps3 #0x4 0xa0 0x00 0x40 0xd4 # CHECK: hlt #0x5 0xc2 0x00 0x00 0xd4 # CHECK: hvc #0x6 + 0xe3 0x00 0x00 0xd4 +# CHECK: smc #0x7 0x01 0x01 0x00 0xd4 # CHECK: svc #0x8 diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,6 +1,6 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 +# RUN: llvm-mc -triple=aarch64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 # RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82 # RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83 @@ -1257,21 +1257,27 @@ 0xe1 0xff 0x1f 0xd4 # CHECK: hvc #{{1|0x1}} +# CHECK: smc #{{12000|0x2ee0}} # CHECK: brk #{{12|0xc}} # CHECK: hlt #{{123|0x7b}} 0x22 0x0 0x0 0xd4 +0x3 0xdc 0x5 0xd4 0x80 0x1 0x20 0xd4 0x60 0xf 0x40 0xd4 # CHECK: dcps1 #{{42|0x2a}} # CHECK: dcps2 #{{9|0x9}} +# CHECK: dcps3 #{{1000|0x3e8}} 0x41 0x5 0xa0 0xd4 0x22 0x1 0xa0 0xd4 +0x3 0x7d 0xa0 0xd4 # CHECK: dcps1 # CHECK: dcps2 +# CHECK: dcps3 0x1 0x0 0xa0 0xd4 0x2 0x0 0xa0 0xd4 +0x3 0x0 0xa0 0xd4 #------------------------------------------------------------------------------ # Extract (immediate) @@ -3252,11 +3258,13 @@ # CHECK: msr {{hacr_el2|HACR_EL2}}, x12 # CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 # CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 +# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 # CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 # CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 # CHECK: msr {{tcr_el1|TCR_EL1}}, x12 # CHECK: msr {{tcr_el2|TCR_EL2}}, x12 # CHECK: msr {{tcr_el3|TCR_EL3}}, x12 +# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 # CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 # CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 # CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 @@ -3545,11 +3553,13 @@ # CHECK: mrs x9, {{hacr_el2|HACR_EL2}} # CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} # CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} +# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} # CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} # CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} # CHECK: mrs x9, {{tcr_el1|TCR_EL1}} # CHECK: mrs x9, {{tcr_el2|TCR_EL2}} # CHECK: mrs x9, {{tcr_el3|TCR_EL3}} +# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} # CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} # CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} # CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}