diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -2658,6 +2658,8 @@
 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
 def BITCONVERT_32_I2F16x2 : F_BITCONVERT<"32", Int32Regs, Float16x2Regs>;
 def BITCONVERT_32_F16x22I : F_BITCONVERT<"32", Float16x2Regs, Int32Regs>;
+def BITCONVERT_32_F2F16x2 : F_BITCONVERT<"32", Float32Regs, Float16x2Regs>;
+def BITCONVERT_32_F16x22F : F_BITCONVERT<"32", Float16x2Regs, Float32Regs>;
 
 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
 // we cannot specify floating-point literals in isel patterns.  Therefore, we
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1002,6 +1002,25 @@
   ret <2 x half> %r
 }
 
+; CHECK-LABEL: test_bitcast_float_to_2xhalf(
+; CHECK: ld.param.f32 	[[AF1:%f[0-9]+]], [test_bitcast_float_to_2xhalf_param_0];
+; CHECK: mov.b32 	[[R:%hh[0-9]+]], [[AF1]];
+; CHECK: st.param.b32 	[func_retval0+0], [[R]];
+; CHECK: ret;
+define <2 x half> @test_bitcast_float_to_2xhalf(float %a) #0 {
+  %r = bitcast float %a to <2 x half>
+  ret <2 x half> %r
+}
+
+; CHECK-LABEL: test_bitcast_2xhalf_to_float(
+; CHECK: ld.param.u32 	[[R:%r[0-9]+]], [test_bitcast_2xhalf_to_float_param_0];
+; CHECK: mov.b32 	[[AF1:%f[0-9]+]], [[R]];
+; CHECK: st.param.f32 	[func_retval0+0], [[AF1]];
+; CHECK: ret;
+define float @test_bitcast_2xhalf_to_float(<2 x half> %a) #0 {
+  %r = bitcast <2 x half> %a to float
+  ret float %r
+}
 
 declare <2 x half> @llvm.sqrt.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.powi.f16.i32(<2 x half> %a, <2 x i32> %b) #0