diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -178,6 +178,9 @@ BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi","") BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc","") +BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc","") +BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc","") +BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc","") BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "") BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "") @@ -189,6 +192,9 @@ BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi","") BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","") BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc","") +BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc","") +BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc","") +BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc","") BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "") BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "") @@ -524,12 +530,12 @@ BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "") // P10 Vector String Isolate Built-ins. -BUILTIN(__builtin_altivec_vstribr, "V16cV16c", "") -BUILTIN(__builtin_altivec_vstribl, "V16cV16c", "") +BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "") +BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "") BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "") BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "") -BUILTIN(__builtin_altivec_vstribr_p, "iiV16c", "") -BUILTIN(__builtin_altivec_vstribl_p, "iiV16c", "") +BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "") +BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "") BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "") BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "") @@ -540,8 +546,8 @@ BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "") // P10 Vector Clear Bytes built-ins. -BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "") -BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "") +BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "") +BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "") // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins. BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "") @@ -566,8 +572,10 @@ BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "") BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "") BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "") -BUILTIN(__builtin_altivec_vec_replace_elt, "V4UiV4UiUiIi", "t") -BUILTIN(__builtin_altivec_vec_replace_unaligned, "V4UiV4UiUiIi", "t") +BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "") +BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "") +BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "") +BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "") // P10 Vector Extract built-ins. BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -15575,65 +15575,65 @@ Function *F = CGM.getIntrinsic(Intrinsic::cttz, ResultType); return Builder.CreateCall(F, {X, Undef}); } - case PPC::BI__builtin_altivec_vec_replace_elt: - case PPC::BI__builtin_altivec_vec_replace_unaligned: { + case PPC::BI__builtin_altivec_vinsd: + case PPC::BI__builtin_altivec_vinsw: + case PPC::BI__builtin_altivec_vinsd_elt: + case PPC::BI__builtin_altivec_vinsw_elt: { + llvm::Type *ResultType = ConvertType(E->getType()); Value *Op0 = EmitScalarExpr(E->getArg(0)); Value *Op1 = EmitScalarExpr(E->getArg(1)); Value *Op2 = EmitScalarExpr(E->getArg(2)); - // The third argument of vec_replace_elt and vec_replace_unaligned must - // be a compile time constant and will be emitted either to the vinsw - // or vinsd instruction. + + bool IsUnaligned = (BuiltinID == PPC::BI__builtin_altivec_vinsw || + BuiltinID == PPC::BI__builtin_altivec_vinsd); + + bool Is32bit = (BuiltinID == PPC::BI__builtin_altivec_vinsw || + BuiltinID == PPC::BI__builtin_altivec_vinsw_elt); + + // The third argument must be a compile time constant. ConstantInt *ArgCI = dyn_cast(Op2); assert(ArgCI && "Third Arg to vinsw/vinsd intrinsic must be a constant integer!"); - llvm::Type *ResultType = ConvertType(E->getType()); - llvm::Function *F = nullptr; - Value *Call = nullptr; + + // Valid value for the third argument is dependent on the input type and + // builtin called. + int ValidMaxValue = 0; + if (IsUnaligned) + ValidMaxValue = (Is32bit) ? 12 : 8; + else + ValidMaxValue = (Is32bit) ? 3 : 1; + + // Get value of third argument. int64_t ConstArg = ArgCI->getSExtValue(); - unsigned ArgWidth = Op1->getType()->getPrimitiveSizeInBits(); - bool Is32Bit = false; - assert((ArgWidth == 32 || ArgWidth == 64) && "Invalid argument width"); - // The input to vec_replace_elt is an element index, not a byte index. - if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt) - ConstArg *= ArgWidth / 8; - if (ArgWidth == 32) { - Is32Bit = true; - // When the second argument is 32 bits, it can either be an integer or - // a float. The vinsw intrinsic is used in this case. - F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsw); + + // Compose range checking error message. + std::string RangeErrMsg = IsUnaligned ? "byte" : "element"; + RangeErrMsg += " number " + llvm::to_string(ConstArg); + RangeErrMsg += " is outside of the valid range [0, "; + RangeErrMsg += llvm::to_string(ValidMaxValue) + "]"; + + // Issue error if third argument is not within the valid range. + if (ConstArg < 0 or ConstArg > ValidMaxValue) + CGM.Error(E->getExprLoc(), RangeErrMsg); + + // Input to vec_replace_elt is an element index, convert to byte index. + if (!IsUnaligned) { + ConstArg *= Is32bit ? 4 : 8; // Fix the constant according to endianess. if (getTarget().isLittleEndian()) - ConstArg = 12 - ConstArg; - } else { - // When the second argument is 64 bits, it can either be a long long or - // a double. The vinsd intrinsic is used in this case. - F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsd); - // Fix the constant for little endian. - if (getTarget().isLittleEndian()) - ConstArg = 8 - ConstArg; + ConstArg = (Is32bit ? 12 : 8) - ConstArg; } + + ID = Is32bit ? Intrinsic::ppc_altivec_vinsw : Intrinsic::ppc_altivec_vinsd; Op2 = ConstantInt::getSigned(Int32Ty, ConstArg); - // Depending on ArgWidth, the input vector could be a float or a double. - // If the input vector is a float type, bitcast the inputs to integers. Or, - // if the input vector is a double, bitcast the inputs to 64-bit integers. - if (!Op1->getType()->isIntegerTy(ArgWidth)) { - Op0 = Builder.CreateBitCast( - Op0, Is32Bit ? llvm::FixedVectorType::get(Int32Ty, 4) - : llvm::FixedVectorType::get(Int64Ty, 2)); - Op1 = Builder.CreateBitCast(Op1, Is32Bit ? Int32Ty : Int64Ty); - } - // Emit the call to vinsw or vinsd. - Call = Builder.CreateCall(F, {Op0, Op1, Op2}); - // Depending on the builtin, bitcast to the approriate result type. - if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt && - !Op1->getType()->isIntegerTy()) - return Builder.CreateBitCast(Call, ResultType); - else if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt && - Op1->getType()->isIntegerTy()) - return Call; - else - return Builder.CreateBitCast(Call, - llvm::FixedVectorType::get(Int8Ty, 16)); + // Casting input to vector int as per intrinsic definition. + Op0 = + Is32bit + ? Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int32Ty, 4)) + : Builder.CreateBitCast(Op0, + llvm::FixedVectorType::get(Int64Ty, 2)); + return Builder.CreateBitCast( + Builder.CreateCall(CGM.getIntrinsic(ID), {Op0, Op1, Op2}), ResultType); } case PPC::BI__builtin_altivec_vpopcntb: case PPC::BI__builtin_altivec_vpopcnth: @@ -15656,6 +15656,51 @@ else return Builder.CreateSub(Op0, Op1, "vsubuqm"); } + case PPC::BI__builtin_altivec_vaddcuq_c: + case PPC::BI__builtin_altivec_vsubcuq_c: { + SmallVector Ops; + Value *Op0 = EmitScalarExpr(E->getArg(0)); + Value *Op1 = EmitScalarExpr(E->getArg(1)); + llvm::Type *V1I128Ty = llvm::FixedVectorType::get( + llvm::IntegerType::get(getLLVMContext(), 128), 1); + Ops.push_back(Builder.CreateBitCast(Op0, V1I128Ty)); + Ops.push_back(Builder.CreateBitCast(Op1, V1I128Ty)); + ID = (BuiltinID == PPC::BI__builtin_altivec_vaddcuq_c) + ? Intrinsic::ppc_altivec_vaddcuq + : Intrinsic::ppc_altivec_vsubcuq; + return Builder.CreateCall(CGM.getIntrinsic(ID), Ops, ""); + } + case PPC::BI__builtin_altivec_vaddeuqm_c: + case PPC::BI__builtin_altivec_vaddecuq_c: + case PPC::BI__builtin_altivec_vsubeuqm_c: + case PPC::BI__builtin_altivec_vsubecuq_c: { + SmallVector Ops; + Value *Op0 = EmitScalarExpr(E->getArg(0)); + Value *Op1 = EmitScalarExpr(E->getArg(1)); + Value *Op2 = EmitScalarExpr(E->getArg(2)); + llvm::Type *V1I128Ty = llvm::FixedVectorType::get( + llvm::IntegerType::get(getLLVMContext(), 128), 1); + Ops.push_back(Builder.CreateBitCast(Op0, V1I128Ty)); + Ops.push_back(Builder.CreateBitCast(Op1, V1I128Ty)); + Ops.push_back(Builder.CreateBitCast(Op2, V1I128Ty)); + switch (BuiltinID) { + default: + llvm_unreachable("Unsupported intrinsic!"); + case PPC::BI__builtin_altivec_vaddeuqm_c: + ID = Intrinsic::ppc_altivec_vaddeuqm; + break; + case PPC::BI__builtin_altivec_vaddecuq_c: + ID = Intrinsic::ppc_altivec_vaddecuq; + break; + case PPC::BI__builtin_altivec_vsubeuqm_c: + ID = Intrinsic::ppc_altivec_vsubeuqm; + break; + case PPC::BI__builtin_altivec_vsubecuq_c: + ID = Intrinsic::ppc_altivec_vsubecuq; + break; + } + return Builder.CreateCall(CGM.getIntrinsic(ID), Ops, ""); + } // Rotate and insert under mask operation. // __rldimi(rs, is, shift, mask) // (rotl64(rs, shift) & mask) | (is & ~mask) diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h --- a/clang/lib/Headers/altivec.h +++ b/clang/lib/Headers/altivec.h @@ -311,7 +311,7 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_add_u128(vector unsigned char __a, vector unsigned char __b) { - return __builtin_altivec_vadduqm(__a, __b); + return (vector unsigned char)__builtin_altivec_vadduqm(__a, __b); } #elif defined(__VSX__) static __inline__ vector signed long long __ATTRS_o_ai @@ -325,9 +325,9 @@ (vector unsigned int)__a + (vector unsigned int)__b; vector unsigned int __carry = __builtin_altivec_vaddcuw( (vector unsigned int)__a, (vector unsigned int)__b); - __carry = __builtin_shufflevector((vector unsigned char)__carry, - (vector unsigned char)__carry, 0, 0, 0, 7, - 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0); + __carry = (vector unsigned int)__builtin_shufflevector( + (vector unsigned char)__carry, (vector unsigned char)__carry, 0, 0, 0, 7, + 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0); return (vector signed long long)(__res + __carry); #endif } @@ -358,7 +358,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_adde(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vaddeuqm(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vaddeuqm( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -371,7 +373,9 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_adde_u128(vector unsigned char __a, vector unsigned char __b, vector unsigned char __c) { - return (vector unsigned char)__builtin_altivec_vaddeuqm(__a, __b, __c); + return (vector unsigned char)__builtin_altivec_vaddeuqm_c( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } #endif @@ -398,7 +402,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_addec(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vaddecuq(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vaddecuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -411,7 +417,9 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_addec_u128(vector unsigned char __a, vector unsigned char __b, vector unsigned char __c) { - return (vector unsigned char)__builtin_altivec_vaddecuq(__a, __b, __c); + return (vector unsigned char)__builtin_altivec_vaddecuq_c( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } #ifdef __powerpc64__ @@ -600,7 +608,8 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_addc_u128(vector unsigned char __a, vector unsigned char __b) { - return (vector unsigned char)__builtin_altivec_vaddcuq(__a, __b); + return (vector unsigned char)__builtin_altivec_vaddcuq_c( + (vector unsigned char)__a, (vector unsigned char)__b); } #endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__) @@ -824,7 +833,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vaddeuqm(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vaddeuqm(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vaddeuqm( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -837,7 +848,8 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vaddcuq(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vaddcuq(__a, __b); + return (vector signed __int128)__builtin_altivec_vaddcuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -850,7 +862,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vaddecuq(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vaddecuq(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vaddecuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -1806,18 +1820,19 @@ static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpeq(vector signed __int128 __a, vector signed __int128 __b) { return (vector bool __int128)__builtin_altivec_vcmpequq( - (vector bool __int128)__a, (vector bool __int128)__b); + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpeq(vector unsigned __int128 __a, vector unsigned __int128 __b) { return (vector bool __int128)__builtin_altivec_vcmpequq( - (vector bool __int128)__a, (vector bool __int128)__b); + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpeq(vector bool __int128 __a, vector bool __int128 __b) { - return (vector bool __int128)__builtin_altivec_vcmpequq(__a, __b); + return (vector bool __int128)__builtin_altivec_vcmpequq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } #endif @@ -1887,19 +1902,20 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpne(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return (vector bool __int128) ~(__builtin_altivec_vcmpequq( - (vector bool __int128)__a, (vector bool __int128)__b)); + return (vector bool __int128)~(__builtin_altivec_vcmpequq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b)); } static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpne(vector signed __int128 __a, vector signed __int128 __b) { - return (vector bool __int128) ~(__builtin_altivec_vcmpequq( - (vector bool __int128)__a, (vector bool __int128)__b)); + return (vector bool __int128)~(__builtin_altivec_vcmpequq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b)); } static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpne(vector bool __int128 __a, vector bool __int128 __b) { - return (vector bool __int128) ~(__builtin_altivec_vcmpequq(__a, __b)); + return (vector bool __int128)~(__builtin_altivec_vcmpequq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b)); } #endif @@ -1944,16 +1960,16 @@ static __inline__ signed int __ATTRS_o_ai vec_cntlz_lsbb(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vctzlsbb(__a); + return __builtin_altivec_vctzlsbb((vector unsigned char)__a); #else - return __builtin_altivec_vclzlsbb(__a); + return __builtin_altivec_vclzlsbb((vector unsigned char)__a); #endif } static __inline__ signed int __ATTRS_o_ai vec_cntlz_lsbb(vector unsigned char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vctzlsbb(__a); + return __builtin_altivec_vctzlsbb((vector unsigned char)__a); #else return __builtin_altivec_vclzlsbb(__a); #endif @@ -1962,9 +1978,9 @@ static __inline__ signed int __ATTRS_o_ai vec_cnttz_lsbb(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vclzlsbb(__a); + return __builtin_altivec_vclzlsbb((vector unsigned char)__a); #else - return __builtin_altivec_vctzlsbb(__a); + return __builtin_altivec_vctzlsbb((vector unsigned char)__a); #endif } @@ -1984,7 +2000,7 @@ static __inline__ vector unsigned int __ATTRS_o_ai vec_parity_lsbb(vector signed int __a) { - return __builtin_altivec_vprtybw(__a); + return __builtin_altivec_vprtybw((vector unsigned int)__a); } #ifdef __SIZEOF_INT128__ @@ -1995,7 +2011,7 @@ static __inline__ vector unsigned __int128 __ATTRS_o_ai vec_parity_lsbb(vector signed __int128 __a) { - return __builtin_altivec_vprtybq(__a); + return __builtin_altivec_vprtybq((vector unsigned __int128)__a); } #endif @@ -2006,7 +2022,7 @@ static __inline__ vector unsigned long long __ATTRS_o_ai vec_parity_lsbb(vector signed long long __a) { - return __builtin_altivec_vprtybd(__a); + return __builtin_altivec_vprtybd((vector unsigned long long)__a); } #else @@ -2212,14 +2228,12 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpgt(vector signed __int128 __a, vector signed __int128 __b) { - return (vector bool __int128)__builtin_altivec_vcmpgtsq( - (vector bool __int128)__a, (vector bool __int128)__b); + return (vector bool __int128)__builtin_altivec_vcmpgtsq(__a, __b); } static __inline__ vector bool __int128 __ATTRS_o_ai vec_cmpgt(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return (vector bool __int128)__builtin_altivec_vcmpgtuq( - (vector bool __int128)__a, (vector bool __int128)__b); + return (vector bool __int128)__builtin_altivec_vcmpgtuq(__a, __b); } #endif @@ -2488,7 +2502,8 @@ static __inline__ vector unsigned char __ATTRS_o_ai vec_popcnt(vector signed char __a) { - return __builtin_altivec_vpopcntb(__a); + return (vector unsigned char)__builtin_altivec_vpopcntb( + (vector unsigned char)__a); } static __inline__ vector unsigned char __ATTRS_o_ai vec_popcnt(vector unsigned char __a) { @@ -2496,7 +2511,8 @@ } static __inline__ vector unsigned short __ATTRS_o_ai vec_popcnt(vector signed short __a) { - return __builtin_altivec_vpopcnth(__a); + return (vector unsigned short)__builtin_altivec_vpopcnth( + (vector unsigned short)__a); } static __inline__ vector unsigned short __ATTRS_o_ai vec_popcnt(vector unsigned short __a) { @@ -2504,7 +2520,7 @@ } static __inline__ vector unsigned int __ATTRS_o_ai vec_popcnt(vector signed int __a) { - return __builtin_altivec_vpopcntw(__a); + return __builtin_altivec_vpopcntw((vector unsigned int)__a); } static __inline__ vector unsigned int __ATTRS_o_ai vec_popcnt(vector unsigned int __a) { @@ -2512,7 +2528,7 @@ } static __inline__ vector unsigned long long __ATTRS_o_ai vec_popcnt(vector signed long long __a) { - return __builtin_altivec_vpopcntd(__a); + return __builtin_altivec_vpopcntd((vector unsigned long long)__a); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_popcnt(vector unsigned long long __a) { @@ -2524,7 +2540,7 @@ static __inline__ vector signed char __ATTRS_o_ai vec_cntlz(vector signed char __a) { - return __builtin_altivec_vclzb(__a); + return (vector signed char)__builtin_altivec_vclzb((vector unsigned char)__a); } static __inline__ vector unsigned char __ATTRS_o_ai vec_cntlz(vector unsigned char __a) { @@ -2532,7 +2548,8 @@ } static __inline__ vector signed short __ATTRS_o_ai vec_cntlz(vector signed short __a) { - return __builtin_altivec_vclzh(__a); + return (vector signed short)__builtin_altivec_vclzh( + (vector unsigned short)__a); } static __inline__ vector unsigned short __ATTRS_o_ai vec_cntlz(vector unsigned short __a) { @@ -2540,7 +2557,7 @@ } static __inline__ vector signed int __ATTRS_o_ai vec_cntlz(vector signed int __a) { - return __builtin_altivec_vclzw(__a); + return (vector signed int)__builtin_altivec_vclzw((vector unsigned int)__a); } static __inline__ vector unsigned int __ATTRS_o_ai vec_cntlz(vector unsigned int __a) { @@ -2548,7 +2565,8 @@ } static __inline__ vector signed long long __ATTRS_o_ai vec_cntlz(vector signed long long __a) { - return __builtin_altivec_vclzd(__a); + return (vector signed long long)__builtin_altivec_vclzd( + (vector unsigned long long)__a); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_cntlz(vector unsigned long long __a) { @@ -2562,7 +2580,7 @@ static __inline__ vector signed char __ATTRS_o_ai vec_cnttz(vector signed char __a) { - return __builtin_altivec_vctzb(__a); + return (vector signed char)__builtin_altivec_vctzb((vector unsigned char)__a); } static __inline__ vector unsigned char __ATTRS_o_ai vec_cnttz(vector unsigned char __a) { @@ -2570,7 +2588,8 @@ } static __inline__ vector signed short __ATTRS_o_ai vec_cnttz(vector signed short __a) { - return __builtin_altivec_vctzh(__a); + return (vector signed short)__builtin_altivec_vctzh( + (vector unsigned short)__a); } static __inline__ vector unsigned short __ATTRS_o_ai vec_cnttz(vector unsigned short __a) { @@ -2578,7 +2597,7 @@ } static __inline__ vector signed int __ATTRS_o_ai vec_cnttz(vector signed int __a) { - return __builtin_altivec_vctzw(__a); + return (vector signed int)__builtin_altivec_vctzw((vector unsigned int)__a); } static __inline__ vector unsigned int __ATTRS_o_ai vec_cnttz(vector unsigned int __a) { @@ -2586,7 +2605,8 @@ } static __inline__ vector signed long long __ATTRS_o_ai vec_cnttz(vector signed long long __a) { - return __builtin_altivec_vctzd(__a); + return (vector signed long long)__builtin_altivec_vctzd( + (vector unsigned long long)__a); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_cnttz(vector unsigned long long __a) { @@ -3144,7 +3164,8 @@ vector unsigned char __mask = (vector unsigned char)__builtin_altivec_lvsl(16 - __c, (int *)NULL); vector unsigned char __res = - __builtin_altivec_vperm_4si((vector int)__a, (vector int)__a, __mask); + (vector unsigned char)__builtin_altivec_vperm_4si( + (vector int)__a, (vector int)__a, __mask); return __builtin_vsx_stxvll((vector int)__res, __b, (__c << 56)); } #endif @@ -3181,34 +3202,40 @@ // the XL-compatible signatures are used for those functions. #ifdef __XL_COMPAT_ALTIVEC__ #define vec_ctf(__a, __b) \ - _Generic((__a), vector int \ - : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)), \ - vector unsigned int \ - : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \ - (__b)), \ - vector unsigned long long \ - : (__builtin_vsx_xvcvuxdsp((vector unsigned long long)(__a)) * \ - (vector float)(vector unsigned)((0x7f - (__b)) << 23)), \ - vector signed long long \ - : (__builtin_vsx_xvcvsxdsp((vector signed long long)(__a)) * \ - (vector float)(vector unsigned)((0x7f - (__b)) << 23))) + _Generic( \ + (__a), vector int \ + : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)), \ + vector unsigned int \ + : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \ + (__b)), \ + vector unsigned long long \ + : (vector float)(__builtin_vsx_xvcvuxdsp( \ + (vector unsigned long long)(__a)) * \ + (vector float)(vector unsigned)((0x7f - (__b)) << 23)), \ + vector signed long long \ + : (vector float)(__builtin_vsx_xvcvsxdsp( \ + (vector signed long long)(__a)) * \ + (vector float)(vector unsigned)((0x7f - (__b)) << 23))) #else // __XL_COMPAT_ALTIVEC__ #define vec_ctf(__a, __b) \ - _Generic((__a), vector int \ - : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)), \ - vector unsigned int \ - : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \ - (__b)), \ - vector unsigned long long \ - : (__builtin_convertvector((vector unsigned long long)(__a), \ - vector double) * \ - (vector double)(vector unsigned long long)((0x3ffULL - (__b)) \ - << 52)), \ - vector signed long long \ - : (__builtin_convertvector((vector signed long long)(__a), \ - vector double) * \ - (vector double)(vector unsigned long long)((0x3ffULL - (__b)) \ - << 52))) + _Generic( \ + (__a), vector int \ + : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)), \ + vector unsigned int \ + : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \ + (__b)), \ + vector unsigned long long \ + : (vector float)(__builtin_convertvector( \ + (vector unsigned long long)(__a), vector double) * \ + (vector double)(vector unsigned long long)((0x3ffULL - \ + (__b)) \ + << 52)), \ + vector signed long long \ + : (vector float)(__builtin_convertvector((vector signed long long)(__a), \ + vector double) * \ + (vector double)(vector unsigned long long)((0x3ffULL - \ + (__b)) \ + << 52))) #endif // __XL_COMPAT_ALTIVEC__ #else #define vec_ctf(__a, __b) \ @@ -3255,26 +3282,29 @@ #ifdef __XL_COMPAT_ALTIVEC__ #define vec_cts(__a, __b) \ _Generic((__a), vector float \ - : __builtin_altivec_vctsxs((vector float)(__a), (__b)), \ + : (vector signed int)__builtin_altivec_vctsxs((vector float)(__a), \ + (__b)), \ vector double \ : __extension__({ \ vector double __ret = \ (vector double)(__a) * \ (vector double)(vector unsigned long long)((0x3ffULL + (__b)) \ << 52); \ - __builtin_vsx_xvcvdpsxws(__ret); \ + (vector signed long long)__builtin_vsx_xvcvdpsxws(__ret); \ })) #else // __XL_COMPAT_ALTIVEC__ #define vec_cts(__a, __b) \ _Generic((__a), vector float \ - : __builtin_altivec_vctsxs((vector float)(__a), (__b)), \ + : (vector signed int)__builtin_altivec_vctsxs((vector float)(__a), \ + (__b)), \ vector double \ : __extension__({ \ vector double __ret = \ (vector double)(__a) * \ (vector double)(vector unsigned long long)((0x3ffULL + (__b)) \ << 52); \ - __builtin_convertvector(__ret, vector signed long long); \ + (vector signed long long)__builtin_convertvector( \ + __ret, vector signed long long); \ })) #endif // __XL_COMPAT_ALTIVEC__ #else @@ -3291,26 +3321,29 @@ #ifdef __XL_COMPAT_ALTIVEC__ #define vec_ctu(__a, __b) \ _Generic((__a), vector float \ - : __builtin_altivec_vctuxs((vector float)(__a), (__b)), \ + : (vector unsigned int)__builtin_altivec_vctuxs( \ + (vector float)(__a), (__b)), \ vector double \ : __extension__({ \ vector double __ret = \ (vector double)(__a) * \ (vector double)(vector unsigned long long)((0x3ffULL + __b) \ << 52); \ - __builtin_vsx_xvcvdpuxws(__ret); \ + (vector unsigned long long)__builtin_vsx_xvcvdpuxws(__ret); \ })) #else // __XL_COMPAT_ALTIVEC__ #define vec_ctu(__a, __b) \ _Generic((__a), vector float \ - : __builtin_altivec_vctuxs((vector float)(__a), (__b)), \ + : (vector unsigned int)__builtin_altivec_vctuxs( \ + (vector float)(__a), (__b)), \ vector double \ : __extension__({ \ vector double __ret = \ (vector double)(__a) * \ (vector double)(vector unsigned long long)((0x3ffULL + __b) \ << 52); \ - __builtin_convertvector(__ret, vector unsigned long long); \ + (vector unsigned long long)__builtin_convertvector( \ + __ret, vector unsigned long long); \ })) #endif // __XL_COMPAT_ALTIVEC__ #else @@ -6491,12 +6524,12 @@ static __inline__ vector signed char __ATTRS_o_ai vec_nand(vector signed char __a, vector bool char __b) { - return ~(__a & __b); + return ~(__a & (vector signed char)__b); } static __inline__ vector signed char __ATTRS_o_ai vec_nand(vector bool char __a, vector signed char __b) { - return ~(__a & __b); + return (vector signed char)~(__a & (vector bool char)__b); } static __inline__ vector unsigned char __ATTRS_o_ai @@ -6506,12 +6539,12 @@ static __inline__ vector unsigned char __ATTRS_o_ai vec_nand(vector unsigned char __a, vector bool char __b) { - return ~(__a & __b); + return ~(__a & (vector unsigned char)__b); } static __inline__ vector unsigned char __ATTRS_o_ai vec_nand(vector bool char __a, vector unsigned char __b) { - return ~(__a & __b); + return (vector unsigned char)~(__a & (vector bool char)__b); } static __inline__ vector bool char __ATTRS_o_ai vec_nand(vector bool char __a, @@ -6526,12 +6559,12 @@ static __inline__ vector signed short __ATTRS_o_ai vec_nand(vector signed short __a, vector bool short __b) { - return ~(__a & __b); + return ~(__a & (vector signed short)__b); } static __inline__ vector signed short __ATTRS_o_ai vec_nand(vector bool short __a, vector signed short __b) { - return ~(__a & __b); + return (vector signed short)~(__a & (vector bool short)__b); } static __inline__ vector unsigned short __ATTRS_o_ai @@ -6541,7 +6574,7 @@ static __inline__ vector unsigned short __ATTRS_o_ai vec_nand(vector unsigned short __a, vector bool short __b) { - return ~(__a & __b); + return ~(__a & (vector unsigned short)__b); } static __inline__ vector bool short __ATTRS_o_ai @@ -6556,12 +6589,12 @@ static __inline__ vector signed int __ATTRS_o_ai vec_nand(vector signed int __a, vector bool int __b) { - return ~(__a & __b); + return ~(__a & (vector signed int)__b); } static __inline__ vector signed int __ATTRS_o_ai vec_nand(vector bool int __a, vector signed int __b) { - return ~(__a & __b); + return (vector signed int)~(__a & (vector bool int)__b); } static __inline__ vector unsigned int __ATTRS_o_ai @@ -6571,12 +6604,12 @@ static __inline__ vector unsigned int __ATTRS_o_ai vec_nand(vector unsigned int __a, vector bool int __b) { - return ~(__a & __b); + return ~(__a & (vector unsigned int)__b); } static __inline__ vector unsigned int __ATTRS_o_ai vec_nand(vector bool int __a, vector unsigned int __b) { - return ~(__a & __b); + return (vector unsigned int)~(__a & (vector bool int)__b); } static __inline__ vector bool int __ATTRS_o_ai vec_nand(vector bool int __a, @@ -6597,12 +6630,12 @@ static __inline__ vector signed long long __ATTRS_o_ai vec_nand(vector signed long long __a, vector bool long long __b) { - return ~(__a & __b); + return ~(__a & (vector signed long long)__b); } static __inline__ vector signed long long __ATTRS_o_ai vec_nand(vector bool long long __a, vector signed long long __b) { - return ~(__a & __b); + return (vector signed long long)~(__a & (vector bool long long)__b); } static __inline__ vector unsigned long long __ATTRS_o_ai @@ -6612,12 +6645,12 @@ static __inline__ vector unsigned long long __ATTRS_o_ai vec_nand(vector unsigned long long __a, vector bool long long __b) { - return ~(__a & __b); + return ~(__a & (vector unsigned long long)__b); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_nand(vector bool long long __a, vector unsigned long long __b) { - return ~(__a & __b); + return (vector unsigned long long)~(__a & (vector bool long long)__b); } static __inline__ vector bool long long __ATTRS_o_ai @@ -7005,12 +7038,12 @@ static __inline__ vector signed char __ATTRS_o_ai vec_orc(vector signed char __a, vector bool char __b) { - return __a | ~__b; + return __a | (vector signed char)~__b; } static __inline__ vector signed char __ATTRS_o_ai vec_orc(vector bool char __a, vector signed char __b) { - return __a | ~__b; + return (vector signed char)(__a | (vector bool char)~__b); } static __inline__ vector unsigned char __ATTRS_o_ai @@ -7020,12 +7053,12 @@ static __inline__ vector unsigned char __ATTRS_o_ai vec_orc(vector unsigned char __a, vector bool char __b) { - return __a | ~__b; + return __a | (vector unsigned char)~__b; } static __inline__ vector unsigned char __ATTRS_o_ai vec_orc(vector bool char __a, vector unsigned char __b) { - return __a | ~__b; + return (vector unsigned char)(__a | (vector bool char)~__b); } static __inline__ vector bool char __ATTRS_o_ai vec_orc(vector bool char __a, @@ -7040,12 +7073,12 @@ static __inline__ vector signed short __ATTRS_o_ai vec_orc(vector signed short __a, vector bool short __b) { - return __a | ~__b; + return __a | (vector signed short)~__b; } static __inline__ vector signed short __ATTRS_o_ai vec_orc(vector bool short __a, vector signed short __b) { - return __a | ~__b; + return (vector signed short)(__a | (vector bool short)~__b); } static __inline__ vector unsigned short __ATTRS_o_ai @@ -7055,12 +7088,12 @@ static __inline__ vector unsigned short __ATTRS_o_ai vec_orc(vector unsigned short __a, vector bool short __b) { - return __a | ~__b; + return __a | (vector unsigned short)~__b; } static __inline__ vector unsigned short __ATTRS_o_ai vec_orc(vector bool short __a, vector unsigned short __b) { - return __a | ~__b; + return (vector unsigned short)(__a | (vector bool short)~__b); } static __inline__ vector bool short __ATTRS_o_ai @@ -7075,12 +7108,12 @@ static __inline__ vector signed int __ATTRS_o_ai vec_orc(vector signed int __a, vector bool int __b) { - return __a | ~__b; + return __a | (vector signed int)~__b; } static __inline__ vector signed int __ATTRS_o_ai vec_orc(vector bool int __a, vector signed int __b) { - return __a | ~__b; + return (vector signed int)(__a | (vector bool int)~__b); } static __inline__ vector unsigned int __ATTRS_o_ai @@ -7090,12 +7123,12 @@ static __inline__ vector unsigned int __ATTRS_o_ai vec_orc(vector unsigned int __a, vector bool int __b) { - return __a | ~__b; + return __a | (vector unsigned int)~__b; } static __inline__ vector unsigned int __ATTRS_o_ai vec_orc(vector bool int __a, vector unsigned int __b) { - return __a | ~__b; + return (vector unsigned int)(__a | (vector bool int)~__b); } static __inline__ vector bool int __ATTRS_o_ai vec_orc(vector bool int __a, @@ -7105,12 +7138,12 @@ static __inline__ vector float __ATTRS_o_ai vec_orc(vector bool int __a, vector float __b) { - return (vector float)(__a | ~(vector unsigned int)__b); + return (vector float)(__a | ~(vector bool int)__b); } static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a, vector bool int __b) { - return (vector float)((vector unsigned int)__a | ~__b); + return (vector float)((vector bool int)__a | ~__b); } static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a, @@ -7125,12 +7158,12 @@ static __inline__ vector signed long long __ATTRS_o_ai vec_orc(vector signed long long __a, vector bool long long __b) { - return __a | ~__b; + return __a | (vector signed long long)~__b; } static __inline__ vector signed long long __ATTRS_o_ai vec_orc(vector bool long long __a, vector signed long long __b) { - return __a | ~__b; + return (vector signed long long)(__a | (vector bool long long)~__b); } static __inline__ vector unsigned long long __ATTRS_o_ai @@ -7140,12 +7173,12 @@ static __inline__ vector unsigned long long __ATTRS_o_ai vec_orc(vector unsigned long long __a, vector bool long long __b) { - return __a | ~__b; + return __a | (vector unsigned long long)~__b; } static __inline__ vector unsigned long long __ATTRS_o_ai vec_orc(vector bool long long __a, vector unsigned long long __b) { - return __a | ~__b; + return (vector unsigned long long)(__a | (vector bool long long)~__b); } static __inline__ vector bool long long __ATTRS_o_ai @@ -7155,17 +7188,17 @@ static __inline__ vector double __ATTRS_o_ai vec_orc(vector double __a, vector bool long long __b) { - return (vector double)((vector unsigned long long)__a | ~__b); + return (vector double)((vector bool long long)__a | ~__b); } static __inline__ vector double __ATTRS_o_ai vec_orc(vector bool long long __a, vector double __b) { - return (vector double)(__a | ~(vector unsigned long long)__b); + return (vector double)(__a | ~(vector bool long long)__b); } static __inline__ vector double __ATTRS_o_ai vec_orc(vector double __a, vector double __b) { - return (vector double)((vector bool long long)__a | + return (vector double)((vector unsigned long long)__a | ~(vector unsigned long long)__b); } #endif @@ -8276,14 +8309,20 @@ static __inline__ vector unsigned long long __ATTRS_o_ai vec_rl(vector unsigned long long __a, vector unsigned long long __b) { - return __builtin_altivec_vrld(__a, __b); + return (vector unsigned long long)__builtin_altivec_vrld( + (vector long long)__a, __b); } #endif #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ vector signed __int128 __ATTRS_o_ai vec_rl(vector signed __int128 __a, vector unsigned __int128 __b) { - return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector signed __int128)) - __a)); + return (vector signed __int128)(((vector unsigned __int128)__b + << (vector unsigned __int128)__a) | + ((vector unsigned __int128)__b >> + ((__CHAR_BIT__ * + sizeof(vector unsigned __int128)) - + (vector unsigned __int128)__a))); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -8317,7 +8356,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_rlmi(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vrlqmi(__a, __c, __b); + return (vector signed __int128)__builtin_altivec_vrlqmi( + (vector unsigned __int128)__a, (vector unsigned __int128)__c, + (vector unsigned __int128)__b); } #endif @@ -8370,7 +8411,8 @@ __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1, -1, -1, -1, -1, -1, -1, -1); #endif - return __builtin_altivec_vrlqnm(__a, (vector unsigned __int128) MaskAndShift); + return (vector signed __int128)__builtin_altivec_vrlqnm( + (vector unsigned __int128)__a, (vector unsigned __int128)MaskAndShift); } #endif @@ -12070,13 +12112,15 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_subc(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vsubcuq(__a, __b); + return (vector signed __int128)__builtin_altivec_vsubcuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } #endif static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_subc_u128(vector unsigned char __a, vector unsigned char __b) { - return (vector unsigned char)__builtin_altivec_vsubcuq(__a, __b); + return (vector unsigned char)__builtin_altivec_vsubcuq_c( + (vector unsigned char)__a, (vector unsigned char)__b); } #endif // __POWER8_VECTOR__ @@ -12298,7 +12342,7 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_sub_u128(vector unsigned char __a, vector unsigned char __b) { - return __builtin_altivec_vsubuqm(__a, __b); + return (vector unsigned char)__builtin_altivec_vsubuqm(__a, __b); } /* vec_vsubeuqm */ @@ -12307,7 +12351,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vsubeuqm(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vsubeuqm(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vsubeuqm( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -12319,7 +12365,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_sube(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vsubeuqm(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vsubeuqm( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -12332,7 +12380,9 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_sube_u128(vector unsigned char __a, vector unsigned char __b, vector unsigned char __c) { - return (vector unsigned char)__builtin_altivec_vsubeuqm(__a, __b, __c); + return (vector unsigned char)__builtin_altivec_vsubeuqm_c( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } /* vec_vsubcuq */ @@ -12340,7 +12390,8 @@ #ifdef __SIZEOF_INT128__ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vsubcuq(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vsubcuq(__a, __b); + return (vector signed __int128)__builtin_altivec_vsubcuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -12353,7 +12404,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_vsubecuq(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vsubecuq(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vsubecuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -12381,7 +12434,9 @@ static __inline__ vector signed __int128 __ATTRS_o_ai vec_subec(vector signed __int128 __a, vector signed __int128 __b, vector signed __int128 __c) { - return __builtin_altivec_vsubecuq(__a, __b, __c); + return (vector signed __int128)__builtin_altivec_vsubecuq( + (vector unsigned __int128)__a, (vector unsigned __int128)__b, + (vector unsigned __int128)__c); } static __inline__ vector unsigned __int128 __ATTRS_o_ai @@ -12394,7 +12449,9 @@ static __inline__ vector unsigned char __attribute__((__always_inline__)) vec_subec_u128(vector unsigned char __a, vector unsigned char __b, vector unsigned char __c) { - return (vector unsigned char)__builtin_altivec_vsubecuq(__a, __b, __c); + return (vector unsigned char)__builtin_altivec_vsubecuq_c( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } #endif // __POWER8_VECTOR__ @@ -14900,17 +14957,20 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_LT, (vector unsigned __int128)__a, + (vector signed __int128)__b); } static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, + (vector signed __int128)__b); } static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool __int128 __a, vector bool __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_LT, (vector unsigned __int128)__a, + (vector signed __int128)__b); } #endif @@ -15850,17 +15910,20 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ int __ATTRS_o_ai vec_all_ne(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_EQ, (vector unsigned __int128)__a, + __b); } static __inline__ int __ATTRS_o_ai vec_all_ne(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, + (vector signed __int128)__b); } static __inline__ int __ATTRS_o_ai vec_all_ne(vector bool __int128 __a, vector bool __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_EQ, (vector unsigned __int128)__a, + (vector signed __int128)__b); } #endif @@ -16144,17 +16207,20 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ int __ATTRS_o_ai vec_any_eq(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, + (vector unsigned __int128)__a, __b); } static __inline__ int __ATTRS_o_ai vec_any_eq(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, + (vector signed __int128)__b); } static __inline__ int __ATTRS_o_ai vec_any_eq(vector bool __int128 __a, vector bool __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b); + return __builtin_altivec_vcmpequq_p( + __CR6_EQ_REV, (vector unsigned __int128)__a, (vector signed __int128)__b); } #endif @@ -17124,17 +17190,20 @@ #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__) static __inline__ int __ATTRS_o_ai vec_any_ne(vector signed __int128 __a, vector signed __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, + (vector unsigned __int128)__a, __b); } static __inline__ int __ATTRS_o_ai vec_any_ne(vector unsigned __int128 __a, vector unsigned __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b); + return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, + (vector signed __int128)__b); } static __inline__ int __ATTRS_o_ai vec_any_ne(vector bool __int128 __a, vector bool __int128 __b) { - return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b); + return __builtin_altivec_vcmpequq_p( + __CR6_LT_REV, (vector unsigned __int128)__a, (vector signed __int128)__b); } #endif @@ -17297,13 +17366,17 @@ static __inline__ vector bool char __ATTRS_o_ai vec_permxor(vector bool char __a, vector bool char __b, vector bool char __c) { - return __builtin_altivec_crypto_vpermxor(__a, __b, __c); + return (vector bool char)__builtin_altivec_crypto_vpermxor( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } static __inline__ vector signed char __ATTRS_o_ai vec_permxor(vector signed char __a, vector signed char __b, vector signed char __c) { - return __builtin_altivec_crypto_vpermxor(__a, __b, __c); + return (vector signed char)__builtin_altivec_crypto_vpermxor( + (vector unsigned char)__a, (vector unsigned char)__b, + (vector unsigned char)__c); } static __inline__ vector unsigned char __ATTRS_o_ai @@ -17365,7 +17438,7 @@ static __inline__ vector signed char __ATTRS_o_ai vec_vgbbd(vector signed char __a) { - return __builtin_altivec_vgbbd((vector unsigned char)__a); + return (vector signed char)__builtin_altivec_vgbbd((vector unsigned char)__a); } #define vec_pmsum_be __builtin_crypto_vpmsumb @@ -17378,23 +17451,25 @@ static __inline__ vector signed long long __ATTRS_o_ai vec_gbb(vector signed long long __a) { - return __builtin_altivec_vgbbd((vector unsigned char)__a); + return (vector signed long long)__builtin_altivec_vgbbd( + (vector unsigned char)__a); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_gbb(vector unsigned long long __a) { - return __builtin_altivec_vgbbd((vector unsigned char)__a); + return (vector unsigned long long)__builtin_altivec_vgbbd( + (vector unsigned char)__a); } static __inline__ vector long long __ATTRS_o_ai vec_vbpermq(vector signed char __a, vector signed char __b) { - return __builtin_altivec_vbpermq((vector unsigned char)__a, - (vector unsigned char)__b); + return (vector long long)__builtin_altivec_vbpermq((vector unsigned char)__a, + (vector unsigned char)__b); } static __inline__ vector long long __ATTRS_o_ai vec_vbpermq(vector unsigned char __a, vector unsigned char __b) { - return __builtin_altivec_vbpermq(__a, __b); + return (vector long long)__builtin_altivec_vbpermq(__a, __b); } #if defined(__powerpc64__) && defined(__SIZEOF_INT128__) @@ -17406,7 +17481,7 @@ #endif static __inline__ vector unsigned char __ATTRS_o_ai vec_bperm(vector unsigned char __a, vector unsigned char __b) { - return __builtin_altivec_vbpermq(__a, __b); + return (vector unsigned char)__builtin_altivec_vbpermq(__a, __b); } #endif // __POWER8_VECTOR__ #ifdef __POWER9_VECTOR__ @@ -17777,26 +17852,26 @@ #if defined(__POWER10_VECTOR__) && defined(__VSX__) && \ defined(__SIZEOF_INT128__) -/* vect_xl_sext */ +/* vec_xl_sext */ -static __inline__ vector unsigned __int128 __ATTRS_o_ai +static __inline__ vector signed __int128 __ATTRS_o_ai vec_xl_sext(ptrdiff_t __offset, const signed char *__pointer) { - return (vector unsigned __int128)*(__pointer + __offset); + return (vector signed __int128)*(__pointer + __offset); } -static __inline__ vector unsigned __int128 __ATTRS_o_ai +static __inline__ vector signed __int128 __ATTRS_o_ai vec_xl_sext(ptrdiff_t __offset, const signed short *__pointer) { - return (vector unsigned __int128)*(__pointer + __offset); + return (vector signed __int128)*(__pointer + __offset); } -static __inline__ vector unsigned __int128 __ATTRS_o_ai +static __inline__ vector signed __int128 __ATTRS_o_ai vec_xl_sext(ptrdiff_t __offset, const signed int *__pointer) { - return (vector unsigned __int128)*(__pointer + __offset); + return (vector signed __int128)*(__pointer + __offset); } -static __inline__ vector unsigned __int128 __ATTRS_o_ai +static __inline__ vector signed __int128 __ATTRS_o_ai vec_xl_sext(ptrdiff_t __offset, const signed long long *__pointer) { - return (vector unsigned __int128)*(__pointer + __offset); + return (vector signed __int128)*(__pointer + __offset); } /* vec_xl_zext */ @@ -18260,13 +18335,17 @@ #define vec_cntm(__a, __mp) \ _Generic((__a), vector unsigned char \ - : __builtin_altivec_vcntmbb((__a), (unsigned char)(__mp)), \ + : __builtin_altivec_vcntmbb((vector unsigned char)(__a), \ + (unsigned char)(__mp)), \ vector unsigned short \ - : __builtin_altivec_vcntmbh((__a), (unsigned char)(__mp)), \ + : __builtin_altivec_vcntmbh((vector unsigned short)(__a), \ + (unsigned char)(__mp)), \ vector unsigned int \ - : __builtin_altivec_vcntmbw((__a), (unsigned char)(__mp)), \ + : __builtin_altivec_vcntmbw((vector unsigned int)(__a), \ + (unsigned char)(__mp)), \ vector unsigned long long \ - : __builtin_altivec_vcntmbd((__a), (unsigned char)(__mp))) + : __builtin_altivec_vcntmbd((vector unsigned long long)(__a), \ + (unsigned char)(__mp))) /* vec_gen[b|h|w|d|q]m */ @@ -18327,43 +18406,52 @@ #ifdef __SIZEOF_INT128__ #define vec_ternarylogic(__a, __b, __c, __imm) \ _Generic((__a), vector unsigned char \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned char)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned short \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned short)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned int \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned int)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned long long \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned long long)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned __int128 \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm))) + : (vector unsigned __int128)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm))) #else #define vec_ternarylogic(__a, __b, __c, __imm) \ _Generic((__a), vector unsigned char \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned char)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned short \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned short)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned int \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm)), \ + : (vector unsigned int)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm)), \ vector unsigned long long \ - : __builtin_vsx_xxeval((vector unsigned long long)(__a), \ - (vector unsigned long long)(__b), \ - (vector unsigned long long)(__c), (__imm))) + : (vector unsigned long long)__builtin_vsx_xxeval( \ + (vector unsigned long long)(__a), \ + (vector unsigned long long)(__b), \ + (vector unsigned long long)(__c), (__imm))) #endif /* __SIZEOF_INT128__ */ #endif /* __VSX__ */ @@ -18371,14 +18459,16 @@ #ifdef __VSX__ #define vec_genpcvm(__a, __imm) \ - _Generic((__a), vector unsigned char \ - : __builtin_vsx_xxgenpcvbm((__a), (int)(__imm)), \ - vector unsigned short \ - : __builtin_vsx_xxgenpcvhm((__a), (int)(__imm)), \ - vector unsigned int \ - : __builtin_vsx_xxgenpcvwm((__a), (int)(__imm)), \ - vector unsigned long long \ - : __builtin_vsx_xxgenpcvdm((__a), (int)(__imm))) + _Generic( \ + (__a), vector unsigned char \ + : __builtin_vsx_xxgenpcvbm((vector unsigned char)(__a), (int)(__imm)), \ + vector unsigned short \ + : __builtin_vsx_xxgenpcvhm((vector unsigned short)(__a), (int)(__imm)), \ + vector unsigned int \ + : __builtin_vsx_xxgenpcvwm((vector unsigned int)(__a), (int)(__imm)), \ + vector unsigned long long \ + : __builtin_vsx_xxgenpcvdm((vector unsigned long long)(__a), \ + (int)(__imm))) #endif /* __VSX__ */ /* vec_clr_first */ @@ -18386,18 +18476,22 @@ static __inline__ vector signed char __ATTRS_o_ai vec_clr_first(vector signed char __a, unsigned int __n) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vclrrb(__a, __n); + return (vector signed char)__builtin_altivec_vclrrb((vector unsigned char)__a, + __n); #else - return __builtin_altivec_vclrlb( __a, __n); + return (vector signed char)__builtin_altivec_vclrlb((vector unsigned char)__a, + __n); #endif } static __inline__ vector unsigned char __ATTRS_o_ai vec_clr_first(vector unsigned char __a, unsigned int __n) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vclrrb((vector signed char)__a, __n); + return (vector unsigned char)__builtin_altivec_vclrrb( + (vector unsigned char)__a, __n); #else - return __builtin_altivec_vclrlb((vector signed char)__a, __n); + return (vector unsigned char)__builtin_altivec_vclrlb( + (vector unsigned char)__a, __n); #endif } @@ -18406,18 +18500,22 @@ static __inline__ vector signed char __ATTRS_o_ai vec_clr_last(vector signed char __a, unsigned int __n) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vclrlb(__a, __n); + return (vector signed char)__builtin_altivec_vclrlb((vector unsigned char)__a, + __n); #else - return __builtin_altivec_vclrrb( __a, __n); + return (vector signed char)__builtin_altivec_vclrrb((vector unsigned char)__a, + __n); #endif } static __inline__ vector unsigned char __ATTRS_o_ai vec_clr_last(vector unsigned char __a, unsigned int __n) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vclrlb((vector signed char)__a, __n); + return (vector unsigned char)__builtin_altivec_vclrlb( + (vector unsigned char)__a, __n); #else - return __builtin_altivec_vclrrb((vector signed char)__a, __n); + return (vector unsigned char)__builtin_altivec_vclrrb( + (vector unsigned char)__a, __n); #endif } @@ -18469,13 +18567,75 @@ } #endif -/* vec_sldbi */ - -#define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7)) - -/* vec_srdbi */ - -#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7)) +/* vec_sldb */ +#define vec_sldb(__a, __b, __c) \ + _Generic( \ + (__a), vector unsigned char \ + : (vector unsigned char)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed char \ + : (vector signed char)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned short \ + : (vector unsigned short)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed short \ + : (vector signed short)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned int \ + : (vector unsigned int)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed int \ + : (vector signed int)__builtin_altivec_vsldbi((vector unsigned char)__a, \ + (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned long long \ + : (vector unsigned long long)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed long long \ + : (vector signed long long)__builtin_altivec_vsldbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, (__c & 0x7))) + +/* vec_srdb */ +#define vec_srdb(__a, __b, __c) \ + _Generic( \ + (__a), vector unsigned char \ + : (vector unsigned char)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed char \ + : (vector signed char)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned short \ + : (vector unsigned short)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed short \ + : (vector signed short)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned int \ + : (vector unsigned int)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed int \ + : (vector signed int)__builtin_altivec_vsrdbi((vector unsigned char)__a, \ + (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector unsigned long long \ + : (vector unsigned long long)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, \ + (__c & 0x7)), \ + vector signed long long \ + : (vector signed long long)__builtin_altivec_vsrdbi( \ + (vector unsigned char)__a, (vector unsigned char)__b, (__c & 0x7))) /* vec_insertl */ @@ -18704,16 +18864,46 @@ #ifdef __VSX__ /* vec_permx */ - #define vec_permx(__a, __b, __c, __d) \ - __builtin_vsx_xxpermx((__a), (__b), (__c), (__d)) + _Generic( \ + (__a), vector unsigned char \ + : (vector unsigned char)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector signed char \ + : (vector signed char)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector unsigned short \ + : (vector unsigned short)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector signed short \ + : (vector signed short)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector unsigned int \ + : (vector unsigned int)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector signed int \ + : (vector signed int)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector unsigned long long \ + : (vector unsigned long long)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector signed long long \ + : (vector signed long long)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector float \ + : (vector float)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d), \ + vector double \ + : (vector double)__builtin_vsx_xxpermx( \ + (vector unsigned char)__a, (vector unsigned char)__b, __c, __d)) /* vec_blendv */ static __inline__ vector signed char __ATTRS_o_ai vec_blendv(vector signed char __a, vector signed char __b, vector unsigned char __c) { - return __builtin_vsx_xxblendvb(__a, __b, __c); + return (vector signed char)__builtin_vsx_xxblendvb( + (vector unsigned char)__a, (vector unsigned char)__b, __c); } static __inline__ vector unsigned char __ATTRS_o_ai @@ -18725,7 +18915,8 @@ static __inline__ vector signed short __ATTRS_o_ai vec_blendv(vector signed short __a, vector signed short __b, vector unsigned short __c) { - return __builtin_vsx_xxblendvh(__a, __b, __c); + return (vector signed short)__builtin_vsx_xxblendvh( + (vector unsigned short)__a, (vector unsigned short)__b, __c); } static __inline__ vector unsigned short __ATTRS_o_ai @@ -18737,7 +18928,8 @@ static __inline__ vector signed int __ATTRS_o_ai vec_blendv(vector signed int __a, vector signed int __b, vector unsigned int __c) { - return __builtin_vsx_xxblendvw(__a, __b, __c); + return (vector signed int)__builtin_vsx_xxblendvw( + (vector unsigned int)__a, (vector unsigned int)__b, __c); } static __inline__ vector unsigned int __ATTRS_o_ai @@ -18749,33 +18941,68 @@ static __inline__ vector signed long long __ATTRS_o_ai vec_blendv(vector signed long long __a, vector signed long long __b, vector unsigned long long __c) { - return __builtin_vsx_xxblendvd(__a, __b, __c); + return (vector signed long long)__builtin_vsx_xxblendvd( + (vector unsigned long long)__a, (vector unsigned long long)__b, __c); } static __inline__ vector unsigned long long __ATTRS_o_ai vec_blendv(vector unsigned long long __a, vector unsigned long long __b, vector unsigned long long __c) { - return __builtin_vsx_xxblendvd(__a, __b, __c); + return (vector unsigned long long)__builtin_vsx_xxblendvd(__a, __b, __c); } static __inline__ vector float __ATTRS_o_ai vec_blendv(vector float __a, vector float __b, vector unsigned int __c) { - return __builtin_vsx_xxblendvw(__a, __b, __c); + return (vector float)__builtin_vsx_xxblendvw((vector unsigned int)__a, + (vector unsigned int)__b, __c); } static __inline__ vector double __ATTRS_o_ai vec_blendv(vector double __a, vector double __b, vector unsigned long long __c) { - return __builtin_vsx_xxblendvd(__a, __b, __c); + return (vector double)__builtin_vsx_xxblendvd( + (vector unsigned long long)__a, (vector unsigned long long)__b, __c); } -/* vec_replace_elt */ - -#define vec_replace_elt __builtin_altivec_vec_replace_elt - -/* vec_replace_unaligned */ +#define vec_replace_unaligned(__a, __b, __c) \ + _Generic((__a), vector signed int \ + : (vector signed int)__builtin_altivec_vinsw( \ + (vector unsigned char)__a, (unsigned int)__b, __c), \ + vector unsigned int \ + : (vector unsigned int)__builtin_altivec_vinsw( \ + (vector unsigned char)__a, (unsigned int)__b, __c), \ + vector unsigned long long \ + : (vector unsigned long long)__builtin_altivec_vinsd( \ + (vector unsigned char)__a, (unsigned long long)__b, __c), \ + vector signed long long \ + : (vector signed long long)__builtin_altivec_vinsd( \ + (vector unsigned char)__a, (unsigned long long)__b, __c), \ + vector float \ + : (vector float)__builtin_altivec_vinsw((vector unsigned char)__a, \ + (unsigned int)__b, __c), \ + vector double \ + : (vector double)__builtin_altivec_vinsd( \ + (vector unsigned char)__a, (unsigned long long)__b, __c)) -#define vec_replace_unaligned __builtin_altivec_vec_replace_unaligned +#define vec_replace_elt(__a, __b, __c) \ + _Generic((__a), vector signed int \ + : (vector signed int)__builtin_altivec_vinsw_elt( \ + (vector unsigned char)__a, (unsigned int)__b, __c), \ + vector unsigned int \ + : (vector unsigned int)__builtin_altivec_vinsw_elt( \ + (vector unsigned char)__a, (unsigned int)__b, __c), \ + vector unsigned long long \ + : (vector unsigned long long)__builtin_altivec_vinsd_elt( \ + (vector unsigned char)__a, (unsigned long long)__b, __c), \ + vector signed long long \ + : (vector signed long long)__builtin_altivec_vinsd_elt( \ + (vector unsigned char)__a, (unsigned long long)__b, __c), \ + vector float \ + : (vector float)__builtin_altivec_vinsw_elt( \ + (vector unsigned char)__a, (unsigned int)__b, __c), \ + vector double \ + : (vector double)__builtin_altivec_vinsd_elt( \ + (vector unsigned char)__a, (unsigned long long)__b, __c)) /* vec_splati */ @@ -18852,27 +19079,33 @@ static __inline__ vector unsigned char __ATTRS_o_ai vec_stril(vector unsigned char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribr((vector signed char)__a); + return (vector unsigned char)__builtin_altivec_vstribr( + (vector unsigned char)__a); #else - return __builtin_altivec_vstribl((vector signed char)__a); + return (vector unsigned char)__builtin_altivec_vstribl( + (vector unsigned char)__a); #endif } static __inline__ vector signed char __ATTRS_o_ai vec_stril(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribr(__a); + return (vector signed char)__builtin_altivec_vstribr( + (vector unsigned char)__a); #else - return __builtin_altivec_vstribl(__a); + return (vector signed char)__builtin_altivec_vstribl( + (vector unsigned char)__a); #endif } static __inline__ vector unsigned short __ATTRS_o_ai vec_stril(vector unsigned short __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstrihr((vector signed short)__a); + return (vector unsigned short)__builtin_altivec_vstrihr( + (vector signed short)__a); #else - return __builtin_altivec_vstrihl((vector signed short)__a); + return (vector unsigned short)__builtin_altivec_vstrihl( + (vector signed short)__a); #endif } @@ -18889,17 +19122,17 @@ static __inline__ int __ATTRS_o_ai vec_stril_p(vector unsigned char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribr_p(__CR6_EQ, (vector signed char)__a); + return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a); #else - return __builtin_altivec_vstribl_p(__CR6_EQ, (vector signed char)__a); + return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a); #endif } static __inline__ int __ATTRS_o_ai vec_stril_p(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribr_p(__CR6_EQ, __a); + return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a); #else - return __builtin_altivec_vstribl_p(__CR6_EQ, __a); + return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a); #endif } @@ -18924,27 +19157,33 @@ static __inline__ vector unsigned char __ATTRS_o_ai vec_strir(vector unsigned char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribl((vector signed char)__a); + return (vector unsigned char)__builtin_altivec_vstribl( + (vector unsigned char)__a); #else - return __builtin_altivec_vstribr((vector signed char)__a); + return (vector unsigned char)__builtin_altivec_vstribr( + (vector unsigned char)__a); #endif } static __inline__ vector signed char __ATTRS_o_ai vec_strir(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribl(__a); + return (vector signed char)__builtin_altivec_vstribl( + (vector unsigned char)__a); #else - return __builtin_altivec_vstribr(__a); + return (vector signed char)__builtin_altivec_vstribr( + (vector unsigned char)__a); #endif } static __inline__ vector unsigned short __ATTRS_o_ai vec_strir(vector unsigned short __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstrihl((vector signed short)__a); + return (vector unsigned short)__builtin_altivec_vstrihl( + (vector signed short)__a); #else - return __builtin_altivec_vstrihr((vector signed short)__a); + return (vector unsigned short)__builtin_altivec_vstrihr( + (vector signed short)__a); #endif } @@ -18961,17 +19200,17 @@ static __inline__ int __ATTRS_o_ai vec_strir_p(vector unsigned char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribl_p(__CR6_EQ, (vector signed char)__a); + return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a); #else - return __builtin_altivec_vstribr_p(__CR6_EQ, (vector signed char)__a); + return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a); #endif } static __inline__ int __ATTRS_o_ai vec_strir_p(vector signed char __a) { #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribl_p(__CR6_EQ, __a); + return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a); #else - return __builtin_altivec_vstribr_p(__CR6_EQ, __a); + return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a); #endif } diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3250,17 +3250,6 @@ isa(Arg->IgnoreParens())); } -static bool isEltOfVectorTy(ASTContext &Context, CallExpr *Call, Sema &S, - QualType VectorTy, QualType EltTy) { - QualType VectorEltTy = VectorTy->castAs()->getElementType(); - if (!Context.hasSameType(VectorEltTy, EltTy)) { - S.Diag(Call->getBeginLoc(), diag::err_typecheck_call_different_arg_types) - << Call->getSourceRange() << VectorEltTy << EltTy; - return false; - } - return true; -} - static bool isValidBPFPreserveTypeInfoArg(Expr *Arg) { QualType ArgType = Arg->getType(); if (ArgType->getAsPlaceholderType()) @@ -4082,14 +4071,6 @@ diag::err_ppc_builtin_only_on_arch, "10"); case PPC::BI__builtin_altivec_vgnb: return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7); - case PPC::BI__builtin_altivec_vec_replace_elt: - case PPC::BI__builtin_altivec_vec_replace_unaligned: { - QualType VecTy = TheCall->getArg(0)->getType(); - QualType EltTy = TheCall->getArg(1)->getType(); - unsigned Width = Context.getIntWidth(EltTy); - return SemaBuiltinConstantArgRange(TheCall, 2, 0, Width == 32 ? 12 : 8) || - !isEltOfVectorTy(Context, TheCall, *this, VecTy, EltTy); - } case PPC::BI__builtin_vsx_xxeval: return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255); case PPC::BI__builtin_altivec_vsldbi: diff --git a/clang/test/CodeGen/PowerPC/altivec-ct.c b/clang/test/CodeGen/PowerPC/altivec-ct.c --- a/clang/test/CodeGen/PowerPC/altivec-ct.c +++ b/clang/test/CodeGen/PowerPC/altivec-ct.c @@ -19,12 +19,12 @@ #ifdef __VSX__ // VSX-LABEL: test3 -vector double test3(vector signed long long x) { +vector float test3(vector signed long long x) { return vec_ctf(x, 0); } // VSX-LABEL: test4 -vector double test4(vector unsigned long long x) { +vector float test4(vector unsigned long long x) { return vec_ctf(x, 0); } #endif diff --git a/clang/test/CodeGen/PowerPC/altivec-dss.c b/clang/test/CodeGen/PowerPC/altivec-dss.c --- a/clang/test/CodeGen/PowerPC/altivec-dss.c +++ b/clang/test/CodeGen/PowerPC/altivec-dss.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple powerpc-linux-gnu -S -O0 -o - %s -target-feature +altivec | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-linux-gnu -S -O0 -o - %s -target-feature +altivec | FileCheck %s // REQUIRES: powerpc-registered-target diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c b/clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c @@ -1,10 +1,12 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ -// RUN: -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec \ +// RUN: -target-feature +power8-vector -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s #include vector signed long long vsll1, vsll2, vsll3; +vector unsigned long long vull1, vull2, vull3; vector signed char vsc; +vector unsigned char vuc; vector bool long long vbll; void dummy(); @@ -157,7 +159,7 @@ // CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdss dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_vpkudus(vsll1, vsll2); + vec_vpkudus(vull1, vull2); // CHECK: call <4 x i32> @llvm.ppc.altivec.vpkudus dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() @@ -165,7 +167,7 @@ // CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdus dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_rl(vsll1, vsll2); + vec_rl(vull1, vull2); // CHECK: call <2 x i64> @llvm.ppc.altivec.vrld dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() @@ -176,7 +178,7 @@ // CHECK: or <2 x i64> dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_sl(vsll1, vsll2); + vec_sl(vull1, vull2); // CHECK: shl <2 x i64> dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() @@ -188,7 +190,7 @@ // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_sll(vsll1, vsll2); + vec_sll(vsll1, vuc); // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() @@ -200,15 +202,15 @@ // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_sr(vsll1, vsll2); + vec_sr(vull1, vull2); // CHECK: lshr <2 x i64> dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_sra(vsll1, vsll2); + vec_sra(vsll1, vull2); // CHECK: ashr <2 x i64> dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() - vec_srl(vsll1, vsc); + vec_srl(vsll1, vuc); // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr dummy(); // CHECK: call void bitcast (void (...)* @dummy to void ()*)() diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c b/clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c @@ -1,9 +1,9 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -triple powerpc64le-unknown-unknown \ // RUN: -target-feature +crypto -target-feature +power8-vector \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -triple powerpc64-unknown-unknown \ // RUN: -target-feature +crypto -target-feature +power8-vector \ // RUN: -emit-llvm %s -o - | FileCheck %s #include @@ -78,36 +78,6 @@ // CHECK: @llvm.ppc.altivec.crypto.vpermxor } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vpermxorh -vector unsigned short test_vpermxorh(void) -{ - vector unsigned short a = H_INIT1 - vector unsigned short b = H_INIT2 - vector unsigned short c = H_INIT2 - return __builtin_altivec_crypto_vpermxor(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor -} - -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vpermxorw -vector unsigned int test_vpermxorw(void) -{ - vector unsigned int a = W_INIT1 - vector unsigned int b = W_INIT2 - vector unsigned int c = W_INIT2 - return __builtin_altivec_crypto_vpermxor(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor -} - -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vpermxord -vector unsigned long long test_vpermxord(void) -{ - vector unsigned long long a = D_INIT1 - vector unsigned long long b = D_INIT2 - vector unsigned long long c = D_INIT2 - return __builtin_altivec_crypto_vpermxor(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor -} - // CHECK-LABEL: test_vpermxorbc vector bool char test_vpermxorbc(vector bool char a, vector bool char b, @@ -132,54 +102,6 @@ // CHECK: @llvm.ppc.altivec.crypto.vpermxor } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorb_be -vector unsigned char test_vpermxorb_be(vector unsigned char a, - vector unsigned char b, - vector unsigned char c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vpermxorh_be -vector unsigned short test_vpermxorh_be(vector unsigned short a, - vector unsigned short b, - vector unsigned short c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vpermxorw_be -vector unsigned int test_vpermxorw_be(vector unsigned int a, - vector unsigned int b, - vector unsigned int c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vpermxord_be -vector unsigned long long test_vpermxord_be(vector unsigned long long a, - vector unsigned long long b, - vector unsigned long long c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorbc_be -vector bool char test_vpermxorbc_be(vector bool char a, - vector bool char b, - vector bool char c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorsc_be -vector signed char test_vpermxorsc_be(vector signed char a, - vector signed char b, - vector signed char c) { - return __builtin_altivec_crypto_vpermxor_be(a, b, c); -// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be -} - // CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxoruc_be vector unsigned char test_vpermxoruc_be(vector unsigned char a, vector unsigned char b, @@ -344,24 +266,6 @@ // CHECK: @llvm.ppc.altivec.crypto.vcipherlast } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipher_e -vector unsigned long long test_vncipher_e(void) -{ - vector unsigned long long a = D_INIT1 - vector unsigned long long b = D_INIT2 - return __builtin_crypto_vncipher(a, b); -// CHECK: @llvm.ppc.altivec.crypto.vncipher -} - -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipherlast_e -vector unsigned long long test_vncipherlast_e(void) -{ - vector unsigned long long a = D_INIT1 - vector unsigned long long b = D_INIT2 - return __builtin_crypto_vncipherlast(a, b); -// CHECK: @llvm.ppc.altivec.crypto.vncipherlast -} - // CHECK-LABEL: define{{.*}} <4 x i32> @test_vshasigmaw_e vector unsigned int test_vshasigmaw_e(void) { @@ -379,45 +283,45 @@ } // CHECK-LABEL: @test_vec_sbox_be -vector unsigned char test_vec_sbox_be(void) +vector unsigned long long test_vec_sbox_be(void) { - vector unsigned char a = B_INIT1 + vector unsigned long long a = D_INIT1 return vec_sbox_be(a); // CHECK: @llvm.ppc.altivec.crypto.vsbox } // CHECK-LABEL: @test_vec_cipher_be -vector unsigned char test_vec_cipher_be(void) +vector unsigned long long test_vec_cipher_be(void) { - vector unsigned char a = B_INIT1 - vector unsigned char b = B_INIT2 + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 return vec_cipher_be(a, b); // CHECK: @llvm.ppc.altivec.crypto.vcipher } // CHECK-LABEL: @test_vec_cipherlast_be -vector unsigned char test_vec_cipherlast_be(void) +vector unsigned long long test_vec_cipherlast_be(void) { - vector unsigned char a = B_INIT1 - vector unsigned char b = B_INIT2 + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 return vec_cipherlast_be(a, b); // CHECK: @llvm.ppc.altivec.crypto.vcipherlast } // CHECK-LABEL: @test_vec_ncipher_be -vector unsigned char test_vec_ncipher_be(void) +vector unsigned long long test_vec_ncipher_be(void) { - vector unsigned char a = B_INIT1 - vector unsigned char b = B_INIT2 + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 return vec_ncipher_be(a, b); // CHECK: @llvm.ppc.altivec.crypto.vncipher } // CHECK-LABEL: @test_vec_ncipherlast_be -vector unsigned char test_vec_ncipherlast_be(void) +vector unsigned long long test_vec_ncipherlast_be(void) { - vector unsigned char a = B_INIT1 - vector unsigned char b = B_INIT2 + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 return vec_ncipherlast_be(a, b); // CHECK: @llvm.ppc.altivec.crypto.vncipherlast } @@ -439,7 +343,7 @@ } // CHECK-LABEL: @test_vec_pmsum_beb -vector unsigned short test_vec_pmsum_beb(void) +vector unsigned char test_vec_pmsum_beb(void) { vector unsigned char a = B_INIT1 vector unsigned char b = B_INIT2 @@ -448,7 +352,7 @@ } // CHECK-LABEL: @test_vec_pmsum_beh -vector unsigned int test_vec_pmsum_beh(void) +vector unsigned short test_vec_pmsum_beh(void) { vector unsigned short a = H_INIT1 vector unsigned short b = H_INIT2 @@ -457,7 +361,7 @@ } // CHECK-LABEL: @test_vec_pmsum_bew -vector unsigned long long test_vec_pmsum_bew(void) +vector unsigned int test_vec_pmsum_bew(void) { vector unsigned int a = W_INIT1 vector unsigned int b = W_INIT2 @@ -466,7 +370,7 @@ } // CHECK-LABEL: @test_vec_pmsum_bed -vector unsigned __int128 test_vec_pmsum_bed(void) +vector unsigned long long test_vec_pmsum_bed(void) { vector unsigned long long a = D_INIT1 vector unsigned long long b = D_INIT2 diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-error.c b/clang/test/CodeGen/PowerPC/builtins-ppc-error.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-error.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-error.c @@ -10,24 +10,21 @@ // RUN: -flax-vector-conversions=integer \ // RUN: -Wall -Werror -verify %s -// FIXME: Fix so this test also passes under -// -flax-vector-conversions=none (this last test exists to produce an error if -// we change the default to that without fixing ). -// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \ -// RUN: -triple powerpc64-unknown-unknown -fsyntax-only \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power9-vector \ +// RUN: -triple powerpc64-unknown-unknown -fsyntax-only \ // RUN: -Wall -Werror -verify %s #include extern vector signed int vsi; -extern vector signed int vui; +extern vector unsigned int vui; extern vector float vf; extern vector unsigned char vuc; extern vector signed __int128 vsllli; void testInsertWord(void) { int index = 5; - vector unsigned char v1 = vec_insert4b(vsi, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}} + vector unsigned char v1 = vec_insert4b(vui, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}} vector unsigned long long v2 = vec_extract4b(vuc, index); // expected-error {{argument to '__builtin_vsx_extractuword' must be a constant integer}} } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-int128.c b/clang/test/CodeGen/PowerPC/builtins-ppc-int128.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-int128.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-int128.c @@ -1,8 +1,8 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64-unknown-unknown -target-cpu pwr8 \ // RUN: -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s -// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64le-unknown-unknown -target-cpu pwr8 \ // RUN: -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | \ // RUN: FileCheck %s -check-prefix=CHECK-LE diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c b/clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c @@ -1,15 +1,15 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=BE-PWR8 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=LE-PWR8 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE-PWR9 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=LE-PWR9 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE32-PWR9 #include diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector-error.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector-error.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector-error.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector-error.c @@ -1,11 +1,11 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-unknown -target-cpu pwr10 \ // RUN: -fsyntax-only -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ // RUN: -fsyntax-only -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-aix -target-cpu pwr10 \ // RUN: -fsyntax-only -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-aix -target-cpu pwr10 \ // RUN: -fsyntax-only -Wall -Werror -verify %s #include diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c @@ -1,8 +1,8 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK @@ -1015,123 +1015,323 @@ return vec_blendv(vda, vdb, vullc); } +// CHECK-BE-LABEL: @test_vec_replace_elt_si( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 0) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_si( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 12) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] +// vector signed int test_vec_replace_elt_si(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 0 - // CHECK-BE-NEXT: ret <4 x i32> - // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 12 - // CHECK-LE-NEXT: ret <4 x i32> return vec_replace_elt(vsia, sia, 0); } +// CHECK-BE-LABEL: @test_vec_replace_elt_ui( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 4) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_ui( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] +// vector unsigned int test_vec_replace_elt_ui(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4 - // CHECK-BE-NEXT: ret <4 x i32> - // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8 - // CHECK-LE-NEXT: ret <4 x i32> return vec_replace_elt(vuia, uia, 1); } +// CHECK-BE-LABEL: @test_vec_replace_elt_f( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 8) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> +// CHECK-BE-NEXT: ret <4 x float> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_f( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 4) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> +// CHECK-LE-NEXT: ret <4 x float> [[TMP6]] +// vector float test_vec_replace_elt_f(void) { - // CHECK-BE: bitcast float %{{.+}} to i32 - // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8 - // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float> - // CHECK-BE-NEXT: ret <4 x float> - // CHECK-LE: bitcast float %{{.+}} to i32 - // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4 - // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float> - // CHECK-LE-NEXT: ret <4 x float> return vec_replace_elt(vfa, fa, 2); } +// CHECK-BE-LABEL: @test_vec_replace_elt_sll( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_sll( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] +// vector signed long long test_vec_replace_elt_sll(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0 - // CHECK-BE-NEXT: ret <2 x i64> - // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8 - // CHECK-LE-NEXT: ret <2 x i64> return vec_replace_elt(vslla, llb, 0); } +// CHECK-BE-LABEL: @test_vec_replace_elt_ull( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_ull( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] +// vector unsigned long long test_vec_replace_elt_ull(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0 - // CHECK-BE-NEXT: ret <2 x i64> - // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8 - // CHECK-LE-NEXT: ret <2 x i64> return vec_replace_elt(vulla, ulla, 0); } +// CHECK-BE-LABEL: @test_vec_replace_elt_d( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> +// CHECK-BE-NEXT: ret <2 x double> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_elt_d( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 0) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> +// CHECK-LE-NEXT: ret <2 x double> [[TMP6]] +// vector double test_vec_replace_elt_d(void) { - // CHECK-BE: bitcast double %{{.+}} to i64 - // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8 - // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double> - // CHECK-BE-NEXT: ret <2 x double> - // CHECK-LE: bitcast double %{{.+}} to i64 - // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0 - // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double> - // CHECK-LE-NEXT: ret <2 x double> return vec_replace_elt(vda, da, 1); } -vector unsigned char test_vec_replace_unaligned_si(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 6 - // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 6 - // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_si( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_si( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] +// +vector signed int test_vec_replace_unaligned_si(void) { return vec_replace_unaligned(vsia, sia, 6); } -vector unsigned char test_vec_replace_unaligned_ui(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8 - // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4 - // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_ui( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_ui( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> +// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]] +// +vector unsigned int test_vec_replace_unaligned_ui(void) { return vec_replace_unaligned(vuia, uia, 8); } -vector unsigned char test_vec_replace_unaligned_f(void) { - // CHECK-BE: bitcast float %{{.+}} to i32 - // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 12 - // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: bitcast float %{{.+}} to i32 - // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 0 - // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_f( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> +// CHECK-BE-NEXT: ret <4 x float> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_f( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> +// CHECK-LE-NEXT: ret <4 x float> [[TMP6]] +// +vector float test_vec_replace_unaligned_f(void) { return vec_replace_unaligned(vfa, fa, 12); } -vector unsigned char test_vec_replace_unaligned_sll(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 6 - // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 2 - // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_sll( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_sll( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] +// +vector signed long long test_vec_replace_unaligned_sll(void) { return vec_replace_unaligned(vslla, llb, 6); } -vector unsigned char test_vec_replace_unaligned_ull(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 7 - // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 1 - // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_ull( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_ull( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> +// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]] +// +vector unsigned long long test_vec_replace_unaligned_ull(void) { return vec_replace_unaligned(vulla, ulla, 7); } -vector unsigned char test_vec_replace_unaligned_d(void) { - // CHECK-BE: bitcast double %{{.+}} to i64 - // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8 - // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: bitcast double %{{.+}} to i64 - // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0 - // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8> - // CHECK-LE-NEXT: ret <16 x i8> +// CHECK-BE-LABEL: @test_vec_replace_unaligned_d( +// CHECK-BE-NEXT: entry: +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 +// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) +// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> +// CHECK-BE-NEXT: ret <2 x double> [[TMP6]] +// +// CHECK-LE-LABEL: @test_vec_replace_unaligned_d( +// CHECK-LE-NEXT: entry: +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 +// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) +// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> +// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> +// CHECK-LE-NEXT: ret <2 x double> [[TMP6]] +// +vector double test_vec_replace_unaligned_d(void) { return vec_replace_unaligned(vda, da, 8); } @@ -1955,7 +2155,7 @@ // CHECK-NEXT: lshr <1 x i128> // CHECK-NEXT: or <1 x i128> // CHECK-NEXT: ret <1 x i128> - return vec_rl(vsi128a, vsi128b); + return vec_rl(vsi128a, vui128b); } vector unsigned __int128 test_vec_rl_u128(void) { diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c @@ -1,6 +1,6 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -target-feature +altivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -target-feature +altivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC // Added -target-feature +vsx above to avoid errors about "vector double" and to // generate the correct errors for functions that are only overloaded with VSX @@ -240,7 +240,7 @@ // CHECK-LE: bitcast <4 x i32> [[T3]] to <16 x i8> // CHECK-PPC: error: assigning to - res_vsc = vec_eqv(vbc, vbc); + res_vbc = vec_eqv(vbc, vbc); // CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32> // CHECK: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32> // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]]) @@ -273,7 +273,7 @@ // CHECK-LE: bitcast <4 x i32> [[T3]] to <8 x i16> // CHECK-PPC: error: assigning to - res_vss = vec_eqv(vbs, vbs); + res_vbs = vec_eqv(vbs, vbs); // CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32> // CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32> // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]]) @@ -300,7 +300,7 @@ // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}}) // CHECK-PPC: error: assigning to - res_vsi = vec_eqv(vbi, vbi); + res_vbi = vec_eqv(vbi, vbi); // CHECK: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}}) // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}}) // CHECK-PPC: error: assigning to @@ -321,7 +321,7 @@ // CHECK-LE: bitcast <4 x i32> [[T3]] to <2 x i64> // CHECK-PPC: error: assigning to - res_vsll = vec_eqv(vbll, vbll); + res_vbll = vec_eqv(vbll, vbll); // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32> // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32> // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]]) @@ -847,7 +847,7 @@ // CHECK-LE: xor <16 x i8> [[T1]], // CHECK-PPC: error: call to undeclared function 'vec_nand' - res_vsc = vec_nand(vbc, vbc); + res_vbc = vec_nand(vbc, vbc); // CHECK: [[T1:%.+]] = and <16 x i8> // CHECK: xor <16 x i8> [[T1]], // CHECK-LE: [[T1:%.+]] = and <16 x i8> @@ -865,7 +865,7 @@ // CHECK-LE: [[T1:%.+]] = and <8 x i16> // CHECK-LE: xor <8 x i16> [[T1]], - res_vss = vec_nand(vbs, vbs); + res_vbs = vec_nand(vbs, vbs); // CHECK: [[T1:%.+]] = and <8 x i16> // CHECK: xor <8 x i16> [[T1]], // CHECK-LE: [[T1:%.+]] = and <8 x i16> @@ -883,7 +883,7 @@ // CHECK-LE: [[T1:%.+]] = and <4 x i32> // CHECK-LE: xor <4 x i32> [[T1]], - res_vsi = vec_nand(vbi, vbi); + res_vbi = vec_nand(vbi, vbi); // CHECK: [[T1:%.+]] = and <4 x i32> // CHECK: xor <4 x i32> [[T1]], // CHECK-LE: [[T1:%.+]] = and <4 x i32> @@ -907,7 +907,7 @@ // CHECK-LE: [[T1:%.+]] = and <2 x i64> // CHECK-LE: xor <2 x i64> [[T1]], - res_vsll = vec_nand(vbll, vbll); + res_vbll = vec_nand(vbll, vbll); // CHECK: [[T1:%.+]] = and <2 x i64> // CHECK: xor <2 x i64> [[T1]], // CHECK-LE: [[T1:%.+]] = and <2 x i64> @@ -1163,7 +1163,7 @@ // CHECK: llvm.ppc.altivec.vbpermq // CHECK-LE: llvm.ppc.altivec.vbpermq - res_vull = vec_vbpermq(vuc, vuc); + res_vsll = vec_vbpermq(vuc, vuc); // CHECK: llvm.ppc.altivec.vbpermq // CHECK-LE: llvm.ppc.altivec.vbpermq // CHECK-PPC: error: call to undeclared function 'vec_vbpermq' @@ -1195,7 +1195,7 @@ // CHECK: llvm.ppc.altivec.vbpermq // CHECK-LE: llvm.ppc.altivec.vbpermq - res_vull = vec_bperm(vuc, vuc); + res_vuc = vec_bperm(vuc, vuc); // CHECK: llvm.ppc.altivec.vbpermq // CHECK-LE: llvm.ppc.altivec.vbpermq diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c @@ -9,9 +9,7 @@ // RUN: -flax-vector-conversions=integer \ // RUN: -o - | FileCheck %s -// FIXME: This last test is intended to fail if the default is changed to -// -flax-vector-conversions=none and isn't fixed first. -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \ // RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefix=CHECK-BE diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c @@ -0,0 +1,84 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ +// RUN: -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s +// +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ +// RUN: -triple powerpc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s + +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ +// RUN: -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s +#include + +// CHECK-LABEL: @test_vaddeuqm_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP4]] +vector unsigned char test_vaddeuqm_c(vector unsigned char a, vector unsigned char b, + vector unsigned char c) { + return __builtin_altivec_vaddeuqm_c(a, b, c); +} + +// CHECK-LABEL: @test_vaddcuq_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP3]] +vector unsigned char test_vaddcuq_c(vector unsigned char a, vector unsigned char b) { + return __builtin_altivec_vaddcuq_c(a, b); +} + +// CHECK-LABEL: @test_vaddecuq_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP4]] +vector unsigned char test_vaddecuq_c(vector unsigned char a, vector unsigned char b, + vector unsigned char c) { + return __builtin_altivec_vaddecuq_c(a, b, c); +} + +// CHECK-LABEL: @test_vsubeuqm_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP4]] +vector unsigned char test_vsubeuqm_c(vector unsigned char a, vector unsigned char b, + vector unsigned char c) { + return __builtin_altivec_vsubeuqm_c(a, b, c); +} + +// CHECK-LABEL: @test_vsubcuq_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP3]] +vector unsigned char test_vsubcuq_c(vector unsigned char a, vector unsigned char b) { + return __builtin_altivec_vsubcuq_c(a, b); +} + +// CHECK-LABEL: @test_vsubecuq_c( +// CHECK: entry: +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128> +// CHECK-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8> +// CHECK-NEXT: ret <16 x i8> [[TMP4]] +vector unsigned char test_vsubecuq_c(vector unsigned char a, vector unsigned char b, + vector unsigned char c) { + return __builtin_altivec_vsubecuq_c(a, b, c); +} diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c @@ -1,12 +1,12 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \ // RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck \ // RUN: %s -check-prefix=CHECK-LE -// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \ // RUN: -triple powerpc64-aix-unknown -emit-llvm %s -o - | FileCheck \ // RUN: %s -check-prefix=CHECK-AIX -// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \ // RUN: -triple powerpc-aix-unknown -emit-llvm %s -o - | FileCheck \ // RUN: %s -check-prefix=CHECK-AIX #include diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c @@ -1,8 +1,8 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ // RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \ // RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=CHECK-LE diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c b/clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c @@ -1,9 +1,17 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -target-feature +vsx -target-cpu pwr10 \ -// RUN: -triple powerpc64le-unknown-unknown -fsyntax-only %s -verify -// RUN: %clang_cc1 -target-feature +vsx -target-cpu pwr10 \ -// RUN: -triple powerpc64-unknown-unknown -fsyntax-only %s -verify +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_SI +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_F +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_SLL +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_D +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_UNALIGNED_UI +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \ +// RUN: -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify #include @@ -20,62 +28,33 @@ float fa; double da; +#ifdef __TEST_ELT_SI vector signed int test_vec_replace_elt_si(void) { - return vec_replace_elt(vsia, sia, 13); // expected-error {{argument value 13 is outside the valid range [0, 12]}} -} - -vector unsigned int test_vec_replace_elt_ui(void) { - return vec_replace_elt(vuia, sia, 1); // expected-error {{arguments are of different types ('unsigned int' vs 'int')}} + return vec_replace_elt(vsia, sia, 4); // expected-error {{element number 4 is outside of the valid range [0, 3]}} } +#elif defined(__TEST_ELT_F) vector float test_vec_replace_elt_f(void) { - return vec_replace_elt(vfa, fa, 20); // expected-error {{argument value 20 is outside the valid range [0, 12]}} -} - -vector float test_vec_replace_elt_f_2(void) { - return vec_replace_elt(vfa, da, 0); // expected-error {{arguments are of different types ('float' vs 'double')}} + return vec_replace_elt(vfa, fa, 10); // expected-error {{element number 10 is outside of the valid range [0, 3]}} } +#elif defined(__TEST_ELT_SLL) vector signed long long test_vec_replace_elt_sll(void) { - return vec_replace_elt(vslla, slla, 9); // expected-error {{argument value 9 is outside the valid range [0, 8]}} -} - -vector unsigned long long test_vec_replace_elt_ull(void) { - return vec_replace_elt(vulla, vda, 0); // expected-error {{arguments are of different types ('unsigned long long' vs '__vector double' (vector of 2 'double' values))}} -} - -vector unsigned long long test_vec_replace_elt_ull_2(void) { - return vec_replace_elt(vulla, vulla, vsia); // expected-error {{argument to '__builtin_altivec_vec_replace_elt' must be a constant integer}} + return vec_replace_elt(vslla, slla, 2); // expected-error {{element number 2 is outside of the valid range [0, 1]}} } +#elif defined(__TEST_ELT_D) vector double test_vec_replace_elt_d(void) { - return vec_replace_elt(vda, da, 33); // expected-error {{argument value 33 is outside the valid range [0, 8]}} -} - -vector unsigned char test_vec_replace_unaligned_si(void) { - return vec_replace_unaligned(vsia, da, 6); // expected-error {{arguments are of different types ('int' vs 'double')}} -} - -vector unsigned char test_vec_replace_unaligned_ui(void) { - return vec_replace_unaligned(vuia, uia, 14); // expected-error {{argument value 14 is outside the valid range [0, 12]}} -} - -vector unsigned char test_vec_replace_unaligned_f(void) { - return vec_replace_unaligned(vfa, fa, 19); // expected-error {{argument value 19 is outside the valid range [0, 12]}} -} - -vector unsigned char test_vec_replace_unaligned_sll(void) { - return vec_replace_unaligned(vslla, fa, 0); // expected-error {{arguments are of different types ('long long' vs 'float')}} -} - -vector unsigned char test_vec_replace_unaligned_ull(void) { - return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{argument value 12 is outside the valid range [0, 8]}} + return vec_replace_elt(vda, da, 3); // expected-error {{element number 3 is outside of the valid range [0, 1]}} } -vector unsigned char test_vec_replace_unaligned_d(void) { - return vec_replace_unaligned(vda, fa, 8); // expected-error {{arguments are of different types ('double' vs 'float')}} +#elif defined(__TEST_UNALIGNED_UI) +vector unsigned int test_vec_replace_unaligned_ui(void) { + return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}} } -vector unsigned char test_vec_replace_unaligned_d_2(void) { - return vec_replace_unaligned(vda, vda, da); // expected-error {{argument to '__builtin_altivec_vec_replace_unaligned' must be a constant integer}} +#else +vector unsigned long long test_vec_replace_unaligned_ull(void) { + return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}} } +#endif diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c @@ -1,6 +1,6 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE #include vector bool char vbc = { 0, 1, 0, 1, 0, 1, 0, 1, @@ -914,7 +914,7 @@ // CHECK-LE: or <2 x i64> // CHECK-LE: xor <2 x i64> - res_vull = vec_nor(vbll, vbll); + res_vbll = vec_nor(vbll, vbll); // CHECK: or <2 x i64> // CHECK: xor <2 x i64> // CHECK-LE: or <2 x i64> @@ -1290,13 +1290,13 @@ // CHECK-LE: fmul <2 x double> {{%.*}}, // CHECK-LE: fptosi <2 x double> {{%.*}} to <2 x i64> - res_vsll = vec_ctu(vd, 0); + res_vull = vec_ctu(vd, 0); // CHECK: fmul <2 x double> // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64> // CHECK-LE: fmul <2 x double> // CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64> - res_vsll = vec_ctu(vd, 31); + res_vull = vec_ctu(vd, 31); // CHECK: fmul <2 x double> // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64> // CHECK-LE: fmul <2 x double> @@ -1315,25 +1315,25 @@ // CHECK-LE: fmul <2 x double> {{%.*}}, // CHECK-LE: fptoui <2 x double> {{%.*}} to <2 x i64> - res_vd = vec_ctf(vsll, 0); + res_vf = vec_ctf(vsll, 0); // CHECK: sitofp <2 x i64> %{{.*}} to <2 x double> // CHECK: fmul <2 x double> // CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double> // CHECK-LE: fmul <2 x double> - res_vd = vec_ctf(vsll, 31); + res_vf = vec_ctf(vsll, 31); // CHECK: sitofp <2 x i64> %{{.*}} to <2 x double> // CHECK: fmul <2 x double> // CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double> // CHECK-LE: fmul <2 x double> - res_vd = vec_ctf(vull, 0); + res_vf = vec_ctf(vull, 0); // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK: fmul <2 x double> // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK-LE: fmul <2 x double> - res_vd = vec_ctf(vull, 31); + res_vf = vec_ctf(vull, 31); // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK: fmul <2 x double> // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double> @@ -1997,7 +1997,7 @@ // CHECK-LE: insertelement <2 x double> // CHECK-LE: shufflevector <2 x double> -res_vsll = vec_load_splats(sll, asi); +res_vsi = vec_load_splats(sll, asi); // CHECK: load i32 // CHECK: insertelement <4 x i32> // CHECK: shufflevector <4 x i32> @@ -2005,7 +2005,7 @@ // CHECK-LE: insertelement <4 x i32> // CHECK-LE: shufflevector <4 x i32> -res_vsll = vec_load_splats(ull, asi); +res_vsi = vec_load_splats(ull, asi); // CHECK: load i32 // CHECK: insertelement <4 x i32> // CHECK: shufflevector <4 x i32> @@ -2013,7 +2013,7 @@ // CHECK-LE: insertelement <4 x i32> // CHECK-LE: shufflevector <4 x i32> -res_vsll = vec_load_splats(sll, aui); +res_vui = vec_load_splats(sll, aui); // CHECK: load i32 // CHECK: insertelement <4 x i32> // CHECK: shufflevector <4 x i32> @@ -2021,7 +2021,7 @@ // CHECK-LE: insertelement <4 x i32> // CHECK-LE: shufflevector <4 x i32> -res_vsll = vec_load_splats(ull, aui); +res_vui = vec_load_splats(ull, aui); // CHECK: load i32 // CHECK: insertelement <4 x i32> // CHECK: shufflevector <4 x i32> @@ -2029,7 +2029,7 @@ // CHECK-LE: insertelement <4 x i32> // CHECK-LE: shufflevector <4 x i32> -res_vsll = vec_load_splats(sll, af); +res_vf = vec_load_splats(sll, af); // CHECK: load float // CHECK: insertelement <4 x float> // CHECK: shufflevector <4 x float> @@ -2037,7 +2037,7 @@ // CHECK-LE: insertelement <4 x float> // CHECK-LE: shufflevector <4 x float> -res_vsll = vec_load_splats(ull, af); +res_vf = vec_load_splats(ull, af); // CHECK: load float // CHECK: insertelement <4 x float> // CHECK: shufflevector <4 x float> @@ -2117,7 +2117,7 @@ // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> -res_vull = vec_permi(vbll, vbll, 3); +res_vbll = vec_permi(vbll, vbll, 3); // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ // RUN: -target-feature +power8-vector -triple powerpc64le-unknown-unknown \ // RUN: -emit-llvm %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-P8 #include diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-vec-error.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-vec-error.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-vec-error.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-vec-error.c @@ -1,11 +1,11 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -fsyntax-only \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-linux-gnu -fsyntax-only \ // RUN: -target-cpu pwr8 -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -fsyntax-only \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-linux-gnu -fsyntax-only \ // RUN: -target-cpu pwr8 -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-aix -fsyntax-only \ // RUN: -target-cpu pwr8 -Wall -Werror -verify %s -// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \ +// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-aix -fsyntax-only \ // RUN: -target-cpu pwr8 -Wall -Werror -verify %s #include diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c @@ -1,18 +1,18 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \ // RUN: -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr7 | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \ // RUN: -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \ // RUN: -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \ // RUN: -U__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck \ // RUN: --check-prefix=NOCOMPAT %s #include vector double vd = { 3.4e22, 1.8e-3 }; -vector signed long long vsll = { -12345678999ll, 12345678999 }; -vector unsigned long long vull = { 11547229456923630743llu, 18014402265226391llu }; +vector signed long long res_vsll, vsll = { -12345678999ll, 12345678999 }; +vector unsigned long long res_vull, vull = { 11547229456923630743llu, 18014402265226391llu }; vector float res_vf; vector double res_vd; vector signed int res_vsi; @@ -34,15 +34,16 @@ // CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]]) // CHECK-NEXT: fmul <4 x float> [[TMP3]], - res_vsi = vec_cts(vd, 4); + res_vsll = vec_cts(vd, 4); // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16 // CHECK-NEXT: fmul <2 x double> [[TMP4]], // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> - res_vui = vec_ctu(vd, 4); + res_vull = vec_ctu(vd, 4); // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16 // CHECK-NEXT: fmul <2 x double> [[TMP8]], // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> +// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> res_vd = vec_round(vd); // CHECK: call double @llvm.ppc.readflm() diff --git a/clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp b/clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp --- a/clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp +++ b/clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s #include