Index: llvm/test/tools/llvm-reduce/mir/generic-vreg.mir =================================================================== --- llvm/test/tools/llvm-reduce/mir/generic-vreg.mir +++ llvm/test/tools/llvm-reduce/mir/generic-vreg.mir @@ -12,13 +12,17 @@ # CHECK-INTERESTINGNESS: G_IMPLICIT_DEF # CHECK-INTERESTINGNESS: G_STORE -# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(<2 x s16>), implicit-def %10(s64), implicit-def %11(s64), implicit-def %12(<2 x s32>) -# RESULT-NEXT: %unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF -# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %12(<2 x s32>) +# RESULT: %{{[0-9]+}}:vgpr(s32) = G_IMPLICIT_DEF +# RESULT-NEXT: %{{[0-9]+}}:vgpr(<2 x s16>) = G_IMPLICIT_DEF +# RESULT-NEXT: %{{[0-9]+}}:sgpr(p1) = G_IMPLICIT_DEF +# RESULT-NEXT: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF +# RESULT-NEXT: %{{[0-9]+}}:vreg_64(s64) = IMPLICIT_DEF +# RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_IMPLICIT_DEF +# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %14(<2 x s32>) # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF -# RESULT-NEXT: G_STORE %v0(s32), %ptr(p1) :: (store (s32), addrspace 1) -# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %9(<2 x s16>), implicit %11(s64) +# RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1) +# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %{{[0-9]+}}(<2 x s16>), implicit %{{[0-9]+}}(s64) --- name: f Index: llvm/test/tools/llvm-reduce/mir/instr-reduce.mir =================================================================== --- llvm/test/tools/llvm-reduce/mir/instr-reduce.mir +++ llvm/test/tools/llvm-reduce/mir/instr-reduce.mir @@ -8,8 +8,8 @@ # pattern in the output and that combined with that the MIR has to be valid # (pass verify) results in the given sequence. -# CHECK: %0:gpr = COPY $x10 -# CHECK-NEXT: %2:gpr = ADDI %0, 5 +# CHECK: [[IMPDEF:%[0-9]+]]:gpr = IMPLICIT_DEF +# CHECK-NEXT: %{{[0-9]+}}:gpr = ADDI [[IMPDEF]], 5 # CHECK-NEXT: PseudoRET implicit $x10 ... Index: llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir =================================================================== --- llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir +++ llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir @@ -46,7 +46,7 @@ # RESULT-NEXT: - { id: 9, name: guard, offset: 128, size: 4, alignment: 4 } -# RESULT: S_NOP 0 +# RESULT: bb.0: # RESULT-NEXT: [[FI0:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.1, implicit $exec # RESULT-NEXT: [[FI1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0.bigalloca, implicit $exec # RESULT-NEXT: [[FI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.2, implicit $exec Index: llvm/test/tools/llvm-reduce/mir/subreg-def0.mir =================================================================== --- llvm/test/tools/llvm-reduce/mir/subreg-def0.mir +++ llvm/test/tools/llvm-reduce/mir/subreg-def0.mir @@ -4,7 +4,8 @@ # CHECK-INTERESTINGNESS: V_ADD_U32 -# RESULT: S_WAITCNT 0, implicit-def undef %2.sub1, implicit-def %3.sub0 +# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF +# RESULT-NEXT: %3.sub0:vreg_64 = IMPLICIT_DEF # RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %2.sub0, %2.sub1, implicit $exec # RESULT-NEXT: S_ENDPGM 0, implicit %1 Index: llvm/test/tools/llvm-reduce/mir/subreg-def1.mir =================================================================== --- llvm/test/tools/llvm-reduce/mir/subreg-def1.mir +++ llvm/test/tools/llvm-reduce/mir/subreg-def1.mir @@ -5,11 +5,10 @@ # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec -# RESULT: S_WAITCNT 0, implicit-def undef %2.sub1 -# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec -# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec -# RESULT-NEXT: S_ENDPGM 0, implicit %{{[0-9]+}}, implicit %{{[0-9]+}}.sub0 - +# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF +# RESULT-NEXT: %0.sub0:vreg_64 = V_ADD_U32_e32 %2.sub1, %2.sub0, implicit $exec +# RESULT-NEXT: %1.sub0:vreg_64 = V_ADD_U32_e32 4, %2.sub0, implicit $exec +# RESULT-NEXT: S_ENDPGM 0, implicit %2, implicit %2.sub0 --- name: f tracksRegLiveness: true Index: llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp =================================================================== --- llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp +++ llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp @@ -53,17 +53,17 @@ auto MRI = &MF.getRegInfo(); SetVector ToDelete; - MachineInstr *TopMI = nullptr; + const TargetSubtargetInfo &STI = MF.getSubtarget(); + const TargetInstrInfo *TII = STI.getInstrInfo(); + MachineBasicBlock *EntryMBB = &*MF.begin(); + MachineBasicBlock::iterator EntryInsPt = + EntryMBB->SkipPHIsLabelsAndDebug(EntryMBB->begin()); // Mark MIs for deletion according to some criteria. for (auto &MBB : MF) { for (auto &MI : MBB) { if (MI.isTerminator()) continue; - if (MBB.isEntryBlock() && !TopMI) { - TopMI = &MI; - continue; - } if (!O.shouldKeep()) ToDelete.insert(&MI); } @@ -102,19 +102,15 @@ } } - // If no dominating definition was found then add an implicit one to the - // first instruction in the entry block. - - // FIXME: This should really insert IMPLICIT_DEF or G_IMPLICIT_DEF. We - // need to refine the reduction quality metric from number of serialized - // bytes to continue progressing if we're going to introduce new - // instructions. - if (!NewReg && TopMI) { + // If no dominating definition was found then add an implicit def to the + // top of the entry block. + if (!NewReg) { NewReg = MRI->cloneVirtualRegister(Reg); - TopMI->addOperand(MachineOperand::CreateReg( - NewReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/, - MO.isDead(), MO.isUndef(), MO.isEarlyClobber(), MO.getSubReg(), - /*IsDebug*/ false, MO.isInternalRead())); + bool IsGeneric = MRI->getRegClassOrNull(Reg) == nullptr; + unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF + : TargetOpcode::IMPLICIT_DEF; + BuildMI(*EntryMBB, EntryInsPt, DebugLoc(), TII->get(ImpDef)) + .addReg(NewReg, getRegState(MO), MO.getSubReg()); } // Update all uses.