Index: lib/Target/X86/AsmParser/X86AsmParser.cpp
===================================================================
--- lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2665,14 +2665,22 @@
   // First, handle aliases that expand to multiple instructions.
   MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
 
-  MCInst Inst;
-
+  MCInst MInst;
+  uint64_t ErrorInfoIgnore;
+  // We are doing relaxcation only for microsoft OS.
+  // This will work only with triple -x86-64-pc-windows-msvc
+  bool RelaxcationMode = STI.getTargetTriple().getOS() == STI.getTargetTriple().Win32; 
+  unsigned M = MatchInstructionImpl(Operands, MInst, ErrorInfoIgnore,
+    MatchingInlineAsm, isParsingIntelSyntax());
   // Find one unsized memory operand, if present.
   X86Operand *UnsizedMemOp = nullptr;
   for (const auto &Op : Operands) {
     X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
     if (X86Op->isMemUnsized())
       UnsizedMemOp = X86Op;
+    //For any type of memory that don't have macth we recognaize it as UnsizeMemOp 
+    if (X86Op->isMem() && M == 0 && RelaxcationMode)
+      UnsizedMemOp = X86Op;
   }
 
   // Allow some instructions to have implicitly pointer-sized operands.  This is
@@ -2686,13 +2694,13 @@
       }
     }
   }
-
   // If an unsized memory operand is present, try to match with each memory
   // operand size.  In Intel assembly, the size is not part of the instruction
   // mnemonic.
+  MCInst Inst;
   SmallVector<unsigned, 8> Match;
   uint64_t ErrorInfoMissingFeature = 0;
-  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
+  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized() || (UnsizedMemOp && M == 0 && RelaxcationMode)) {
     static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
     for (unsigned Size : MopSizes) {
       UnsizedMemOp->Mem.Size = Size;
@@ -2701,8 +2709,11 @@
       unsigned M =
           MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
                                MatchingInlineAsm, isParsingIntelSyntax());
-      if (Match.empty() || LastOpcode != Inst.getOpcode())
+      if (Match.empty() || LastOpcode != Inst.getOpcode()){
         Match.push_back(M);
+        if (RelaxcationMode && M > 0)
+          break;
+      }
 
       // If this returned as a missing feature failure, remember that.
       if (Match.back() == Match_MissingFeature)
Index: test/MC/X86/intel-syntax-ambiguous.s
===================================================================
--- test/MC/X86/intel-syntax-ambiguous.s
+++ test/MC/X86/intel-syntax-ambiguous.s
@@ -1,47 +1,58 @@
-// RUN: not llvm-mc -triple i686-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple i686-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=NOT_MICROSOFT
+// RUN: not llvm-mc -triple -x86-64-microsoft-pc-masm < %s 2>&1 | FileCheck %s -check-prefix=MICROSOFT
 
 .intel_syntax
 
 // Basic case of ambiguity for inc.
 
 inc [eax]
-// CHECK: error: ambiguous operand size for instruction 'inc'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'inc'
+// MICROSOFT: incb    (%eax)
 inc dword ptr [eax]
 inc word ptr [eax]
 inc byte ptr [eax]
-// CHECK-NOT: error:
+// NOT_MICROSOFT-NOT: error:
 
 // Other ambiguous instructions.  Anything that doesn't take a register,
 // basically.
 
 dec [eax]
-// CHECK: error: ambiguous operand size for instruction 'dec'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'dec'
+// MICROSOFT: decb    (%eax)
 mov [eax], 1
-// CHECK: error: ambiguous operand size for instruction 'mov'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'mov'
+// MICROSOFT: movb   $1, (%eax)
 and [eax], 0
-// CHECK: error: ambiguous operand size for instruction 'and'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'and'
+// MICROSOFT: andb   $0, (%eax)
 or [eax], 1
-// CHECK: error: ambiguous operand size for instruction 'or'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'or'
+// MICROSOFT: orb    $1, (%eax)
 add [eax], 1
-// CHECK: error: ambiguous operand size for instruction 'add'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'add'
+// MICROSOFT: addb   $1, (%eax)
 sub [eax], 1
-// CHECK: error: ambiguous operand size for instruction 'sub'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'sub'
+// MICROSOFT: subb   $1, (%eax)
 
 // gas assumes these instructions are pointer-sized by default, and we follow
 // suit.
 push [eax]
 call [eax]
 jmp [eax]
-// CHECK-NOT: error:
+// NOT_MICROSOFT-NOT: error:
 
 add byte ptr [eax], eax
-// CHECK: error: invalid operand for instruction
+// NOT_MICROSOFT: error: invalid operand for instruction
+// MICROSOFT: addl    %eax, (%eax)
 
 add byte ptr [eax], eax
-// CHECK: error: invalid operand for instruction
+// NOT_MICROSOFT: error: invalid operand for instruction
+// MICROSOFT: addl    %eax, (%eax)
 
 add rax, 3
-// CHECK: error: register %rax is only available in 64-bit mode
+// NOT_MICROSOFT: error: register %rax is only available in 64-bit mode
+// MICROSOFT: addq    $3, %rax
 
 fadd   "?half@?0??bar@@YAXXZ@4NA"
-// CHECK: error: ambiguous operand size for instruction 'fadd'
+// NOT_MICROSOFT: error: ambiguous operand size for instruction 'fadd'
Index: test/MC/X86/relaxation.s
===================================================================
--- test/MC/X86/relaxation.s
+++ test/MC/X86/relaxation.s
@@ -0,0 +1,13 @@
+// RUN:%llvm-mc -triple x86_64-pc-windows-msvc -x86-asm-syntax=intel -output-asm-variant=1 -S -o - %s | FileCheck %s
+/*
+ This file is auto-generated to test inline assembler insertion compilation
+ This is test for instruction 'not'. This test must pass.
+ IMPORTANT:
+ use just to compile, NOT to run
+*/
+
+	//CHECK:not byte ptr [rip + test_mem] 
+		not	XMMWORD PTR test_mem
+    //CHECK:not byte ptr [rip + test_mem] 
+		not	TBYTE PTR test_mem
+