diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -648,6 +648,25 @@ ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAX}, VT, Custom); + // Expand FP operations that need libcalls. + setOperationAction(ISD::FREM, VT, Expand); + setOperationAction(ISD::FPOW, VT, Expand); + setOperationAction(ISD::FCOS, VT, Expand); + setOperationAction(ISD::FSIN, VT, Expand); + setOperationAction(ISD::FSINCOS, VT, Expand); + setOperationAction(ISD::FEXP, VT, Expand); + setOperationAction(ISD::FEXP2, VT, Expand); + setOperationAction(ISD::FLOG, VT, Expand); + setOperationAction(ISD::FLOG2, VT, Expand); + setOperationAction(ISD::FLOG10, VT, Expand); + setOperationAction(ISD::FRINT, VT, Expand); + setOperationAction(ISD::FNEARBYINT, VT, Expand); + + setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); + setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom); + setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); + setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); + setOperationAction(ISD::FCOPYSIGN, VT, Legal); setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom); diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll new file mode 100644 --- /dev/null +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt < %s -passes='print' 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v | FileCheck %s + +define void @unsupported_fp_ops( %vec) { +; CHECK-LABEL: 'unsupported_fp_ops' +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %sin = call @llvm.sin.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %cos = call @llvm.cos.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %pow = call @llvm.pow.nxv4f32( %vec, %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %powi = call @llvm.powi.nxv4f32.i32( %vec, i32 42) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %exp = call @llvm.exp.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %exp2 = call @llvm.exp2.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %log = call @llvm.log.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %log2 = call @llvm.log2.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %log10 = call @llvm.log10.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %rint = call @llvm.rint.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %nearbyint = call @llvm.nearbyint.nxv4f32( %vec) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + + %sin = call @llvm.sin.nxv4f32( %vec) + %cos = call @llvm.cos.nxv4f32( %vec) + %pow = call @llvm.pow.nxv4f32( %vec, %vec) + %powi = call @llvm.powi.nxv4f32.i32( %vec, i32 42) + %exp = call @llvm.exp.nxv4f32( %vec) + %exp2 = call @llvm.exp2.nxv4f32( %vec) + %log = call @llvm.log.nxv4f32( %vec) + %log2 = call @llvm.log2.nxv4f32( %vec) + %log10 = call @llvm.log10.nxv4f32( %vec) + %rint = call @llvm.rint.nxv4f32( %vec) + %nearbyint = call @llvm.nearbyint.nxv4f32( %vec) + ret void +} + +declare @llvm.sin.nxv4f32() +declare @llvm.cos.nxv4f32() +declare @llvm.pow.nxv4f32(, ) +declare @llvm.powi.nxv4f32.i32(, i32) +declare @llvm.exp.nxv4f32() +declare @llvm.exp2.nxv4f32() +declare @llvm.log.nxv4f32() +declare @llvm.log2.nxv4f32() +declare @llvm.log10.nxv4f32() +declare @llvm.rint.nxv4f32() +declare @llvm.nearbyint.nxv4f32()