Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17454,6 +17454,15 @@
   if (N->getOperand(0) == N->getOperand(1))
     return N->getOperand(0);
 
+  // CSEL cttz, 0, cc -> AND cttz 31
+  SDValue N1 = N->getOperand(1);
+  SDValue N2 = N->getOperand(2);
+  bool isZero = cast<ConstantSDNode>(N2.getNode())->isZero();
+  if (N1.getOpcode() == ISD::CTTZ && isZero) {
+    SDValue thirtyOne = DAG.getConstant(31, SDLoc(N), N1.getValueType());
+    return DAG.getNode(ISD::AND, SDLoc(N), N1.getValueType(), N1, thirtyOne);
+  }
+
   return performCONDCombine(N, DCI, DAG, 2, 3);
 }