diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
@@ -80,38 +80,48 @@
 
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
-  void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
+  void printInstruction(const MCInst *MI, uint64_t Address,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
 
-  bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
+  bool printAliasInstr(const MCInst *MI, uint64_t Address,
+                       const MCSubtargetInfo &STI, raw_ostream &OS);
   void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
                                unsigned OpIdx, unsigned PrintMethodIdx,
-                               raw_ostream &O);
+                               const MCSubtargetInfo &STI, raw_ostream &O);
 
 private:
-  void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
-                    raw_ostream &O) {
-    printOperand(MI, OpNum, O);
-  }
+  void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                    raw_ostream &O);
+  void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
   template <unsigned Bits, unsigned Offset = 0>
-  void printUImm(const MCInst *MI, int opNum, raw_ostream &O);
-  void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
-  void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
-  void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
+  void printUImm(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+                 raw_ostream &O);
+  void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+                       raw_ostream &O);
+  void printMemOperandEA(const MCInst *MI, int opNum,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+  void printFCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+                       raw_ostream &O);
   void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
 
-  bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
-                  raw_ostream &OS);
-  bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
-                  unsigned OpNo1, raw_ostream &OS);
-  bool printAlias(const MCInst &MI, raw_ostream &OS);
-  void printSaveRestore(const MCInst *MI, raw_ostream &O);
-  void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
+  bool printAlias(const char *Str, const MCInst &MI, uint64_t Address,
+                  unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS,
+                  bool IsBranch = false);
+  bool printAlias(const char *Str, const MCInst &MI, uint64_t Address,
+                  unsigned OpNo0, unsigned OpNo1, const MCSubtargetInfo &STI,
+                  raw_ostream &OS, bool IsBranch = false);
+  bool printAlias(const MCInst &MI, uint64_t Address,
+                  const MCSubtargetInfo &STI, raw_ostream &OS);
+  void printSaveRestore(const MCInst *MI, const MCSubtargetInfo &STI,
+                        raw_ostream &O);
+  void printRegisterList(const MCInst *MI, int opNum,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
 };
 } // end namespace llvm
 
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
@@ -88,29 +88,30 @@
     break;
   case Mips::Save16:
     O << "\tsave\t";
-    printSaveRestore(MI, O);
+    printSaveRestore(MI, STI, O);
     O << " # 16 bit inst\n";
     return;
   case Mips::SaveX16:
     O << "\tsave\t";
-    printSaveRestore(MI, O);
+    printSaveRestore(MI, STI, O);
     O << "\n";
     return;
   case Mips::Restore16:
     O << "\trestore\t";
-    printSaveRestore(MI, O);
+    printSaveRestore(MI, STI, O);
     O << " # 16 bit inst\n";
     return;
   case Mips::RestoreX16:
     O << "\trestore\t";
-    printSaveRestore(MI, O);
+    printSaveRestore(MI, STI, O);
     O << "\n";
     return;
   }
 
   // Try to print any aliases first.
-  if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O))
-    printInstruction(MI, Address, O);
+  if (!printAliasInstr(MI, Address, STI, O) &&
+      !printAlias(*MI, Address, STI, O))
+    printInstruction(MI, Address, STI, O);
   printAnnotation(O, Annot);
 
   switch (MI->getOpcode()) {
@@ -123,7 +124,7 @@
 }
 
 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
-                                   raw_ostream &O) {
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
@@ -139,8 +140,28 @@
   Op.getExpr()->print(O, &MAI, true);
 }
 
+void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
+                                         unsigned OpNo,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
+  const MCOperand &Op = MI->getOperand(OpNo);
+  if (!Op.isImm())
+    return printOperand(MI, OpNo, STI, O);
+
+  if (PrintBranchImmAsAddress) {
+    uint64_t Target = Address + Op.getImm();
+    if (STI.hasFeature(Mips::FeatureMips32))
+      Target &= 0xffffffff;
+    else if (STI.hasFeature(Mips::FeatureMips16))
+      Target &= 0xffff;
+    O << formatHex(Target);
+  } else
+    O << formatImm(Op.getImm());
+}
+
 template <unsigned Bits, unsigned Offset>
-void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,
+                                const MCSubtargetInfo &STI, raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(opNum);
   if (MO.isImm()) {
     uint64_t Imm = MO.getImm();
@@ -151,11 +172,12 @@
     return;
   }
 
-  printOperand(MI, opNum, O);
+  printOperand(MI, opNum, STI, O);
 }
 
-void MipsInstPrinter::
-printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,
+                                      const MCSubtargetInfo &STI,
+                                      raw_ostream &O) {
   // Load/Store memory operands -- imm($reg)
   // If PIC target the target is loaded as the
   // pattern lw $25,%call16($28)
@@ -175,24 +197,26 @@
     break;
   }
 
-  printOperand(MI, opNum+1, O);
+  printOperand(MI, opNum + 1, STI, O);
   O << "(";
-  printOperand(MI, opNum, O);
+  printOperand(MI, opNum, STI, O);
   O << ")";
 }
 
-void MipsInstPrinter::
-printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum,
+                                        const MCSubtargetInfo &STI,
+                                        raw_ostream &O) {
   // when using stack locations for not load/store instructions
   // print the same way as all normal 3 operand instructions.
-  printOperand(MI, opNum, O);
+  printOperand(MI, opNum, STI, O);
   O << ", ";
-  printOperand(MI, opNum+1, O);
+  printOperand(MI, opNum + 1, STI, O);
 }
 
-void MipsInstPrinter::
-printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
-  const MCOperand& MO = MI->getOperand(opNum);
+void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,
+                                      const MCSubtargetInfo & /* STI */,
+                                      raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(opNum);
   O << MipsFCCToString((Mips::CondCode)MO.getImm());
 }
 
@@ -202,82 +226,112 @@
 }
 
 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
-                                 unsigned OpNo, raw_ostream &OS) {
+                                 uint64_t Address, unsigned OpNo,
+                                 const MCSubtargetInfo &STI, raw_ostream &OS,
+                                 bool IsBranch) {
   OS << "\t" << Str << "\t";
-  printOperand(&MI, OpNo, OS);
+  IsBranch ? printBranchOperand(&MI, Address, OpNo, STI, OS)
+           : printOperand(&MI, OpNo, STI, OS);
   return true;
 }
 
 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
-                                 unsigned OpNo0, unsigned OpNo1,
-                                 raw_ostream &OS) {
-  printAlias(Str, MI, OpNo0, OS);
+                                 uint64_t Address, unsigned OpNo0,
+                                 unsigned OpNo1, const MCSubtargetInfo &STI,
+                                 raw_ostream &OS, bool IsBranch) {
+  printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch);
   OS << ", ";
-  printOperand(&MI, OpNo1, OS);
+  IsBranch ? printBranchOperand(&MI, Address, OpNo1, STI, OS)
+           : printOperand(&MI, OpNo1, STI, OS);
   return true;
 }
 
-bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
+bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
+                                 const MCSubtargetInfo &STI, raw_ostream &OS) {
   switch (MI.getOpcode()) {
   case Mips::BEQ:
   case Mips::BEQ_MM:
     // beq $zero, $zero, $L2 => b $L2
     // beq $r0, $zero, $L2 => beqz $r0, $L2
     return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
-            printAlias("b", MI, 2, OS)) ||
-           (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
+            printAlias("b", MI, Address, 2, STI, OS, true)) ||
+           (isReg<Mips::ZERO>(MI, 1) &&
+            printAlias("beqz", MI, Address, 0, 2, STI, OS, true));
   case Mips::BEQ64:
     // beq $r0, $zero, $L2 => beqz $r0, $L2
-    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
+    return isReg<Mips::ZERO_64>(MI, 1) &&
+           printAlias("beqz", MI, Address, 0, 2, STI, OS, true);
   case Mips::BNE:
   case Mips::BNE_MM:
     // bne $r0, $zero, $L2 => bnez $r0, $L2
-    return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
+    return isReg<Mips::ZERO>(MI, 1) &&
+           printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
   case Mips::BNE64:
     // bne $r0, $zero, $L2 => bnez $r0, $L2
-    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
+    return isReg<Mips::ZERO_64>(MI, 1) &&
+           printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
   case Mips::BGEZAL:
     // bgezal $zero, $L1 => bal $L1
-    return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
+    return isReg<Mips::ZERO>(MI, 0) &&
+           printAlias("bal", MI, Address, 1, STI, OS, true);
   case Mips::BC1T:
     // bc1t $fcc0, $L1 => bc1t $L1
-    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
+    return isReg<Mips::FCC0>(MI, 0) &&
+           printAlias("bc1t", MI, Address, 1, STI, OS, true);
   case Mips::BC1F:
     // bc1f $fcc0, $L1 => bc1f $L1
-    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
+    return isReg<Mips::FCC0>(MI, 0) &&
+           printAlias("bc1f", MI, Address, 1, STI, OS, true);
   case Mips::JALR:
+    // jalr $zero, $r1 => jr $r1
     // jalr $ra, $r1 => jalr $r1
-    return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
+    return (isReg<Mips::ZERO>(MI, 0) &&
+            printAlias("jr", MI, Address, 1, STI, OS)) ||
+           (isReg<Mips::RA>(MI, 0) &&
+            printAlias("jalr", MI, Address, 1, STI, OS));
   case Mips::JALR64:
+    // jalr $zero, $r1 => jr $r1
     // jalr $ra, $r1 => jalr $r1
-    return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
+    return (isReg<Mips::ZERO_64>(MI, 0) &&
+            printAlias("jr", MI, Address, 1, STI, OS)) ||
+           (isReg<Mips::RA_64>(MI, 0) &&
+            printAlias("jalr", MI, Address, 1, STI, OS));
   case Mips::NOR:
   case Mips::NOR_MM:
   case Mips::NOR_MMR6:
     // nor $r0, $r1, $zero => not $r0, $r1
-    return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
+    return isReg<Mips::ZERO>(MI, 2) &&
+           printAlias("not", MI, Address, 0, 1, STI, OS);
   case Mips::NOR64:
     // nor $r0, $r1, $zero => not $r0, $r1
-    return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
+    return isReg<Mips::ZERO_64>(MI, 2) &&
+           printAlias("not", MI, Address, 0, 1, STI, OS);
   case Mips::OR:
+  case Mips::ADDu:
     // or $r0, $r1, $zero => move $r0, $r1
-    return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
-  default: return false;
+    // addu $r0, $r1, $zero => move $r0, $r1
+    return isReg<Mips::ZERO>(MI, 2) &&
+           printAlias("move", MI, Address, 0, 1, STI, OS);
+  default:
+    return false;
   }
 }
 
-void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
+void MipsInstPrinter::printSaveRestore(const MCInst *MI,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     if (i != 0) O << ", ";
     if (MI->getOperand(i).isReg())
       printRegName(O, MI->getOperand(i).getReg());
     else
-      printUImm<16>(MI, i, O);
+      printUImm<16>(MI, i, STI, O);
   }
 }
 
-void MipsInstPrinter::
-printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,
+                                        const MCSubtargetInfo & /* STI */,
+                                        raw_ostream &O) {
   // - 2 because register List is always first operand of instruction and it is
   // always followed by memory operand (base + offset).
   for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -15,6 +15,7 @@
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget21MM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtarget26_mm : Operand<OtherVT> {
@@ -22,6 +23,7 @@
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget26MM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtargetr6 : Operand<OtherVT> {
@@ -29,6 +31,7 @@
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTargetMM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtarget_lsl2_mm : Operand<OtherVT> {
@@ -38,6 +41,7 @@
   // set with DecodeDisambiguates
   let DecoderMethod = "";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -174,6 +174,7 @@
   let OperandType   = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget7MM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtarget10_mm : Operand<OtherVT> {
@@ -181,6 +182,7 @@
   let OperandType   = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget10MM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtarget_mm : Operand<OtherVT> {
@@ -188,6 +190,7 @@
   let OperandType   = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTargetMM";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def simm23_lsl2 : Operand<i32> {
@@ -1320,6 +1323,7 @@
                                      II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
+  def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -267,8 +267,13 @@
   string RegisterPrefix = "$";
 }
 
+def MipsAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
 def Mips : Target {
   let InstructionSet = MipsInstrInfo;
+  let AssemblyWriters = [MipsAsmWriter];
   let AssemblyParsers = [MipsAsmParser];
   let AssemblyParserVariants = [MipsAsmParserVariant];
   let AllowRegisterRenaming = 1;
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -39,6 +39,7 @@
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget21";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def brtarget26 : Operand<OtherVT> {
@@ -46,6 +47,7 @@
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget26";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 
 def jmpoffset16 : Operand<OtherVT> {
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -833,18 +833,22 @@
 def jmptarget   : Operand<OtherVT> {
   let EncoderMethod = "getJumpTargetOpValue";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
+  let OperandType = "OPERAND_PCREL";
 }
 def brtarget    : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValue";
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 def brtarget1SImm16 : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValue1SImm16";
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget1SImm16";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let PrintMethod = "printBranchOperand";
 }
 def calltarget  : Operand<iPTR> {
   let EncoderMethod = "getJumpTargetOpValue";
diff --git a/llvm/test/CodeGen/Mips/micromips-b-range.ll b/llvm/test/CodeGen/Mips/micromips-b-range.ll
--- a/llvm/test/CodeGen/Mips/micromips-b-range.ll
+++ b/llvm/test/CodeGen/Mips/micromips-b-range.ll
@@ -7,56 +7,56 @@
 ; CHECK-NEXT:     8:	03 22 11 50 	addu	$2, $2, $25
 ; CHECK-NEXT:     c:	fc 42 00 00 	lw	$2, 0($2)
 ; CHECK-NEXT:    10:	69 20 	      lw16	$2, 0($2)
-; CHECK-NEXT:    12:	40 c2 00 14 	bgtz	$2, 44 <foo+0x3e>
+; CHECK-NEXT:    12:	40 c2 00 14 	bgtz	$2, 0x3e <foo+0x3e>
 ; CHECK-NEXT:    16:	00 00 00 00 	nop
 ; CHECK-NEXT:    1a:	33 bd ff f8 	addiu	$sp, $sp, -8
 ; CHECK-NEXT:    1e:	fb fd 00 00 	sw	$ra, 0($sp)
 ; CHECK-NEXT:    22:	41 a1 00 01 	lui	$1, 1
-; CHECK-NEXT:    26:	40 60 00 02 	bal	8 <foo+0x2e>
+; CHECK-NEXT:    26:	40 60 00 02 	bal	0x2e <foo+0x2e>
 ; CHECK-NEXT:    2a:	30 21 04 69 	addiu	$1, $1, 1129
 ; CHECK-NEXT:    2e:	00 3f 09 50 	addu	$1, $ra, $1
 ; CHECK-NEXT:    32:	ff fd 00 00 	lw	$ra, 0($sp)
 ; CHECK-NEXT:    36:	00 01 0f 3c 	jr	$1
 ; CHECK-NEXT:    3a:	33 bd 00 08 	addiu	$sp, $sp, 8
-; CHECK-NEXT:    3e:	94 00 00 02 	b	8 <foo+0x46>
+; CHECK-NEXT:    3e:	94 00 00 02 	b	0x46 <foo+0x46>
 ; CHECK-NEXT:    42:	00 00 00 00 	nop
 ; CHECK-NEXT:    46:	30 20 4e 1f 	addiu	$1, $zero, 19999
-; CHECK-NEXT:    4a:	b4 22 00 14 	bne	$2, $1, 44 <foo+0x76>
+; CHECK-NEXT:    4a:	b4 22 00 14 	bne	$2, $1, 0x76 <foo+0x76>
 ; CHECK-NEXT:    4e:	00 00 00 00 	nop
 ; CHECK-NEXT:    52:	33 bd ff f8 	addiu	$sp, $sp, -8
 ; CHECK-NEXT:    56:	fb fd 00 00 	sw	$ra, 0($sp)
 ; CHECK-NEXT:    5a:	41 a1 00 01 	lui	$1, 1
-; CHECK-NEXT:    5e:	40 60 00 02 	bal	8 <foo+0x66>
+; CHECK-NEXT:    5e:	40 60 00 02 	bal	0x66 <foo+0x66>
 ; CHECK-NEXT:    62:	30 21 04 5d 	addiu	$1, $1, 1117
 ; CHECK-NEXT:    66:	00 3f 09 50 	addu	$1, $ra, $1
 ; CHECK-NEXT:    6a:	ff fd 00 00 	lw	$ra, 0($sp)
 ; CHECK-NEXT:    6e:	00 01 0f 3c 	jr	$1
 ; CHECK-NEXT:    72:	33 bd 00 08 	addiu	$sp, $sp, 8
 ; CHECK-NEXT:    76:	30 20 27 0f 	addiu	$1, $zero, 9999
-; CHECK-NEXT:    7a:	94 22 00 14 	beq	$2, $1, 44 <foo+0xa6>
+; CHECK-NEXT:    7a:	94 22 00 14 	beq	$2, $1, 0xa6 <foo+0xa6>
 ; CHECK-NEXT:    7e:	00 00 00 00 	nop
 ; CHECK-NEXT:    82:	33 bd ff f8 	addiu	$sp, $sp, -8
 ; CHECK-NEXT:    86:	fb fd 00 00 	sw	$ra, 0($sp)
 ; CHECK-NEXT:    8a:	41 a1 00 01 	lui	$1, 1
-; CHECK-NEXT:    8e:	40 60 00 02 	bal	8 <foo+0x96>
+; CHECK-NEXT:    8e:	40 60 00 02 	bal	0x96 <foo+0x96>
 ; CHECK-NEXT:    92:	30 21 04 2d 	addiu	$1, $1, 1069
 ; CHECK-NEXT:    96:	00 3f 09 50 	addu	$1, $ra, $1
 ; CHECK-NEXT:    9a:	ff fd 00 00 	lw	$ra, 0($sp)
 ; CHECK-NEXT:    9e:	00 01 0f 3c 	jr	$1
 ; CHECK-NEXT:    a2:	33 bd 00 08 	addiu	$sp, $sp, 8
 ; CHECK:                ...
-; CHECK-NEXT: 1046a:	94 00 00 02 	b	8 <foo+0x10472>
+; CHECK-NEXT: 1046a:	94 00 00 02 	b	0x10472 <foo+0x10472>
 ; CHECK-NEXT: 1046e:	00 00 00 00 	nop
 ; CHECK-NEXT: 10472:	33 bd ff f8 	addiu	$sp, $sp, -8
 ; CHECK-NEXT: 10476:	fb fd 00 00 	sw	$ra, 0($sp)
 ; CHECK-NEXT: 1047a:	41 a1 00 01 	lui	$1, 1
-; CHECK-NEXT: 1047e:	40 60 00 02 	bal	8 <foo+0x10486>
+; CHECK-NEXT: 1047e:	40 60 00 02 	bal	0x10486 <foo+0x10486>
 ; CHECK-NEXT: 10482:	30 21 04 01 	addiu	$1, $1, 1025
 ; CHECK-NEXT: 10486:	00 3f 09 50 	addu	$1, $ra, $1
 ; CHECK-NEXT: 1048a:	ff fd 00 00 	lw	$ra, 0($sp)
 ; CHECK-NEXT: 1048e:	00 01 0f 3c 	jr	$1
 ; CHECK-NEXT: 10492:	33 bd 00 08 	addiu	$sp, $sp, 8
-; CHECK-NEXT: 10496:	94 00 00 02 	b	8 <foo+0x1049e>
+; CHECK-NEXT: 10496:	94 00 00 02 	b	0x1049e <foo+0x1049e>
 
 @x = external global i32, align 4
 
diff --git a/llvm/test/MC/Mips/expansion-j-sym-pic.s b/llvm/test/MC/Mips/expansion-j-sym-pic.s
--- a/llvm/test/MC/Mips/expansion-j-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-j-sym-pic.s
@@ -38,9 +38,9 @@
 # MICRO:  b      local_label      # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: local_label, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 ff ff     b       0
+# ELF-O32:      10 00 ff ff     b       0x0 <local_label>
 
-# ELF-NXX:      10 00 ff ff     b       0
+# ELF-NXX:      10 00 ff ff     b       0x0 <local_label>
 
   j weak_label
   nop
@@ -51,10 +51,10 @@
 # MICRO:  b      weak_label       # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: weak_label, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 ff ff     b       0
+# ELF-O32:      10 00 ff ff     b       0x8 <local_label+0x8>
 # ELF-O32-NEXT:                 R_MIPS_PC16  weak_label
 
-# ELF-NXX:      10 00 00 00     b       4
+# ELF-NXX:      10 00 00 00     b       0xc <local_label+0xc>
 # ELF-N32-NEXT:                 R_MIPS_PC16  weak_label
 # ELF-N64-NEXT:                 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE  weak_label
 
@@ -67,10 +67,10 @@
 # MICRO:  b      global_label     # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: global_label, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 ff ff     b       0
+# ELF-O32:      10 00 ff ff     b       0x10 <local_label+0x10>
 # ELF-O32-NEXT:         00000010:  R_MIPS_PC16  global_label
 
-# ELF-NXX:      10 00 00 00     b       4
+# ELF-NXX:      10 00 00 00     b       0x14 <local_label+0x14>
 # ELF-N32-NEXT:                 R_MIPS_PC16 global_label
 # ELF-N64-NEXT:                 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE  global_label
 
@@ -83,10 +83,10 @@
 # MICRO:  b      .text            # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: .text, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 ff f9 	b	-24 <local_label>
+# ELF-O32:      10 00 ff f9 	b	0x0 <local_label>
 # ELF-O32-NEXT: 00 00 00 00 	nop
 
-# ELF-NXX:      10 00 ff f9 	b	-24 <local_label>
+# ELF-NXX:      10 00 ff f9 	b	0x0 <local_label>
 # ELF-NXX-NEXT: 00 00 00 00 	nop
 
   j 1f
@@ -98,9 +98,9 @@
 # MICRO:  b      {{.*}}tmp0{{.*}} # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: {{.*}}tmp0{{.*}}, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 00 04     b       20 <local_label+0x34>
+# ELF-O32:      10 00 00 04     b       0x34 <local_label+0x34>
 
-# ELF-NXX:      10 00 00 04     b       20 <local_label+0x34>
+# ELF-NXX:      10 00 00 04     b       0x34 <local_label+0x34>
 
   .local forward_local
   j forward_local
@@ -112,9 +112,9 @@
 # MICRO:  b      forward_local    # encoding: [0x94,0x00,A,A]
 # MICRO:                          #   fixup A - offset: 0, value: forward_local, kind: fixup_MICROMIPS_PC16_S1
 
-# ELF-O32:      10 00 00 04     b       20 <forward_local>
+# ELF-O32:      10 00 00 04     b       0x3c <forward_local>
 
-# ELF-NXX:      10 00 00 04     b       20 <forward_local>
+# ELF-NXX:      10 00 00 04     b       0x3c <forward_local>
 
   j 0x4
 
@@ -122,9 +122,9 @@
 
 # MICRO:  b      4                # encoding: [0x94,0x00,0x00,0x02]
 
-# ELF-O32:      10 00 00 01     b       8
+# ELF-O32:      10 00 00 01     b       0x38 <local_label+0x38>
 
-# ELF-NXX:      10 00 00 01     b       8
+# ELF-NXX:      10 00 00 01     b       0x38 <local_label+0x38>
 
   .end local_label
 
diff --git a/llvm/test/MC/Mips/instr-analysis.s b/llvm/test/MC/Mips/instr-analysis.s
--- a/llvm/test/MC/Mips/instr-analysis.s
+++ b/llvm/test/MC/Mips/instr-analysis.s
@@ -10,15 +10,15 @@
 # CHECK-NEXT:        c:       00 00 00 00     nop
 #
 # CHECK:      <loc2>:
-# CHECK-NEXT:       10:       10 00 ff fd     b       -8 <loc1>
+# CHECK-NEXT:       10:       10 00 ff fd     b	      0x8 <loc1>
 # CHECK-NEXT:       14:       00 00 00 00     nop
 #
 # CHECK:      <loc3>:
-# CHECK-NEXT:       18:       10 43 ff fd     beq     $2, $3, -8 <loc2>
+# CHECK-NEXT:       18:       10 43 ff fd     beq     $2, $3, 0x10 <loc2>
 # CHECK-NEXT:       1c:       00 00 00 00     nop
-# CHECK-NEXT:       20:       04 11 ff f9     bal     -24 <loc1>
+# CHECK-NEXT:       20:       04 11 ff f9     bal     0x8 <loc1>
 # CHECK-NEXT:       24:       00 00 00 00     nop
-# CHECK-NEXT:       28:       08 00 00 04     j       16 <loc2>
+# CHECK-NEXT:       28:       08 00 00 04     j       0x38 <loc3+0x20>
 
   .text
   .globl foo
diff --git a/llvm/test/MC/Mips/micromips-el-fixup-data.s b/llvm/test/MC/Mips/micromips-el-fixup-data.s
--- a/llvm/test/MC/Mips/micromips-el-fixup-data.s
+++ b/llvm/test/MC/Mips/micromips-el-fixup-data.s
@@ -16,7 +16,7 @@
     addiu   $sp, $sp, -16
     bnez    $9, lab1
 
-# CHECK:    09 b4 03 00    bnez $9, 10
+# CHECK:    09 b4 03 00    bnez $9, 0xe <lab1>
 
     addu    $zero, $zero, $zero
 lab1:
diff --git a/llvm/test/MC/Mips/micromips-neg-offset.s b/llvm/test/MC/Mips/micromips-neg-offset.s
--- a/llvm/test/MC/Mips/micromips-neg-offset.s
+++ b/llvm/test/MC/Mips/micromips-neg-offset.s
@@ -4,9 +4,9 @@
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o - \
 # RUN:   | llvm-objdump -d --mattr=micromips - | FileCheck %s
 
-# CHECK: 0:   8f 7e        beqzc16  $6, -4
-# CHECK: 2:   cf fe        bc16     -4
-# CHECK: 4:   b7 ff ff fe  balc     -4
+# CHECK: 0:   8f 7e        beqzc16  $6, 0xfffffffc <.text+0xfffffffffffffffc>
+# CHECK: 2:   cf fe        bc16     0xfffffffe <.text+0xfffffffffffffffe>
+# CHECK: 4:   b7 ff ff fe  balc     0x0 <.text>
 
 beqz16  $6, -4
 b16     -4
diff --git a/llvm/test/MC/Mips/mips-jump-pc-region.s b/llvm/test/MC/Mips/mips-jump-pc-region.s
--- a/llvm/test/MC/Mips/mips-jump-pc-region.s
+++ b/llvm/test/MC/Mips/mips-jump-pc-region.s
@@ -8,7 +8,7 @@
 # Force us into the second 256 MB region with a non-zero instruction index
 .org 256*1024*1024 + 12
 # CHECK-LABEL: 1000000c <foo>:
-# CHECK-NEXT: 1000000c: 08 00 00 03                   j       12 <foo>
+# CHECK-NEXT: 1000000c: 08 00 00 03                   j       0x10000018 <foo+0xc>
 # CHECK-NEXT: 10000010: 0c 00 00 04                   jal     16 <foo+0x4>
 # CHECK-NEXT: 10000014: 74 00 00 05                   jalx    20 <foo+0x8>
 foo: