Index: llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
@@ -0,0 +1,20 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# RESULT: S_ENDPGM 0, implicit undef %0:vgpr_32
+
+# Previously the the function clone would assert due to not preserving
+# virtual registers which had no defs.
+
+---
+name: undef_vreg_operand
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    S_NOP 0
+    S_ENDPGM 0, implicit undef %0:vgpr_32
+
+...
Index: llvm/tools/llvm-reduce/ReducerWorkItem.cpp
===================================================================
--- llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -35,7 +35,7 @@
     for (auto &SrcMI : SrcMBB) {
       for (unsigned I = 0, E = SrcMI.getNumOperands(); I < E; ++I) {
         auto &DMO = SrcMI.getOperand(I);
-        if (!DMO.isReg() || !DMO.isDef())
+        if (!DMO.isReg())
           continue;
         Register SrcReg = DMO.getReg();
         if (Register::isPhysicalRegister(SrcReg))