diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -87,6 +87,8 @@ SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; + SDValue makeV_ILLEGAL(SDValue Op, SelectionDAG &DAG) const; + // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset // (the offset that is included in bounds checking and swizzling, to be split // between the instruction's voffset and immoffset fields) and soffset (the diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6632,8 +6632,7 @@ Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx90a, NumVDataDwords, NumVAddrDwords); if (Opcode == -1) - report_fatal_error( - "requested image instruction is not supported on this GPU"); + return makeV_ILLEGAL(Op, DAG); } if (Opcode == -1 && Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) @@ -7823,6 +7822,9 @@ unsigned Opcode = 0; switch (IntrID) { case Intrinsic::amdgcn_global_atomic_fadd: + if (!Subtarget->hasAtomicFaddNoRtnInsts()) + return makeV_ILLEGAL(Op, DAG); + LLVM_FALLTHROUGH; case Intrinsic::amdgcn_flat_atomic_fadd: { EVT VT = Op.getOperand(3).getValueType(); return DAG.getAtomic(ISD::ATOMIC_LOAD_FADD, DL, VT, @@ -8390,6 +8392,27 @@ } } +SDValue SITargetLowering::makeV_ILLEGAL(SDValue Op, SelectionDAG & DAG) const { + // Create the V_ILLEGAL node. + SDLoc DL(Op); + auto Opcode = Subtarget->getGeneration() < AMDGPUSubtarget::GFX10 ? + AMDGPU::V_ILLEGAL_gfx6_gfx7_gfx8_gfx9 : AMDGPU::V_ILLEGAL; + auto EntryNode = DAG.getEntryNode(); + auto IllegalNode = DAG.getMachineNode(Opcode, DL, MVT::Other, EntryNode); + auto IllegalVal = SDValue(IllegalNode, 0u); + + // Add the V_ILLEGAL node to the root chain to prevent its removal. + auto Chains = SmallVector(); + Chains.push_back(IllegalVal); + Chains.push_back(DAG.getRoot()); + auto Root = DAG.getTokenFactor(SDLoc(Chains.back()), Chains); + DAG.setRoot(Root); + + // Merge with UNDEF to satisfy return value requirements. + auto UndefVal = DAG.getUNDEF(Op.getValueType()); + return DAG.getMergeValues({UndefVal, IllegalVal}, DL); +} + // The raw.(t)buffer and struct.(t)buffer intrinsics have two offset args: // offset (the offset that is included in bounds checking and swizzling, to be // split between the instruction's voffset and immoffset fields) and soffset diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3356,3 +3356,25 @@ let InOperandList = (ins type1:$src0); let hasSideEffects = 0; } + +//============================================================================// +// Dummy Instructions +//============================================================================// + +def V_ILLEGAL_gfx6_gfx7_gfx8_gfx9 : Enc32, InstSI<(outs), (ins), "v_illegal"> { + let Inst{31-0} = 0xFFFFFFFF; + let FixedSize = 1; + let Size = 4; + let Uses = [EXEC]; + let hasSideEffects = 1; + let SubtargetPredicate = isGFX6GFX7GFX8GFX9; +} + +def V_ILLEGAL : Enc32, InstSI<(outs), (ins), "v_illegal"> { + let Inst{31-0} = 0x00000000; + let FixedSize = 1; + let Size = 4; + let Uses = [EXEC]; + let hasSideEffects = 1; + let SubtargetPredicate = isGFX10Plus; +} diff --git a/llvm/test/CodeGen/AMDGPU/v_illegal-atomics.ll b/llvm/test/CodeGen/AMDGPU/v_illegal-atomics.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/v_illegal-atomics.ll @@ -0,0 +1,63 @@ +; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906-ASM %s +; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX908-ASM %s +; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A-ASM %s +; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940-ASM %s +; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1030-ASM %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100-ASM %s + +; GFX906-ASM-LABEL: fadd_test: +; GFX906-ASM-NOT: global_atomic_add_f32 +; GFX906-ASM: v_illegal + +; GFX908-ASM-LABEL: fadd_test: +; GFX908-ASM-NOT: v_illegal +; GFX908-ASM: global_atomic_add_f32 + +; GFX90A-ASM-LABEL: fadd_test: +; GFX90A-ASM-NOT: v_illegal +; GFX90A-ASM: global_atomic_add_f32 + +; GFX940-ASM-LABEL: fadd_test: +; GFX940-ASM-NOT: v_illegal +; GFX940-ASM: global_atomic_add_f32 + +; GFX1030-ASM-LABEL: fadd_test: +; GFX1030-ASM-NOT: global_atomic_add_f32 +; GFX1030-ASM: v_illegal + +; GFX1100-ASM-LABEL: fadd_test: +; GFX1100-ASM-NOT: v_illegal +; GFX1100-ASM: global_atomic_add_f32 + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx906 -d - | FileCheck --check-prefix=GFX906-OBJ %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx908 -d - | FileCheck --check-prefix=GFX908-OBJ %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx90a -d - | FileCheck --check-prefix=GFX90A-OBJ %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx940 -d - | FileCheck --check-prefix=GFX940-OBJ %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck --check-prefix=GFX1030-OBJ %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1100 -d - | FileCheck --check-prefix=GFX1100-OBJ %s + +; GFX906-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-OBJ-NEXT: v_illegal // 000000000004: FFFFFFFF + +; GFX908-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX908-OBJ-NEXT: global_atomic_add_f32 + +; GFX90A-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-OBJ-NEXT: global_atomic_add_f32 + +; GFX940-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX940-OBJ-NEXT: global_atomic_add_f32 + +; GFX1030-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1030-OBJ-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1030-OBJ-NEXT: v_illegal // 000000000008: 00000000 + +; GFX1100-OBJ: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-OBJ-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1100-OBJ-NEXT: global_atomic_add_f32 v[0:1], v2, off + +define fastcc void @fadd_test(float addrspace(1)* nocapture noundef %0, float noundef %1) unnamed_addr { + %3 = tail call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* noundef %0, float noundef %1) + ret void +} +declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* nocapture, float) diff --git a/llvm/test/CodeGen/AMDGPU/v_illegal-image_sample.ll b/llvm/test/CodeGen/AMDGPU/v_illegal-image_sample.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/v_illegal-image_sample.ll @@ -0,0 +1,40 @@ +; RUN: llc -O0 -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906 %s +; RUN: llc -O0 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX908 %s +; RUN: llc -O0 -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX90A %s +; RUN: llc -O0 -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940 %s +; RUN: llc -O0 -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1030 %s +; RUN: llc -O0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100 %s + +; GFX906-LABEL: image_sample_test: +; GFX906-NOT: v_illegal +; GFX906: image_sample_lz + +; GFX908-LABEL: image_sample_test: +; GFX908-NOT: v_illegal +; GFX908: image_sample_lz + +; GFX90A-LABEL: image_sample_test: +; GFX90A-NOT: image_sample_lz +; GFX90A: v_illegal + +; GFX940-LABEL: image_sample_test: +; GFX940-NOT: image_sample_lz +; GFX940: v_illegal + +; GFX1030-LABEL: image_sample_test: +; GFX1030-NOT: v_illegal +; GFX1030: image_sample_lz + +; GFX1100-LABEL: image_sample_test: +; GFX1100-NOT: v_illegal +; GFX1100: image_sample_lz + +define amdgpu_kernel void @image_sample_test(<4 x float> addrspace(1)* %out, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) { + + %result = tail call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 false, i32 0, i32 0) + + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} + +declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) diff --git a/llvm/test/MC/AMDGPU/v_illegal-atomics.s b/llvm/test/MC/AMDGPU/v_illegal-atomics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AMDGPU/v_illegal-atomics.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck --check-prefix=GFX906 %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck --check-prefix=GFX908 %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX1030 %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX1100 %s + +v_illegal +// GFX906: encoding: [0xff,0xff,0xff,0xff] +// GFX908: encoding: [0xff,0xff,0xff,0xff] +// GFX90A: encoding: [0xff,0xff,0xff,0xff] +// GFX940: encoding: [0xff,0xff,0xff,0xff] +// GFX1030: encoding: [0x00,0x00,0x00,0x00] +// GFX1100: encoding: [0x00,0x00,0x00,0x00]