diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1621,7 +1621,7 @@ } // Reject elements larger than ELEN. - if (EltVT.getSizeInBits() > Subtarget.getMaxELENForFixedLengthVectors()) + if (EltVT.getSizeInBits() > Subtarget.getELEN()) return false; unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); @@ -1650,7 +1650,7 @@ "Expected legal fixed length vector!"); unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits(); - unsigned MaxELen = Subtarget.getMaxELENForFixedLengthVectors(); + unsigned MaxELen = Subtarget.getELEN(); MVT EltVT = VT.getVectorElementType(); switch (EltVT.SimpleTy) { @@ -2050,8 +2050,7 @@ // codegen across RV32 and RV64. unsigned NumViaIntegerBits = std::min(std::max(NumElts, 8u), Subtarget.getXLen()); - NumViaIntegerBits = std::min(NumViaIntegerBits, - Subtarget.getMaxELENForFixedLengthVectors()); + NumViaIntegerBits = std::min(NumViaIntegerBits, Subtarget.getELEN()); if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { // If we have to use more than one INSERT_VECTOR_ELT then this // optimization is likely to increase code size; avoid peforming it in @@ -2435,7 +2434,7 @@ static bool isInterleaveShuffle(ArrayRef Mask, MVT VT, bool &SwapSources, const RISCVSubtarget &Subtarget) { // We need to be able to widen elements to the next larger integer type. - if (VT.getScalarSizeInBits() >= Subtarget.getMaxELENForFixedLengthVectors()) + if (VT.getScalarSizeInBits() >= Subtarget.getELEN()) return false; int Size = Mask.size(); @@ -4516,7 +4515,7 @@ unsigned WidenVecLen; SDValue ExtractElementIdx; SDValue ExtractBitIdx; - unsigned MaxEEW = Subtarget.getMaxELENForFixedLengthVectors(); + unsigned MaxEEW = Subtarget.getELEN(); MVT LargestEltVT = MVT::getIntegerVT( std::min(MaxEEW, unsigned(XLenVT.getSizeInBits()))); if (NumElts <= LargestEltVT.getSizeInBits()) { diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -207,6 +207,10 @@ return 0; } + unsigned getELEN() const { + assert(hasVInstructions() && "Expected V extension"); + return hasVInstructionsI64() ? 64 : 32; + } unsigned getMinVLen() const { return ZvlLen; } unsigned getMaxVLen() const { return Zvl65536b; } unsigned getRealMinVLen() const { @@ -262,7 +266,6 @@ unsigned getMaxRVVVectorSizeInBits() const; unsigned getMinRVVVectorSizeInBits() const; unsigned getMaxLMULForFixedLengthVectors() const; - unsigned getMaxELENForFixedLengthVectors() const; bool useRVVForFixedLengthVectors() const; }; } // End llvm namespace diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -46,11 +46,6 @@ "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden); -static cl::opt RVVVectorELENMax( - "riscv-v-fixed-length-vector-elen-max", - cl::desc("The maximum ELEN value to use for fixed length vectors."), - cl::init(64), cl::Hidden); - static cl::opt RISCVDisableUsingConstantPoolForLargeInts( "riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), @@ -192,17 +187,6 @@ std::max(std::min(RVVVectorLMULMax, 8), 1)); } -unsigned RISCVSubtarget::getMaxELENForFixedLengthVectors() const { - assert(hasVInstructions() && - "Tried to get maximum ELEN without Zve or V extension support!"); - assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 && - isPowerOf2_32(RVVVectorELENMax) && - "V extension requires a ELEN to be a power of 2 between 8 and 64!"); - unsigned ELEN = hasVInstructionsI64() ? 64 : 32; - return PowerOf2Floor( - std::max(std::min(RVVVectorELENMax, ELEN), 8)); -} - bool RISCVSubtarget::useRVVForFixedLengthVectors() const { return hasVInstructions() && getMinRVVVectorSizeInBits() != 0; } diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -113,7 +113,7 @@ // Don't allow elements larger than the ELEN. // FIXME: How to limit for scalable vectors? if (isa(DataType) && - DataType->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors()) + DataType->getScalarSizeInBits() > ST->getELEN()) return false; if (Alignment < @@ -141,7 +141,7 @@ // Don't allow elements larger than the ELEN. // FIXME: How to limit for scalable vectors? if (isa(DataType) && - DataType->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors()) + DataType->getScalarSizeInBits() > ST->getELEN()) return false; if (Alignment < diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -230,8 +230,8 @@ return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); // Skip if element size of Dst or Src is bigger than ELEN. - if (Src->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors() || - Dst->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors()) + if (Src->getScalarSizeInBits() > ST->getELEN() || + Dst->getScalarSizeInBits() > ST->getELEN()) return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); int ISD = TLI->InstructionOpcodeToISD(Opcode); @@ -278,7 +278,7 @@ return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind); // Skip if scalar size of Ty is bigger than ELEN. - if (Ty->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors()) + if (Ty->getScalarSizeInBits() > ST->getELEN()) return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind); // IR Reduction is composed by two vmv and one rvv reduction instruction. @@ -304,7 +304,7 @@ return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind); // Skip if scalar size of VTy is bigger than ELEN. - if (VTy->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors()) + if (VTy->getScalarSizeInBits() > ST->getELEN()) return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind); int ISD = TLI->InstructionOpcodeToISD(Opcode); diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll @@ -5,13 +5,11 @@ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ ; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ -; RUN: -riscv-v-vector-bits-min=128 \ -; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ +; RUN: -riscv-v-vector-bits-min=128 -target-abi=ilp32d < %s \ ; RUN: | FileCheck %s --check-prefixes=ELEN32,RV32ELEN32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ -; RUN: -riscv-v-vector-bits-min=128 \ -; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ +; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \ ; RUN: | FileCheck %s --check-prefixes=ELEN32,RV64ELEN32 define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll @@ -1,10 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; Test that limiting ELEN, either through the command line or zve32, scalarizes +; Test that limiting ELEN, either through zve32, scalarizes ; elements larger than that and disables some fractional LMULs. ; This should use LMUL=1. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll @@ -8,12 +8,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8 ; Test with ELEN limited -; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN32 -; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN32 -; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN16 -; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN16 -; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN8 -; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN8 +; RUN: llc -mtriple=riscv32 -mattr=+f,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN32 +; RUN: llc -mtriple=riscv64 -mattr=+f,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN32 define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) { ; CHECK-LABEL: buildvec_mask_nonconst_v1i1: