Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -129,6 +129,15 @@ int &SPAdj); void insertPrologEpilogCode(MachineFunction &MF); void insertZeroCallUsedRegs(MachineFunction &MF); + + void removeRedundantAddrAnchors(MachineFunction &MF); + // Data structures to map regs to definitions per MBB. + typedef std::map Reg2DefMap; + typedef std::map MBB2RegDefsMap; + void visitBlock(MachineBasicBlock *MBB, + std::set &Visited, + std::list &Worklist, + MBB2RegDefsMap &RegDefs); }; } // end anonymous namespace @@ -269,6 +278,11 @@ if (TRI->requiresRegisterScavenging(MF) && FrameIndexVirtualScavenging) scavengeFrameVirtualRegs(MF, *RS); + // Remove redundant frame addressing anchor points created during Frame + // Indices elimination. + if (MF.getTarget().getOptLevel() != CodeGenOpt::None) + removeRedundantAddrAnchors(MF); + // Warn on stack size when we exceeds the given limit. MachineFrameInfo &MFI = MF.getFrameInfo(); uint64_t StackSize = MFI.getStackSize(); @@ -1442,3 +1456,196 @@ RS->forward(MI); } } + +#ifndef NDEBUG +// (Experimental) Only used to verify that all reachable MBBs were processed. +static void addSuccessors(MachineBasicBlock *MBB, + std::set &Visited) { + Visited.insert(MBB); + for (MachineBasicBlock *SuccMBB : MBB->successors()) + if (!Visited.count(SuccMBB)) + addSuccessors(SuccMBB, Visited); +} +static unsigned getNumReachableBlocks(MachineFunction &MF) { + std::set Visited; + addSuccessors(&MF.front(), Visited); + return Visited.size(); +} +#endif + +void PEI::removeRedundantAddrAnchors(MachineFunction &MF) { + // TODO: BreadthFirstIterator..? + std::set Visited; + std::list Worklist; + Worklist.push_back(&MF.front()); + MBB2RegDefsMap RegDefs; + auto allPredsVisited = [&Visited](MachineBasicBlock *MBB) { + for (MachineBasicBlock *Pred : MBB->predecessors()) + if (!Visited.count(Pred)) + return false; + return true; + }; + + // Try to visit all blocks in an order so that all predecessors of an MBB + // were visited before, in order to reuse definitions from them. + bool Change = true; + while (Change) { + Change = false; + for (auto &MBB : Worklist) + if (!Visited.count(MBB) && allPredsVisited(MBB)) { + visitBlock(MBB, Visited, Worklist, RegDefs); + Change = true; + } + if (!Change) + // TODO: Probably better to prioritize a loop header here. + for (auto &MBB : Worklist) + if (!Visited.count(MBB)) { + visitBlock(MBB, Visited, Worklist, RegDefs); + Change = true; + break; + } + } + + assert(Visited.size() == getNumReachableBlocks(MF) && + "Failed to visit all MBBs."); +} + +// Slow version for now: Update live-in lists and clear kill flags after each +// removal of a redundant definition. Not sure how important kill-flags are +// after PEI, but this clears them carefully on each user. TODO: This should +// probably be done after all else in a single pass instead to avoid +// unnecessary compile-time. +static void clearKillsForDef(MachineBasicBlock *MBB, + MachineBasicBlock::iterator I, + Register Reg, + MachineInstr *MI, + std::set &Visited, + const TargetRegisterInfo *TRI) { + Visited.insert(MBB); + // Clear kill flags on instructions before I in MBB, stopping at a + // definition of Reg, which should be an identical instruction. + while (I != MBB->begin()) { + I--; + if (I->modifiesRegister(Reg, TRI)) { + assert (I->isIdenticalTo(*MI) && "Broken redundancy assumption."); + return; + } + I->clearRegisterKills(Reg, TRI); + } + + // If earlier def is not in MBB, continue in predecessors. + if (!MBB->isLiveIn(Reg)) + MBB->addLiveIn(Reg); + assert(MBB->pred_size() && "Predecessor def not found!"); + for (MachineBasicBlock *Pred : MBB->predecessors()) + if (!Visited.count(Pred)) + clearKillsForDef(Pred, Pred->end(), Reg, MI, Visited, TRI); +} + +static void removeRedundantDef(MachineInstr *MI, + const TargetRegisterInfo *TRI) { + Register Reg = MI->getOperand(0).getReg(); + std::set Visited; + clearKillsForDef(MI->getParent(), MI->getIterator(), Reg, MI, Visited, TRI); + MI->eraseFromParent(); +} + +void PEI::visitBlock(MachineBasicBlock *MBB, + std::set &Visited, + std::list &Worklist, + MBB2RegDefsMap &RegDefs) { + Visited.insert(MBB); + + // Reuse definition in predecessor(s). + std::set PredRegs; + // Find set of all regs reusable from any predecessor. + for (MachineBasicBlock *Pred : MBB->predecessors()) + for (auto I : RegDefs[Pred]) + PredRegs.insert(I.first); + Reg2DefMap &MBBDefs = RegDefs[MBB]; + // Fill MBBDefs with reusable definitions if all predecessor definitions + // are present and identical. + for(auto Reg : PredRegs) { + MachineInstr *IdenticalDefMI = nullptr; + for (MachineBasicBlock *Pred : MBB->predecessors()) { + MachineInstr *PredDefMI = nullptr; + if (RegDefs[Pred].find(Reg) != RegDefs[Pred].end()) + PredDefMI = RegDefs[Pred][Reg]; + if (PredDefMI == nullptr || + (IdenticalDefMI != nullptr && + !IdenticalDefMI->isIdenticalTo(*PredDefMI))) { + IdenticalDefMI = nullptr; + break; + } + IdenticalDefMI = PredDefMI; + } + if (IdenticalDefMI != nullptr) { + MBBDefs[Reg] = IdenticalDefMI; + LLVM_DEBUG(dbgs() << "Reusable instruction from pred(s): in MBB#" + << MBB->getNumber() << ":"; IdenticalDefMI->dump();); + } + } + + // Process MBB. + MachineFunction *MF = MBB->getParent(); + const TargetRegisterInfo *TRI =MF->getSubtarget().getRegisterInfo(); + Register FrameReg = TRI->getFrameRegister(*MF); + for (MachineBasicBlock::iterator I = MBB->begin(); I != MBB->end();) { + MachineInstr *MI = &*(I++); + + // If the FrameReg is modified, no previous definitions (using it) can be + // reused. TODO: There seems to be many load immediate instructions that + // do not use FrameReg that could still be reused. + if (MI->modifiesRegister(FrameReg, TRI)) { + MBBDefs.clear(); + continue; + } + + // A candidate is a simple instruction that does not touch memory, has + // only one register definition and the only reg it may use is FrameReg. + Register DefedReg = 0; + bool Candidate = !(MI->mayStore() || MI->mayLoad() || MI->isCall() || + MI->isImplicitDef() || MI->isInlineAsm() || + MI->hasUnmodeledSideEffects()); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg()) { + if (MO.isDef()) { + if (i == 0 && !MO.isImplicit() && !MO.isDead()) + DefedReg = MO.getReg(); + else + Candidate = false; + } + else if (MO.getReg() && MO.getReg() != FrameReg) + Candidate = false; + } + else if (!MO.isImm()) + Candidate = false; + } + + if (Candidate && DefedReg && MBBDefs[DefedReg] != nullptr && + MBBDefs[DefedReg]->isIdenticalTo(*MI)) { + LLVM_DEBUG(dbgs() << "Removing redundant instruction in MBB#" + << MBB->getNumber() << ":"; MI->dump();); + removeRedundantDef(MI, TRI); + continue; + } + + // Clear any defs that MI clobbers. + for (auto DefI : MBBDefs) { + Register Reg = DefI.first; + if (MI->modifiesRegister(Reg, TRI)) + MBBDefs[Reg] = nullptr; + } + + if (Candidate && DefedReg) { + LLVM_DEBUG(dbgs() << "Found interesting instruction in MBB#" + << MBB->getNumber() << ":"; MI->dump();); + MBBDefs[DefedReg] = MI; + } + } + + // Add successors to worklist. + for (MachineBasicBlock *SuccMBB : MBB->successors()) + Worklist.push_back(SuccMBB); +} Index: llvm/test/CodeGen/AArch64/framelayout-sve.mir =================================================================== --- llvm/test/CodeGen/AArch64/framelayout-sve.mir +++ llvm/test/CodeGen/AArch64/framelayout-sve.mir @@ -266,10 +266,8 @@ # CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 # CHECK-NEXT: $[[TMP:x[0-9]+]] = ADDXri $sp, 16 -# CHECK-NEXT: STR_ZXI $z0, killed $[[TMP]], 2 -# CHECK-NEXT: $[[TMP:x[0-9]+]] = ADDXri $sp, 16 -# CHECK-NEXT: STR_ZXI $z1, killed $[[TMP]], 1 -# CHECK-NEXT: $[[TMP:x[0-9]+]] = ADDXri $sp, 16 +# CHECK-NEXT: STR_ZXI $z0, $[[TMP]], 2 +# CHECK-NEXT: STR_ZXI $z1, $[[TMP]], 1 # CHECK-NEXT: STR_PXI $p0, killed $[[TMP]], 7 # CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 3 Index: llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll =================================================================== --- llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll +++ llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll @@ -22,7 +22,6 @@ ; SUBOPTIMAL: // %bb.0: // %entry ; SUBOPTIMAL-NEXT: mov w8, #1 ; SUBOPTIMAL-NEXT: scvtf s0, w8 -; SUBOPTIMAL-NEXT: mov w8, #1 ; SUBOPTIMAL-NEXT: scvtf s1, w8 ; SUBOPTIMAL-NEXT: fcmp s0, s1 ; SUBOPTIMAL-NEXT: cset w8, eq @@ -50,7 +49,6 @@ ; SUBOPTIMAL: // %bb.0: // %entry ; SUBOPTIMAL-NEXT: mov w8, #1 ; SUBOPTIMAL-NEXT: scvtf s0, w8 -; SUBOPTIMAL-NEXT: mov w8, #1 ; SUBOPTIMAL-NEXT: ucvtf s1, w8 ; SUBOPTIMAL-NEXT: fcmp s0, s1 ; SUBOPTIMAL-NEXT: cset w8, eq Index: llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll +++ llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll @@ -43,26 +43,23 @@ ; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: add x9, sp, #16 +; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0] ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: fmov s0, #1.00000000 ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w1, #1 ; CHECK-NEXT: mov w2, #2 -; CHECK-NEXT: st1d { z16.d }, p0, [x9] -; CHECK-NEXT: add x9, sp, #16 ; CHECK-NEXT: mov w3, #3 ; CHECK-NEXT: mov w4, #4 ; CHECK-NEXT: mov w5, #5 ; CHECK-NEXT: mov w6, #6 -; CHECK-NEXT: st1d { z17.d }, p0, [x9, #1, mul vl] -; CHECK-NEXT: add x9, sp, #16 ; CHECK-NEXT: mov w7, #7 -; CHECK-NEXT: st1d { z18.d }, p0, [x9, #2, mul vl] ; CHECK-NEXT: add x9, sp, #16 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: st1d { z16.d }, p0, [x9] +; CHECK-NEXT: st1d { z17.d }, p0, [x9, #1, mul vl] +; CHECK-NEXT: st1d { z18.d }, p0, [x9, #2, mul vl] ; CHECK-NEXT: st1d { z19.d }, p0, [x9, #3, mul vl] ; CHECK-NEXT: str x8, [sp] ; CHECK-NEXT: bl callee2 Index: llvm/test/CodeGen/AArch64/sve-ld1r.mir =================================================================== --- llvm/test/CodeGen/AArch64/sve-ld1r.mir +++ llvm/test/CodeGen/AArch64/sve-ld1r.mir @@ -35,27 +35,28 @@ ; CHECK-LABEL: name: testcase_positive_offset ; CHECK: liveins: $p0 - ; CHECK: $sp = frame-setup SUBXri $sp, 16, 0 - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: renamable $z0 = LD1RB_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RB_H_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RB_S_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RB_D_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RSB_H_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RSB_S_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RSB_D_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: renamable $z0 = LD1RH_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) - ; CHECK: renamable $z0 = LD1RH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) - ; CHECK: renamable $z0 = LD1RH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) - ; CHECK: renamable $z0 = LD1RSH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) - ; CHECK: renamable $z0 = LD1RSH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) - ; CHECK: renamable $z0 = LD1RW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) - ; CHECK: renamable $z0 = LD1RW_D_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) - ; CHECK: renamable $z0 = LD1RSW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object) - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object) - ; CHECK: $sp = frame-destroy ADDXri $sp, 16, 0 - ; CHECK: RET_ReallyLR implicit $z0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: renamable $z0 = LD1RB_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_H_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_S_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_D_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_H_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_S_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_D_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RH_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RW_D_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object) + ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 16, 0 + ; CHECK-NEXT: RET_ReallyLR implicit $z0 renamable $z0 = LD1RB_IMM renamable $p0, %stack.1.object, 63 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_H_IMM renamable $p0, %stack.1.object, 63 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_S_IMM renamable $p0, %stack.1.object, 63 :: (load 1 from %ir.object, align 2) @@ -87,44 +88,32 @@ ; CHECK-LABEL: name: testcase_positive_offset_out_of_range ; CHECK: liveins: $p0 - ; CHECK: $sp = frame-setup SUBXri $sp, 16, 0 - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_H_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_S_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_D_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_H_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_S_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_D_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = ADDXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_S_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_D_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RSH_S_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RSH_D_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RW_IMM renamable $p0, killed $x8, 63 :: (load (s32) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RW_D_IMM renamable $p0, killed $x8, 63 :: (load (s32) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RSW_IMM renamable $p0, killed $x8, 63 :: (load (s32) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 8, 0 - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 63 :: (load (s64) from %ir.object) - ; CHECK: $x8 = ADDXri $sp, 8, 0 - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 63 :: (load (s64) from %ir.object) - ; CHECK: $sp = frame-destroy ADDXri $sp, 16, 0 - ; CHECK: RET_ReallyLR implicit $z0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: $x8 = ADDXri $sp, 1, 0 + ; CHECK-NEXT: renamable $z0 = LD1RB_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_H_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_S_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_D_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_H_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_S_IMM renamable $p0, $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_D_IMM renamable $p0, killed $x8, 63 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: $x8 = ADDXri $sp, 2, 0 + ; CHECK-NEXT: renamable $z0 = LD1RH_IMM renamable $p0, $x8, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_S_IMM renamable $p0, $x8, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_D_IMM renamable $p0, $x8, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_S_IMM renamable $p0, $x8, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_D_IMM renamable $p0, killed $x8, 63 :: (load (s16) from %ir.object) + ; CHECK-NEXT: $x8 = ADDXri $sp, 4, 0 + ; CHECK-NEXT: renamable $z0 = LD1RW_IMM renamable $p0, $x8, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RW_D_IMM renamable $p0, $x8, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSW_IMM renamable $p0, killed $x8, 63 :: (load (s32) from %ir.object) + ; CHECK-NEXT: $x8 = ADDXri $sp, 8, 0 + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, $x8, 63 :: (load (s64) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 63 :: (load (s64) from %ir.object) + ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 16, 0 + ; CHECK-NEXT: RET_ReallyLR implicit $z0 renamable $z0 = LD1RB_IMM renamable $p0, %stack.1.object, 64 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_H_IMM renamable $p0, %stack.1.object, 64 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_S_IMM renamable $p0, %stack.1.object, 64 :: (load 1 from %ir.object, align 2) @@ -158,44 +147,32 @@ ; CHECK-LABEL: name: testcase_negative_offset_out_of_range ; CHECK: liveins: $p0 - ; CHECK: $sp = frame-setup SUBXri $sp, 16, 0 - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_H_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_S_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RB_D_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_H_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_S_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 1, 0 - ; CHECK: renamable $z0 = LD1RSB_D_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) - ; CHECK: $x8 = SUBXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_S_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RH_D_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RSH_S_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 2, 0 - ; CHECK: renamable $z0 = LD1RSH_D_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RW_IMM renamable $p0, killed $x8, 0 :: (load (s32) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RW_D_IMM renamable $p0, killed $x8, 0 :: (load (s32) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 4, 0 - ; CHECK: renamable $z0 = LD1RSW_IMM renamable $p0, killed $x8, 0 :: (load (s32) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 8, 0 - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 0 :: (load (s64) from %ir.object) - ; CHECK: $x8 = SUBXri $sp, 8, 0 - ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 0 :: (load (s64) from %ir.object) - ; CHECK: $sp = frame-destroy ADDXri $sp, 16, 0 - ; CHECK: RET_ReallyLR implicit $z0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: $x8 = SUBXri $sp, 1, 0 + ; CHECK-NEXT: renamable $z0 = LD1RB_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_H_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_S_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RB_D_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_H_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_S_IMM renamable $p0, $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LD1RSB_D_IMM renamable $p0, killed $x8, 0 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: $x8 = SUBXri $sp, 2, 0 + ; CHECK-NEXT: renamable $z0 = LD1RH_IMM renamable $p0, $x8, 0 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_S_IMM renamable $p0, $x8, 0 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RH_D_IMM renamable $p0, $x8, 0 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_S_IMM renamable $p0, $x8, 0 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSH_D_IMM renamable $p0, killed $x8, 0 :: (load (s16) from %ir.object) + ; CHECK-NEXT: $x8 = SUBXri $sp, 4, 0 + ; CHECK-NEXT: renamable $z0 = LD1RW_IMM renamable $p0, $x8, 0 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RW_D_IMM renamable $p0, $x8, 0 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RSW_IMM renamable $p0, killed $x8, 0 :: (load (s32) from %ir.object) + ; CHECK-NEXT: $x8 = SUBXri $sp, 8, 0 + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, $x8, 0 :: (load (s64) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LD1RD_IMM renamable $p0, killed $x8, 0 :: (load (s64) from %ir.object) + ; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 16, 0 + ; CHECK-NEXT: RET_ReallyLR implicit $z0 renamable $z0 = LD1RB_IMM renamable $p0, %stack.1.object, -1 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_H_IMM renamable $p0, %stack.1.object, -1 :: (load 1 from %ir.object, align 2) renamable $z0 = LD1RB_S_IMM renamable $p0, %stack.1.object, -1 :: (load 1 from %ir.object, align 2) Index: llvm/test/CodeGen/AArch64/sve-ldstnt1.mir =================================================================== --- llvm/test/CodeGen/AArch64/sve-ldstnt1.mir +++ llvm/test/CodeGen/AArch64/sve-ldstnt1.mir @@ -135,20 +135,13 @@ ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, killed $x8, 7 :: (load (s64) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s8) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s16) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 - ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s32) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1 + ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, $x8, 7 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $x8, 7 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, $x8, 7 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $x8, 7 :: (load (s64) from %ir.object) + ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, $x8, 7 :: (store (s8) into %ir.object, align 8) + ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, $x8, 7 :: (store (s16) into %ir.object, align 8) + ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $x8, 7 :: (store (s32) into %ir.object, align 8) ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s64) into %ir.object) ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4 ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16 @@ -186,20 +179,13 @@ ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, killed $x8, -8 :: (load (s64) from %ir.object) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s8) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s16) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 - ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s32) into %ir.object, align 8) - ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1 + ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, $x8, -8 :: (load (s8) from %ir.object, align 2) + ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $x8, -8 :: (load (s16) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, $x8, -8 :: (load (s32) from %ir.object) + ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $x8, -8 :: (load (s64) from %ir.object) + ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, $x8, -8 :: (store (s8) into %ir.object, align 8) + ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, $x8, -8 :: (store (s16) into %ir.object, align 8) + ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $x8, -8 :: (store (s32) into %ir.object, align 8) ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s64) into %ir.object) ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4 ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll @@ -158,50 +158,29 @@ ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:8 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:72 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:16 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:80 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:24 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:88 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:32 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:96 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:40 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:104 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:48 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:112 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:56 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 -; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:120 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:64 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:72 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:80 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:88 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:96 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:104 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:112 +; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:120 ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:128 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s33 offset:8 -; FLATSCR-NEXT: s_mov_b32 s33, 0 +; FLATSCR-NEXT: s_nop 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s33 offset:16 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s33 offset:24 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[6:7], off, s33 offset:32 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s33 offset:40 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s33 offset:48 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[12:13], off, s33 offset:56 -; FLATSCR-NEXT: s_mov_b32 s33, 0 ; FLATSCR-NEXT: scratch_load_dwordx2 v[14:15], off, s33 offset:64 ; FLATSCR-NEXT: s_movk_i32 s32, 0x50 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] Index: llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll @@ -499,7 +499,6 @@ ; GFX940-NEXT: scratch_store_dword v1, v0, vcc_hi sc0 sc1 ; GFX940-NEXT: s_waitcnt vmcnt(0) ; GFX940-NEXT: v_mov_b32_e32 v0, s0 -; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004 ; GFX940-NEXT: scratch_load_dword v0, v0, vcc_hi sc0 sc1 ; GFX940-NEXT: s_waitcnt vmcnt(0) ; GFX940-NEXT: s_endpgm @@ -572,7 +571,6 @@ ; GFX940-NEXT: scratch_store_dword v1, v2, vcc_hi sc0 sc1 ; GFX940-NEXT: s_waitcnt vmcnt(0) ; GFX940-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004 ; GFX940-NEXT: scratch_load_dword v0, v0, vcc_hi offset:124 sc0 sc1 ; GFX940-NEXT: s_waitcnt vmcnt(0) ; GFX940-NEXT: s_endpgm Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll @@ -946,7 +946,6 @@ ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: buffer_load_dwordx3 v[1:3], v[1:2], s[4:7], 0 addr64 ; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 -; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX7-NEXT: s_cbranch_execz .LBB13_2 Index: llvm/test/CodeGen/AMDGPU/cc-update.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/cc-update.ll +++ llvm/test/CodeGen/AMDGPU/cc-update.ll @@ -410,7 +410,6 @@ ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill ; GFX803-NEXT: ;;#ASMSTART ; GFX803-NEXT: ;;#ASMEND -; GFX803-NEXT: s_mov_b32 s4, 0x40000 ; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 @@ -427,7 +426,6 @@ ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: s_mov_b32 s4, 0x40000 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 @@ -442,8 +440,6 @@ ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc dlc ; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill -; GFX1010-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-NEXT: s_mov_b32 s4, 0x20000 ; GFX1010-NEXT: ;;#ASMSTART ; GFX1010-NEXT: ;;#ASMEND ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload Index: llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll +++ llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll @@ -399,18 +399,14 @@ ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:4 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:2 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:6 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:4 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:8 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 -; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: scratch_load_dword v1, off, vcc_hi offset:6 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] @@ -463,22 +459,15 @@ ; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:4 ; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1] offset:2 -; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3 -; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0) ; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:6 ; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1] offset:4 -; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3 -; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0) ; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:8 ; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3 -; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0 +; FLATSCR_GFX10-NEXT: s_clause 0x1 ; FLATSCR_GFX10-NEXT: scratch_load_dword v0, off, vcc_lo offset:4 -; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3 -; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0 ; FLATSCR_GFX10-NEXT: scratch_load_dword v1, off, vcc_lo offset:6 ; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0) ; FLATSCR_GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] Index: llvm/test/CodeGen/AMDGPU/flat-scratch.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/flat-scratch.ll +++ llvm/test/CodeGen/AMDGPU/flat-scratch.ll @@ -21,11 +21,8 @@ ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:64 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-NEXT: s_endpgm ; @@ -68,11 +65,8 @@ ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:64 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-PAL-NEXT: s_endpgm ; @@ -111,14 +105,8 @@ ; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:64 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 ; GFX1010-PAL-NEXT: s_endpgm ; @@ -786,13 +774,9 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304 -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320 ; GFX9-NEXT: s_endpgm ; @@ -838,13 +822,9 @@ ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304 -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320 ; GFX9-PAL-NEXT: s_endpgm ; @@ -886,16 +866,9 @@ ; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:272 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:288 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:304 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:320 ; GFX1010-PAL-NEXT: s_endpgm ; @@ -1635,11 +1608,8 @@ ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi -; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 -; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 -; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX9-NEXT: s_endpgm ; @@ -1661,11 +1631,8 @@ ; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo -; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 -; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 -; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 ; GFX10-NEXT: s_endpgm ; @@ -1691,11 +1658,8 @@ ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi -; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 -; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 -; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX9-PAL-NEXT: s_endpgm ; @@ -1711,11 +1675,8 @@ ; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3] ; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi -; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 -; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 -; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX940-NEXT: s_endpgm ; @@ -1743,14 +1704,8 @@ ; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 -; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3 -; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 ; GFX1010-PAL-NEXT: s_endpgm ; @@ -1777,11 +1732,8 @@ ; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1030-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo -; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 -; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 -; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 ; GFX1030-PAL-NEXT: s_endpgm %padding = alloca [4096 x i32], align 4, addrspace(5) @@ -3325,7 +3277,6 @@ ; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:3024 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: scratch_load_dwordx4 v[0:3], off, vcc_hi offset:3024 glc ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, 16 @@ -3380,7 +3331,6 @@ ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:3024 ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) -; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, vcc_hi offset:3024 glc ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 16 Index: llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll +++ llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll @@ -300,7 +300,6 @@ ; FLATSCR-NEXT: s_movk_i32 s2, 0x2000 ; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s2 offset:16 glc ; FLATSCR-NEXT: s_waitcnt vmcnt(0) -; FLATSCR-NEXT: s_movk_i32 s2, 0x2000 ; FLATSCR-NEXT: scratch_load_dwordx4 v[4:7], off, s2 glc ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: v_mov_b32_e32 v12, 0 Index: llvm/test/CodeGen/AMDGPU/multilevel-break.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/multilevel-break.ll +++ llvm/test/CodeGen/AMDGPU/multilevel-break.ll @@ -184,7 +184,6 @@ ; GCN-NEXT: ; %bb.3: ; %LeafBlock1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: s_mov_b64 s[4:5], -1 ; GCN-NEXT: s_cbranch_vccz .LBB1_5 ; GCN-NEXT: ; %bb.4: ; %case1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 Index: llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll +++ llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll @@ -203,13 +203,10 @@ ; SI-NEXT: s_cbranch_vccz .LBB3_3 ; SI-NEXT: ; %bb.5: ; %convex.exit ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 -; SI-NEXT: s_mov_b64 s[8:9], -1 -; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 vcc, s[2:3] ; SI-NEXT: s_cbranch_vccz .LBB3_2 ; SI-NEXT: ; %bb.6: ; %if.end ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 -; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 vcc, s[4:5] ; SI-NEXT: s_cbranch_vccz .LBB3_1 ; SI-NEXT: ; %bb.7: ; %if.else @@ -278,13 +275,10 @@ ; FLAT-NEXT: s_cbranch_vccz .LBB3_3 ; FLAT-NEXT: ; %bb.5: ; %convex.exit ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 -; FLAT-NEXT: s_mov_b64 s[8:9], -1 -; FLAT-NEXT: s_mov_b64 s[10:11], -1 ; FLAT-NEXT: s_mov_b64 vcc, s[2:3] ; FLAT-NEXT: s_cbranch_vccz .LBB3_2 ; FLAT-NEXT: ; %bb.6: ; %if.end ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 -; FLAT-NEXT: s_mov_b64 s[10:11], -1 ; FLAT-NEXT: s_mov_b64 vcc, s[4:5] ; FLAT-NEXT: s_cbranch_vccz .LBB3_1 ; FLAT-NEXT: ; %bb.7: ; %if.else Index: llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll +++ llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll @@ -150,7 +150,6 @@ ; MUBUF: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1004 ; MUBUF: buffer_load_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+:[0-9]+}}], 0 offen ; 4-byte Folded Reload - ; FLATSCR: s_movk_i32 [[SOFF:s[0-9]+]], 0x1004 ; FLATSCR: scratch_load_dword v{{[0-9]+}}, off, [[SOFF]] ; 4-byte Folded Reload ; Force %a to spill with no free SGPRs Index: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -115,8 +115,7 @@ ; FLATSCR: s_movk_i32 [[SOFF1:s[0-9]+]], 0x ; GFX9-FLATSCR: s_waitcnt vmcnt(0) ; FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SOFF1]] ; 16-byte Folded Spill -; FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x -; FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, [[SOFF2]] ; 16-byte Folded Reload +; FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, [[SOFF1]] ; 16-byte Folded Reload define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 { entry: %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) Index: llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll =================================================================== --- llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll +++ llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -1652,7 +1652,6 @@ ; THUMB-ENABLE-NEXT: movs r0, #0 ; THUMB-ENABLE-NEXT: cbnz r0, LBB11_5 ; THUMB-ENABLE-NEXT: @ %bb.1: @ %loop2a.preheader -; THUMB-ENABLE-NEXT: movs r0, #0 ; THUMB-ENABLE-NEXT: movs r1, #0 ; THUMB-ENABLE-NEXT: mov r2, r0 ; THUMB-ENABLE-NEXT: b LBB11_3 @@ -1679,7 +1678,6 @@ ; THUMB-DISABLE-NEXT: movs r0, #0 ; THUMB-DISABLE-NEXT: cbnz r0, LBB11_5 ; THUMB-DISABLE-NEXT: @ %bb.1: @ %loop2a.preheader -; THUMB-DISABLE-NEXT: movs r0, #0 ; THUMB-DISABLE-NEXT: movs r1, #0 ; THUMB-DISABLE-NEXT: mov r2, r0 ; THUMB-DISABLE-NEXT: b LBB11_3 Index: llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll =================================================================== --- llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll +++ llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll @@ -22,7 +22,7 @@ ; for.body -> for.cond.backedge (100%) ; -> cond.false.i (0%) ; CHECK: bb.1.for.body: -; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000000) +; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000) for.body: br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1 Index: llvm/test/CodeGen/ARM/machine-outliner-calls.mir =================================================================== --- llvm/test/CodeGen/ARM/machine-outliner-calls.mir +++ llvm/test/CodeGen/ARM/machine-outliner-calls.mir @@ -21,23 +21,47 @@ body: | ; CHECK-LABEL: name: outline_call_arm ; CHECK: bb.0: - ; CHECK: liveins: $r4, $lr - ; CHECK: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: BL @OUTLINED_FUNCTION_0 - ; CHECK: bb.1: - ; CHECK: BL @OUTLINED_FUNCTION_0 - ; CHECK: bb.2: - ; CHECK: BL @OUTLINED_FUNCTION_0 - ; CHECK: bb.3: - ; CHECK: BL @OUTLINED_FUNCTION_0 - ; CHECK: bb.4: - ; CHECK: BL @OUTLINED_FUNCTION_0 - ; CHECK: bb.5: - ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr - ; CHECK: BX_RET 14 /* CC::al */, $noreg + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r4, $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg bb.0: BL @bar, implicit-def dead $lr, implicit $sp $r0 = MOVi 1, 14, $noreg, $noreg @@ -83,22 +107,44 @@ body: | ; CHECK-LABEL: name: outline_call_thumb ; CHECK: bb.0: - ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4 - ; CHECK: bb.1: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4 - ; CHECK: bb.2: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4 - ; CHECK: bb.3: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4 - ; CHECK: bb.4: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4 - ; CHECK: bb.5: - ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r7, $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc bb.0: tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp $r0 = t2MOVi 1, 14, $noreg, $noreg @@ -134,21 +180,45 @@ body: | ; CHECK-LABEL: name: outline_call_tailcall_arm ; CHECK: bb.0: - ; CHECK: liveins: $r4, $lr - ; CHECK: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: BL @OUTLINED_FUNCTION_1 - ; CHECK: bb.1: - ; CHECK: BL @OUTLINED_FUNCTION_1 - ; CHECK: bb.2: - ; CHECK: BL @OUTLINED_FUNCTION_1 - ; CHECK: bb.3: - ; CHECK: BL @OUTLINED_FUNCTION_1 - ; CHECK: bb.4: - ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr - ; CHECK: BX_RET 14 /* CC::al */, $noreg + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r4, $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: $r0 = MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r2 = MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r3 = MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r4 = MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg bb.0: BL @bar, implicit-def dead $lr, implicit $sp $r0 = MOVi 2, 14, $noreg, $noreg @@ -191,20 +261,42 @@ body: | ; CHECK-LABEL: name: outline_call_tailcall_thumb ; CHECK: bb.0: - ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3 - ; CHECK: bb.1: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3 - ; CHECK: bb.2: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3 - ; CHECK: bb.3: - ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3 - ; CHECK: bb.4: - ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r7, $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: $r0 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r1 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r2 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc bb.0: tBL 14, $noreg, @bar, implicit-def dead $lr, implicit $sp $r0 = t2MOVi 2, 14, $noreg, $noreg @@ -239,28 +331,43 @@ body: | ; CHECK-LABEL: name: outline_call_KO_mcount ; CHECK: bb.0: - ; CHECK: liveins: $r4, $lr - ; CHECK: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 - ; CHECK: bb.1: - ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 - ; CHECK: bb.2: - ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 - ; CHECK: bb.3: - ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 - ; CHECK: bb.4: - ; CHECK: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp - ; CHECK: BL @OUTLINED_FUNCTION_2 - ; CHECK: bb.5: - ; CHECK: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr - ; CHECK: BX_RET 14 /* CC::al */, $noreg + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r4, $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, implicit-def $r4, implicit $noreg, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, implicit-def $r4, implicit $noreg, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, implicit-def $r4, implicit $noreg, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, implicit-def $r4, implicit $noreg, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp + ; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, implicit-def $lr, implicit $sp, implicit-def $lr, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, implicit-def $r4, implicit $noreg, implicit $sp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $sp = frame-destroy LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $lr + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg bb.0: BL @"\01mcount", csr_aapcs, implicit-def dead $lr, implicit $sp $r0 = MOVi 3, 14, $noreg, $noreg @@ -305,74 +412,15 @@ tracksRegLiveness: true body: | bb.0: + ; CHECK-LABEL: name: bar + ; CHECK: BX_RET 14 /* CC::al */, $noreg BX_RET 14, $noreg - ; CHECK-LABEL: name: OUTLINED_FUNCTION_0 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: BL @bar, implicit-def dead $lr, implicit $sp - ; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg - ; CHECK: MOVPCLR 14 /* CC::al */, $noreg - ; CHECK-LABEL: name: OUTLINED_FUNCTION_1 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: BL @bar, implicit-def dead $lr, implicit $sp - ; CHECK: $r0 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r3 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy LDR_POST_IMM $sp, $noreg, 8, 14 /* CC::al */, $noreg - ; CHECK: TAILJMPd @bar, implicit $sp - ; CHECK-LABEL: name: OUTLINED_FUNCTION_2 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8 - ; CHECK: $r0 = MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r3 = MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: MOVPCLR 14 /* CC::al */, $noreg - ; CHECK-LABEL: name: OUTLINED_FUNCTION_3 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp - ; CHECK: $r0 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg - ; CHECK: tTAILJMPdND @bar, 14 /* CC::al */, $noreg, implicit $sp - ; CHECK-LABEL: name: OUTLINED_FUNCTION_4 - ; CHECK: bb.0: - ; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8 - ; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp - ; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg - ; CHECK: tBX_RET 14 /* CC::al */, $noreg Index: llvm/test/CodeGen/ARM/reg_sequence.ll =================================================================== --- llvm/test/CodeGen/ARM/reg_sequence.ll +++ llvm/test/CodeGen/ARM/reg_sequence.ll @@ -283,7 +283,6 @@ ; CHECK-NEXT: vst1.32 {d17[1]}, [r0:32] ; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: bxne lr ; CHECK-NEXT: LBB9_1: ; CHECK-NEXT: trap Index: llvm/test/CodeGen/BPF/objdump_cond_op_2.ll =================================================================== --- llvm/test/CodeGen/BPF/objdump_cond_op_2.ll +++ llvm/test/CodeGen/BPF/objdump_cond_op_2.ll @@ -14,9 +14,8 @@ ;