Index: lib/CodeGen/AtomicExpandPass.cpp =================================================================== --- lib/CodeGen/AtomicExpandPass.cpp +++ lib/CodeGen/AtomicExpandPass.cpp @@ -551,6 +551,7 @@ LoadInst *InitLoaded = Builder.CreateLoad(Addr); // Atomics require at least natural alignment. InitLoaded->setAlignment(AI->getType()->getPrimitiveSizeInBits() / 8); + InitLoaded->setOrdering(AtomicCmpXchgInst::getStrongestFailureOrdering(MemOpOrder)); Builder.CreateBr(LoopBB); // Start the main loop block now that we've taken care of the preliminaries. Index: test/CodeGen/X86/2010-01-08-Atomic64Bug.ll =================================================================== --- test/CodeGen/X86/2010-01-08-Atomic64Bug.ll +++ test/CodeGen/X86/2010-01-08-Atomic64Bug.ll @@ -7,8 +7,8 @@ define void @t(i64* nocapture %p) nounwind ssp { entry: ; CHECK-LABEL: t: -; CHECK: movl ([[REG:%[a-z]+]]), %eax -; CHECK: movl 4([[REG]]), %edx +; CHECK: movl 12({{%[a-z]+}}), [[REG:%[a-z]+]] +; CHECK: lock cmpxchg8b ([[REG]]) ; CHECK: LBB0_1: ; CHECK: movl %eax, %ebx ; CHECK: addl $1, %ebx Index: test/CodeGen/X86/atomic-load-store-wide.ll =================================================================== --- test/CodeGen/X86/atomic-load-store-wide.ll +++ test/CodeGen/X86/atomic-load-store-wide.ll @@ -6,6 +6,7 @@ define void @test1(i64* %ptr, i64 %val1) { ; CHECK-LABEL: test1 ; CHECK: lock cmpxchg8b +; CHECK: lock cmpxchg8b ; CHECK-NEXT: jne store atomic i64 %val1, i64* %ptr seq_cst, align 8 ret void Index: test/CodeGen/X86/atomic-minmax-i6432.ll =================================================================== --- test/CodeGen/X86/atomic-minmax-i6432.ll +++ test/CodeGen/X86/atomic-minmax-i6432.ll @@ -45,8 +45,7 @@ define void @tf_bug(i8* %ptr) nounwind { ; PIC-LABEL: tf_bug: -; PIC-DAG: movl _id-L1$pb( -; PIC-DAG: movl (_id-L1$pb)+4( +; PIC-DAG: lock cmpxchg8b _id-L1$pb( %tmp1 = atomicrmw add i64* @id, i64 1 seq_cst %tmp2 = add i64 %tmp1, 1 %tmp3 = bitcast i8* %ptr to i64* Index: test/CodeGen/X86/atomic128.ll =================================================================== --- test/CodeGen/X86/atomic128.ll +++ test/CodeGen/X86/atomic128.ll @@ -18,8 +18,7 @@ define void @fetch_and_nand(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_nand: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: movq %rdx, %rcx @@ -43,8 +42,7 @@ define void @fetch_and_or(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_or: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: movq %rax, %rbx @@ -67,8 +65,7 @@ define void @fetch_and_add(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_add: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: movq %rax, %rbx @@ -91,8 +88,7 @@ define void @fetch_and_sub(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_sub: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: movq %rax, %rbx @@ -115,8 +111,7 @@ define void @fetch_and_min(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_min: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: cmpq %rsi, %rax @@ -147,8 +142,7 @@ define void @fetch_and_max(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_max: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: cmpq %rsi, %rax @@ -179,8 +173,7 @@ define void @fetch_and_umin(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_umin: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: cmpq %rsi, %rax @@ -211,8 +204,7 @@ define void @fetch_and_umax(i128* %p, i128 %bits) { ; CHECK-LABEL: fetch_and_umax: ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]] -; CHECK-DAG: movq (%rdi), %rax -; CHECK-DAG: movq 8(%rdi), %rdx +; CHECK-DAG: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: cmpq %rax, %rsi @@ -268,10 +260,8 @@ define void @atomic_store_seq_cst(i128* %p, i128 %in) { ; CHECK-LABEL: atomic_store_seq_cst: -; CHECK: movq %rdx, %rcx -; CHECK: movq %rsi, %rbx -; CHECK: movq (%rdi), %rax -; CHECK: movq 8(%rdi), %rdx +; CHECK: movq %rdx, %r8 +; CHECK: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: lock @@ -285,10 +275,8 @@ define void @atomic_store_release(i128* %p, i128 %in) { ; CHECK-LABEL: atomic_store_release: -; CHECK: movq %rdx, %rcx -; CHECK: movq %rsi, %rbx -; CHECK: movq (%rdi), %rax -; CHECK: movq 8(%rdi), %rdx +; CHECK: movq %rdx, %r8 +; CHECK: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: lock @@ -301,10 +289,8 @@ define void @atomic_store_relaxed(i128* %p, i128 %in) { ; CHECK-LABEL: atomic_store_relaxed: -; CHECK: movq %rdx, %rcx -; CHECK: movq %rsi, %rbx -; CHECK: movq (%rdi), %rax -; CHECK: movq 8(%rdi), %rdx +; CHECK: movq %rdx, %r8 +; CHECK: lock cmpxchg16b (%rdi) ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]: ; CHECK: lock Index: test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll =================================================================== --- test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll +++ test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll @@ -8,4 +8,4 @@ ret i8 %res } ; CHECK-LABEL: @test_initial_load -; CHECK-NEXT: %1 = load i8, i8* %ptr, align 1 +; CHECK-NEXT: %1 = load atomic i8, i8* %ptr seq_cst, align 1