diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -776,11 +776,13 @@ } // (srli (slli x, c3-c2), c3). - // Skip it in order to select sraiw. + // Skip if we could use (zext.w (sraiw X, C2)). bool Skip = Subtarget->hasStdExtZba() && C3 == 32 && X.getOpcode() == ISD::SIGN_EXTEND_INREG && cast(X.getOperand(1))->getVT() == MVT::i32; - if (OneUseOrZExtW && !IsCANDI && !Skip) { + // Also Skip if we can use bexti. + Skip |= Subtarget->hasStdExtZbs() && C3 == XLen - 1; + if (OneUseOrZExtW && !Skip) { SDNode *SLLI = CurDAG->getMachineNode( RISCV::SLLI, DL, XLenVT, X, CurDAG->getTargetConstant(C3 - C2, DL, XLenVT)); diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll --- a/llvm/test/CodeGen/RISCV/div-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll @@ -526,8 +526,8 @@ ; RV32IM-NEXT: li a1, 86 ; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: srli a1, a0, 8 -; RV32IM-NEXT: srli a0, a0, 15 -; RV32IM-NEXT: andi a0, a0, 1 +; RV32IM-NEXT: slli a0, a0, 16 +; RV32IM-NEXT: srli a0, a0, 31 ; RV32IM-NEXT: add a0, a1, a0 ; RV32IM-NEXT: ret ; @@ -537,8 +537,8 @@ ; RV32IMZB-NEXT: li a1, 86 ; RV32IMZB-NEXT: mul a0, a0, a1 ; RV32IMZB-NEXT: srli a1, a0, 8 -; RV32IMZB-NEXT: srli a0, a0, 15 -; RV32IMZB-NEXT: andi a0, a0, 1 +; RV32IMZB-NEXT: slli a0, a0, 16 +; RV32IMZB-NEXT: srli a0, a0, 31 ; RV32IMZB-NEXT: add a0, a1, a0 ; RV32IMZB-NEXT: ret ; @@ -549,8 +549,8 @@ ; RV64IM-NEXT: li a1, 86 ; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: srli a1, a0, 8 -; RV64IM-NEXT: srli a0, a0, 15 -; RV64IM-NEXT: andi a0, a0, 1 +; RV64IM-NEXT: slli a0, a0, 48 +; RV64IM-NEXT: srli a0, a0, 63 ; RV64IM-NEXT: add a0, a1, a0 ; RV64IM-NEXT: ret ; @@ -560,8 +560,8 @@ ; RV64IMZB-NEXT: li a1, 86 ; RV64IMZB-NEXT: mul a0, a0, a1 ; RV64IMZB-NEXT: srli a1, a0, 8 -; RV64IMZB-NEXT: srli a0, a0, 15 -; RV64IMZB-NEXT: andi a0, a0, 1 +; RV64IMZB-NEXT: slli a0, a0, 48 +; RV64IMZB-NEXT: srli a0, a0, 63 ; RV64IMZB-NEXT: add a0, a1, a0 ; RV64IMZB-NEXT: ret %1 = sdiv i8 %a, 3 @@ -576,8 +576,8 @@ ; RV32IM-NEXT: li a1, 103 ; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: srai a1, a0, 9 -; RV32IM-NEXT: srli a0, a0, 15 -; RV32IM-NEXT: andi a0, a0, 1 +; RV32IM-NEXT: slli a0, a0, 16 +; RV32IM-NEXT: srli a0, a0, 31 ; RV32IM-NEXT: add a0, a1, a0 ; RV32IM-NEXT: ret ; @@ -587,8 +587,8 @@ ; RV32IMZB-NEXT: li a1, 103 ; RV32IMZB-NEXT: mul a0, a0, a1 ; RV32IMZB-NEXT: srai a1, a0, 9 -; RV32IMZB-NEXT: srli a0, a0, 15 -; RV32IMZB-NEXT: andi a0, a0, 1 +; RV32IMZB-NEXT: slli a0, a0, 16 +; RV32IMZB-NEXT: srli a0, a0, 31 ; RV32IMZB-NEXT: add a0, a1, a0 ; RV32IMZB-NEXT: ret ; @@ -599,8 +599,8 @@ ; RV64IM-NEXT: li a1, 103 ; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: srai a1, a0, 9 -; RV64IM-NEXT: srli a0, a0, 15 -; RV64IM-NEXT: andi a0, a0, 1 +; RV64IM-NEXT: slli a0, a0, 48 +; RV64IM-NEXT: srli a0, a0, 63 ; RV64IM-NEXT: add a0, a1, a0 ; RV64IM-NEXT: ret ; @@ -610,8 +610,8 @@ ; RV64IMZB-NEXT: li a1, 103 ; RV64IMZB-NEXT: mul a0, a0, a1 ; RV64IMZB-NEXT: srai a1, a0, 9 -; RV64IMZB-NEXT: srli a0, a0, 15 -; RV64IMZB-NEXT: andi a0, a0, 1 +; RV64IMZB-NEXT: slli a0, a0, 48 +; RV64IMZB-NEXT: srli a0, a0, 63 ; RV64IMZB-NEXT: add a0, a1, a0 ; RV64IMZB-NEXT: ret %1 = sdiv i8 %a, 5 diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll --- a/llvm/test/CodeGen/RISCV/div.ll +++ b/llvm/test/CodeGen/RISCV/div.ll @@ -1031,8 +1031,8 @@ ; RV32IM-NEXT: li a1, 103 ; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: srai a1, a0, 9 -; RV32IM-NEXT: srli a0, a0, 15 -; RV32IM-NEXT: andi a0, a0, 1 +; RV32IM-NEXT: slli a0, a0, 16 +; RV32IM-NEXT: srli a0, a0, 31 ; RV32IM-NEXT: add a0, a1, a0 ; RV32IM-NEXT: ret ; @@ -1055,8 +1055,8 @@ ; RV64IM-NEXT: li a1, 103 ; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: srai a1, a0, 9 -; RV64IM-NEXT: srli a0, a0, 15 -; RV64IM-NEXT: andi a0, a0, 1 +; RV64IM-NEXT: slli a0, a0, 48 +; RV64IM-NEXT: srli a0, a0, 63 ; RV64IM-NEXT: add a0, a1, a0 ; RV64IM-NEXT: ret %1 = sdiv i8 %a, 5 @@ -1068,8 +1068,8 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: srai a1, a1, 24 -; RV32I-NEXT: srli a1, a1, 12 -; RV32I-NEXT: andi a1, a1, 7 +; RV32I-NEXT: slli a1, a1, 17 +; RV32I-NEXT: srli a1, a1, 29 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 27 @@ -1079,8 +1079,8 @@ ; RV32IM: # %bb.0: ; RV32IM-NEXT: slli a1, a0, 24 ; RV32IM-NEXT: srai a1, a1, 24 -; RV32IM-NEXT: srli a1, a1, 12 -; RV32IM-NEXT: andi a1, a1, 7 +; RV32IM-NEXT: slli a1, a1, 17 +; RV32IM-NEXT: srli a1, a1, 29 ; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: slli a0, a0, 24 ; RV32IM-NEXT: srai a0, a0, 27 @@ -1090,8 +1090,8 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a0, 56 ; RV64I-NEXT: srai a1, a1, 56 -; RV64I-NEXT: srli a1, a1, 12 -; RV64I-NEXT: andi a1, a1, 7 +; RV64I-NEXT: slli a1, a1, 49 +; RV64I-NEXT: srli a1, a1, 61 ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 59 @@ -1101,8 +1101,8 @@ ; RV64IM: # %bb.0: ; RV64IM-NEXT: slli a1, a0, 56 ; RV64IM-NEXT: srai a1, a1, 56 -; RV64IM-NEXT: srli a1, a1, 12 -; RV64IM-NEXT: andi a1, a1, 7 +; RV64IM-NEXT: slli a1, a1, 49 +; RV64IM-NEXT: srli a1, a1, 61 ; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: slli a0, a0, 56 ; RV64IM-NEXT: srai a0, a0, 59 @@ -1260,8 +1260,8 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: srai a1, a1, 16 -; RV32I-NEXT: srli a1, a1, 28 -; RV32I-NEXT: andi a1, a1, 7 +; RV32I-NEXT: slli a1, a1, 1 +; RV32I-NEXT: srli a1, a1, 29 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 19 @@ -1271,8 +1271,8 @@ ; RV32IM: # %bb.0: ; RV32IM-NEXT: slli a1, a0, 16 ; RV32IM-NEXT: srai a1, a1, 16 -; RV32IM-NEXT: srli a1, a1, 28 -; RV32IM-NEXT: andi a1, a1, 7 +; RV32IM-NEXT: slli a1, a1, 1 +; RV32IM-NEXT: srli a1, a1, 29 ; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: slli a0, a0, 16 ; RV32IM-NEXT: srai a0, a0, 19 @@ -1282,8 +1282,8 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a0, 48 ; RV64I-NEXT: srai a1, a1, 48 -; RV64I-NEXT: srli a1, a1, 28 -; RV64I-NEXT: andi a1, a1, 7 +; RV64I-NEXT: slli a1, a1, 33 +; RV64I-NEXT: srli a1, a1, 61 ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 51 @@ -1293,8 +1293,8 @@ ; RV64IM: # %bb.0: ; RV64IM-NEXT: slli a1, a0, 48 ; RV64IM-NEXT: srai a1, a1, 48 -; RV64IM-NEXT: srli a1, a1, 28 -; RV64IM-NEXT: andi a1, a1, 7 +; RV64IM-NEXT: slli a1, a1, 33 +; RV64IM-NEXT: srli a1, a1, 61 ; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: slli a0, a0, 48 ; RV64IM-NEXT: srai a0, a0, 51 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll @@ -140,8 +140,8 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: rol_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: srli a3, a2, 5 -; RV32I-NEXT: andi a3, a3, 1 +; RV32I-NEXT: slli a3, a2, 26 +; RV32I-NEXT: srli a3, a3, 31 ; RV32I-NEXT: mv a4, a1 ; RV32I-NEXT: bnez a3, .LBB7_2 ; RV32I-NEXT: # %bb.1: @@ -165,8 +165,8 @@ ; ; RV32ZBB-ZBP-ZBKB-LABEL: rol_i64: ; RV32ZBB-ZBP-ZBKB: # %bb.0: -; RV32ZBB-ZBP-ZBKB-NEXT: srli a3, a2, 5 -; RV32ZBB-ZBP-ZBKB-NEXT: andi a3, a3, 1 +; RV32ZBB-ZBP-ZBKB-NEXT: slli a3, a2, 26 +; RV32ZBB-ZBP-ZBKB-NEXT: srli a3, a3, 31 ; RV32ZBB-ZBP-ZBKB-NEXT: mv a4, a1 ; RV32ZBB-ZBP-ZBKB-NEXT: bnez a3, .LBB7_2 ; RV32ZBB-ZBP-ZBKB-NEXT: # %bb.1: diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -324,8 +324,8 @@ define i32 @bexti_i32(i32 %a) nounwind { ; RV32I-LABEL: bexti_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: srli a0, a0, 5 -; RV32I-NEXT: andi a0, a0, 1 +; RV32I-NEXT: slli a0, a0, 26 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: ret ; ; RV32ZBS-LABEL: bexti_i32: @@ -340,8 +340,8 @@ define i64 @bexti_i64(i64 %a) nounwind { ; RV32I-LABEL: bexti_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: srli a0, a0, 5 -; RV32I-NEXT: andi a0, a0, 1 +; RV32I-NEXT: slli a0, a0, 26 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rv32zbt.ll b/llvm/test/CodeGen/RISCV/rv32zbt.ll --- a/llvm/test/CodeGen/RISCV/rv32zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbt.ll @@ -799,8 +799,8 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind { ; RV32I-LABEL: fshl_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: srli a5, a4, 5 -; RV32I-NEXT: andi a6, a5, 1 +; RV32I-NEXT: slli a5, a4, 26 +; RV32I-NEXT: srli a6, a5, 31 ; RV32I-NEXT: mv a5, a3 ; RV32I-NEXT: bnez a6, .LBB36_2 ; RV32I-NEXT: # %bb.1: @@ -828,8 +828,8 @@ ; ; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT: # %bb.0: -; RV32ZBT-NEXT: srli a5, a4, 5 -; RV32ZBT-NEXT: andi a5, a5, 1 +; RV32ZBT-NEXT: slli a5, a4, 26 +; RV32ZBT-NEXT: srli a5, a5, 31 ; RV32ZBT-NEXT: cmov a2, a5, a2, a3 ; RV32ZBT-NEXT: cmov a3, a5, a3, a0 ; RV32ZBT-NEXT: andi a4, a4, 31 diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll --- a/llvm/test/CodeGen/RISCV/rv64zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll @@ -409,8 +409,8 @@ define signext i32 @bexti_i32(i32 signext %a) nounwind { ; RV64I-LABEL: bexti_i32: ; RV64I: # %bb.0: -; RV64I-NEXT: srli a0, a0, 5 -; RV64I-NEXT: andi a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 58 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ret ; ; RV64ZBS-LABEL: bexti_i32: @@ -425,8 +425,8 @@ define i64 @bexti_i64(i64 %a) nounwind { ; RV64I-LABEL: bexti_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: srli a0, a0, 5 -; RV64I-NEXT: andi a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 58 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ret ; ; RV64ZBS-LABEL: bexti_i64: diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll --- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -211,8 +211,8 @@ ; RV32: # %bb.0: ; RV32-NEXT: slli a1, a0, 26 ; RV32-NEXT: srai a1, a1, 26 -; RV32-NEXT: srli a1, a1, 9 -; RV32-NEXT: andi a1, a1, 3 +; RV32-NEXT: slli a1, a1, 21 +; RV32-NEXT: srli a1, a1, 30 ; RV32-NEXT: add a1, a0, a1 ; RV32-NEXT: andi a1, a1, 60 ; RV32-NEXT: sub a0, a0, a1 @@ -224,8 +224,8 @@ ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a0, 58 ; RV64-NEXT: srai a1, a1, 58 -; RV64-NEXT: srli a1, a1, 9 -; RV64-NEXT: andi a1, a1, 3 +; RV64-NEXT: slli a1, a1, 53 +; RV64-NEXT: srli a1, a1, 62 ; RV64-NEXT: addw a1, a0, a1 ; RV64-NEXT: andi a1, a1, 60 ; RV64-NEXT: subw a0, a0, a1 @@ -237,8 +237,8 @@ ; RV32M: # %bb.0: ; RV32M-NEXT: slli a1, a0, 26 ; RV32M-NEXT: srai a1, a1, 26 -; RV32M-NEXT: srli a1, a1, 9 -; RV32M-NEXT: andi a1, a1, 3 +; RV32M-NEXT: slli a1, a1, 21 +; RV32M-NEXT: srli a1, a1, 30 ; RV32M-NEXT: add a1, a0, a1 ; RV32M-NEXT: andi a1, a1, 60 ; RV32M-NEXT: sub a0, a0, a1 @@ -250,8 +250,8 @@ ; RV64M: # %bb.0: ; RV64M-NEXT: slli a1, a0, 58 ; RV64M-NEXT: srai a1, a1, 58 -; RV64M-NEXT: srli a1, a1, 9 -; RV64M-NEXT: andi a1, a1, 3 +; RV64M-NEXT: slli a1, a1, 53 +; RV64M-NEXT: srli a1, a1, 62 ; RV64M-NEXT: addw a1, a0, a1 ; RV64M-NEXT: andi a1, a1, 60 ; RV64M-NEXT: subw a0, a0, a1 @@ -263,8 +263,8 @@ ; RV32MV: # %bb.0: ; RV32MV-NEXT: slli a1, a0, 26 ; RV32MV-NEXT: srai a1, a1, 26 -; RV32MV-NEXT: srli a1, a1, 9 -; RV32MV-NEXT: andi a1, a1, 3 +; RV32MV-NEXT: slli a1, a1, 21 +; RV32MV-NEXT: srli a1, a1, 30 ; RV32MV-NEXT: add a1, a0, a1 ; RV32MV-NEXT: andi a1, a1, 60 ; RV32MV-NEXT: sub a0, a0, a1 @@ -276,8 +276,8 @@ ; RV64MV: # %bb.0: ; RV64MV-NEXT: slli a1, a0, 58 ; RV64MV-NEXT: srai a1, a1, 58 -; RV64MV-NEXT: srli a1, a1, 9 -; RV64MV-NEXT: andi a1, a1, 3 +; RV64MV-NEXT: slli a1, a1, 53 +; RV64MV-NEXT: srli a1, a1, 62 ; RV64MV-NEXT: addw a1, a0, a1 ; RV64MV-NEXT: andi a1, a1, 60 ; RV64MV-NEXT: subw a0, a0, a1 @@ -310,15 +310,15 @@ ; RV32-NEXT: slli a3, a1, 30 ; RV32-NEXT: srli a4, a2, 2 ; RV32-NEXT: or s2, a4, a3 -; RV32-NEXT: srli a1, a1, 2 -; RV32-NEXT: andi a1, a1, 1 +; RV32-NEXT: slli a1, a1, 29 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: neg s3, a1 ; RV32-NEXT: slli a1, a2, 31 ; RV32-NEXT: srli a0, a0, 1 ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: lw s4, 0(s0) -; RV32-NEXT: srli a1, a2, 1 -; RV32-NEXT: andi a1, a1, 1 +; RV32-NEXT: slli a1, a2, 30 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: neg a1, a1 ; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a3, 0 @@ -464,15 +464,15 @@ ; RV32M-NEXT: slli a3, a1, 30 ; RV32M-NEXT: srli a4, a2, 2 ; RV32M-NEXT: or s2, a4, a3 -; RV32M-NEXT: srli a1, a1, 2 -; RV32M-NEXT: andi a1, a1, 1 +; RV32M-NEXT: slli a1, a1, 29 +; RV32M-NEXT: srli a1, a1, 31 ; RV32M-NEXT: neg s3, a1 ; RV32M-NEXT: slli a1, a2, 31 ; RV32M-NEXT: srli a0, a0, 1 ; RV32M-NEXT: or a0, a0, a1 ; RV32M-NEXT: lw s4, 0(s0) -; RV32M-NEXT: srli a1, a2, 1 -; RV32M-NEXT: andi a1, a1, 1 +; RV32M-NEXT: slli a1, a2, 30 +; RV32M-NEXT: srli a1, a1, 31 ; RV32M-NEXT: neg a1, a1 ; RV32M-NEXT: li a2, 7 ; RV32M-NEXT: li a3, 0 @@ -614,14 +614,14 @@ ; RV32MV-NEXT: srli a3, a1, 1 ; RV32MV-NEXT: or s3, a3, a2 ; RV32MV-NEXT: lbu a2, 12(s2) -; RV32MV-NEXT: srli a3, a0, 1 -; RV32MV-NEXT: andi a3, a3, 1 +; RV32MV-NEXT: slli a3, a0, 30 +; RV32MV-NEXT: srli a3, a3, 31 ; RV32MV-NEXT: neg s4, a3 ; RV32MV-NEXT: slli a3, a2, 30 ; RV32MV-NEXT: srli a0, a0, 2 ; RV32MV-NEXT: or s5, a0, a3 -; RV32MV-NEXT: srli a0, a2, 2 -; RV32MV-NEXT: andi a2, a0, 1 +; RV32MV-NEXT: slli a0, a2, 29 +; RV32MV-NEXT: srli a2, a0, 31 ; RV32MV-NEXT: lw a0, 0(s2) ; RV32MV-NEXT: neg s6, a2 ; RV32MV-NEXT: andi a1, a1, 1 @@ -766,8 +766,8 @@ ; RV64MV-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; RV64MV-NEXT: vslidedown.vi v10, v8, 2 ; RV64MV-NEXT: vmv.x.s a2, v10 -; RV64MV-NEXT: srli a3, a2, 30 -; RV64MV-NEXT: andi a3, a3, 7 +; RV64MV-NEXT: slli a3, a2, 31 +; RV64MV-NEXT: srli a3, a3, 61 ; RV64MV-NEXT: sb a3, 12(a0) ; RV64MV-NEXT: slli a2, a2, 2 ; RV64MV-NEXT: vslidedown.vi v10, v8, 1 diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -363,8 +363,8 @@ ; RV32-NEXT: neg a1, s3 ; RV32-NEXT: neg a0, a0 ; RV32-NEXT: neg a2, s1 -; RV32-NEXT: srli a2, a2, 10 -; RV32-NEXT: andi a2, a2, 1 +; RV32-NEXT: slli a2, a2, 21 +; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: sb a2, 4(s0) ; RV32-NEXT: andi a1, a1, 2047 ; RV32-NEXT: andi a0, a0, 2047 @@ -473,8 +473,8 @@ ; RV32M-NEXT: neg a2, a2 ; RV32M-NEXT: neg a3, a3 ; RV32M-NEXT: neg a4, a1 -; RV32M-NEXT: srli a4, a4, 10 -; RV32M-NEXT: andi a4, a4, 1 +; RV32M-NEXT: slli a4, a4, 21 +; RV32M-NEXT: srli a4, a4, 31 ; RV32M-NEXT: sb a4, 4(a0) ; RV32M-NEXT: andi a2, a2, 2047 ; RV32M-NEXT: andi a3, a3, 2047 @@ -579,8 +579,8 @@ ; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; RV32MV-NEXT: vslidedown.vi v9, v8, 2 ; RV32MV-NEXT: vmv.x.s a1, v9 -; RV32MV-NEXT: srli a2, a1, 10 -; RV32MV-NEXT: andi a2, a2, 1 +; RV32MV-NEXT: slli a2, a1, 21 +; RV32MV-NEXT: srli a2, a2, 31 ; RV32MV-NEXT: sb a2, 4(a0) ; RV32MV-NEXT: vmv.x.s a2, v8 ; RV32MV-NEXT: andi a2, a2, 2047