diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4572,9 +4572,13 @@ } bool getGatherScatterIndexIsExtended(SDValue Index) { + // Ignore non-pointer sized indices. + if (Index.getValueType() != MVT::nxv2i64) + return false; + unsigned Opcode = Index.getOpcode(); if (Opcode == ISD::SIGN_EXTEND_INREG) - return true; + return cast(Index.getOperand(1))->getVT() == MVT::nxv2i32; if (Opcode == ISD::AND) { SDValue Splat = Index.getOperand(1); diff --git a/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll b/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll --- a/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll +++ b/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll @@ -374,11 +374,11 @@ ret %data } -; TODO: The generated code is wrong because we've lost the sign extension which -; defines bits offsets[8:31]. define @masked_gather_nxv4i32_s8_offsets(i32* %base, %offsets, %mask) #0 { ; CHECK-LABEL: masked_gather_nxv4i32_s8_offsets: ; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: sxtb z0.s, p1/m, z0.s ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw #2] ; CHECK-NEXT: ret %offsets.sext = sext %offsets to @@ -399,12 +399,13 @@ ret %data } -; TODO: The generated code is wrong because we've lost the sign extension which -; defines bits offsets[8:31] and we're also replicating offset[31] across +; TODO: The generated code is wrong because we're replicating offset[31] across ; offset[32:63] even though the IR has explicitly zero'd those bits. define @masked_gather_nxv4i32_u32s8_offsets(i32* %base, %offsets, %mask) #0 { ; CHECK-LABEL: masked_gather_nxv4i32_u32s8_offsets: ; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: sxtb z0.s, p1/m, z0.s ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw #2] ; CHECK-NEXT: ret %offsets.sext = sext %offsets to @@ -456,11 +457,11 @@ ret void } -; TODO: The generated code is wrong because we've lost the sign extension which -; defines bits offsets[8:31]. define void @masked_scatter_nxv4i32_s8_offsets(i32* %base, %offsets, %mask, %data) #0 { ; CHECK-LABEL: masked_scatter_nxv4i32_s8_offsets: ; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: sxtb z0.s, p1/m, z0.s ; CHECK-NEXT: st1w { z1.s }, p0, [x0, z0.s, sxtw #2] ; CHECK-NEXT: ret %offsets.sext = sext %offsets to @@ -481,12 +482,13 @@ ret void } -; TODO: The generated code is wrong because we've lost the sign extension which -; defines bits offsets[8:31] and we're also replicating offset[31] across +; TODO: The generated code is wrong because we're replicating offset[31] across ; offset[32:63] even though the IR has explicitly zero'd those bits. define void @masked_scatter_nxv4i32_u32s8_offsets(i32* %base, %offsets, %mask, %data) #0 { ; CHECK-LABEL: masked_scatter_nxv4i32_u32s8_offsets: ; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: sxtb z0.s, p1/m, z0.s ; CHECK-NEXT: st1w { z1.s }, p0, [x0, z0.s, sxtw #2] ; CHECK-NEXT: ret %offsets.sext = sext %offsets to