diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp --- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp +++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp @@ -7,20 +7,8 @@ //===----------------------------------------------------------------------===// // // Merge the offset of address calculation into the offset field -// of instructions in a global address lowering sequence. This pass transforms: -// lui vreg1, %hi(s) -// addi vreg2, vreg1, %lo(s) -// addi vreg3, verg2, Offset +// of instructions in a global address lowering sequence. // -// Into: -// lui vreg1, %hi(s+Offset) -// addi vreg2, vreg1, %lo(s+Offset) -// -// The transformation is carried out under certain conditions: -// 1) The offset field in the base of global address lowering sequence is zero. -// 2) The lowered global address has only one use. -// -// The offset field can be in a different form. This pass handles all of them. //===----------------------------------------------------------------------===// #include "RISCV.h" @@ -44,10 +32,10 @@ public: static char ID; bool runOnMachineFunction(MachineFunction &Fn) override; - bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI); + bool detectFoldable(MachineInstr &Hi, MachineInstr *&Lo); - bool detectAndFoldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI); - void foldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI, MachineInstr &Tail, + bool detectAndFoldOffset(MachineInstr &Hi, MachineInstr &Lo); + void foldOffset(MachineInstr &Hi, MachineInstr &Lo, MachineInstr &Tail, int64_t Offset); bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset); bool matchShiftedOffset(MachineInstr &TailShXAdd, Register GSReg, @@ -79,51 +67,70 @@ INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, DEBUG_TYPE, RISCV_MERGE_BASE_OFFSET_NAME, false, false) -// Detect the pattern: +// Detect either of the patterns: +// +// 1. (medlow pattern): // lui vreg1, %hi(s) // addi vreg2, vreg1, %lo(s) // -// Pattern only accepted if: -// 1) ADDI has only one use. -// 2) LUI has only one use; which is the ADDI. -// 3) Both ADDI and LUI have GlobalAddress type which indicates that these -// are generated from global address lowering. -// 4) Offset value in the Global Address is 0. -bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI, - MachineInstr *&LoADDI) { - if (HiLUI.getOpcode() != RISCV::LUI || - HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || - !HiLUI.getOperand(1).isGlobal() || - HiLUI.getOperand(1).getOffset() != 0 || - !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) - return false; - Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); - LoADDI = &*MRI->use_instr_begin(HiLuiDestReg); - if (LoADDI->getOpcode() != RISCV::ADDI || - LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || - !LoADDI->getOperand(2).isGlobal() || - LoADDI->getOperand(2).getOffset() != 0 || - !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) +// 2. (medany pattern): +// .Lpcrel_hi1: +// auipc vreg1, %pcrel_hi(s) +// addi vreg2, vreg1, %pcrel_lo(.Lpcrel_hi1) +// +// The pattern is only accepted if: +// 1) The first instruction has only one use, which is the ADDI. +// 2) ADDI has only one use. +// 3) The address operands have the appropriate type, reflecting the +// lowering of a global address using medlow or medany. +// 4) The offset value in the Global Address is 0. +bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi, + MachineInstr *&Lo) { + if (Hi.getOpcode() == RISCV::LUI) { + if (Hi.getOperand(1).getTargetFlags() != RISCVII::MO_HI || + !Hi.getOperand(1).isGlobal() || Hi.getOperand(1).getOffset() != 0 || + !MRI->hasOneUse(Hi.getOperand(0).getReg())) + return false; + Register HiDestReg = Hi.getOperand(0).getReg(); + Lo = &*MRI->use_instr_begin(HiDestReg); + if (Lo->getOpcode() != RISCV::ADDI || + Lo->getOperand(2).getTargetFlags() != RISCVII::MO_LO || + !Lo->getOperand(2).isGlobal() || Lo->getOperand(2).getOffset() != 0 || + !MRI->hasOneUse(Lo->getOperand(0).getReg())) + return false; + return true; + } else if (Hi.getOpcode() == RISCV::AUIPC) { + if (Hi.getOperand(1).getTargetFlags() != RISCVII::MO_PCREL_HI || + !Hi.getOperand(1).isGlobal() || Hi.getOperand(1).getOffset() != 0 || + !MRI->hasOneUse(Hi.getOperand(0).getReg())) + return false; + Register HiDestReg = Hi.getOperand(0).getReg(); + Lo = &*MRI->use_instr_begin(HiDestReg); + if (Lo->getOpcode() != RISCV::ADDI || + Lo->getOperand(2).getTargetFlags() != RISCVII::MO_PCREL_LO || + Lo->getOperand(2).getType() != MachineOperand::MO_MCSymbol || + !MRI->hasOneUse(Lo->getOperand(0).getReg())) + return false; + return true; + } else { return false; - return true; + } } -// Update the offset in HiLUI and LoADDI instructions. +// Update the offset in Hi and Lo instructions. // Delete the tail instruction and update all the uses to use the -// output from LoADDI. -void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &HiLUI, - MachineInstr &LoADDI, +// output from Lo. +void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &Hi, MachineInstr &Lo, MachineInstr &Tail, int64_t Offset) { assert(isInt<32>(Offset) && "Unexpected offset"); - // Put the offset back in HiLUI and the LoADDI - HiLUI.getOperand(1).setOffset(Offset); - LoADDI.getOperand(2).setOffset(Offset); + // Put the offset back in Hi and the Lo + Hi.getOperand(1).setOffset(Offset); + Lo.getOperand(2).setOffset(Offset); // Delete the tail instruction. DeadInstrs.insert(&Tail); - MRI->replaceRegWith(Tail.getOperand(0).getReg(), - LoADDI.getOperand(0).getReg()); + MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg()); LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n" - << " " << HiLUI << " " << LoADDI;); + << " " << Hi << " " << Lo;); } // Detect patterns for large offsets that are passed into an ADD instruction. @@ -155,7 +162,7 @@ // Can't fold if the register has more than one use. if (!MRI->hasOneUse(Reg)) return false; - // This can point to an ADDI or a LUI: + // This can point to an ADDI(W) or a LUI: MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); if (OffsetTail.getOpcode() == RISCV::ADDI || OffsetTail.getOpcode() == RISCV::ADDIW) { @@ -249,11 +256,11 @@ return true; } -bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI, - MachineInstr &LoADDI) { - Register DestReg = LoADDI.getOperand(0).getReg(); - assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); - // LoADDI has only one use. +bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &Hi, + MachineInstr &Lo) { + Register DestReg = Lo.getOperand(0).getReg(); + assert(MRI->hasOneUse(DestReg) && "expected one use for Lo"); + // Lo has only one use. MachineInstr &Tail = *MRI->use_instr_begin(DestReg); switch (Tail.getOpcode()) { default: @@ -261,6 +268,8 @@ << Tail); return false; case RISCV::ADDI: { + if (Hi.getOpcode() != RISCV::LUI) + return false; // Offset is simply an immediate operand. int64_t Offset = Tail.getOperand(2).getImm(); @@ -272,13 +281,13 @@ Offset += TailTail.getOperand(2).getImm(); LLVM_DEBUG(dbgs() << " Offset Instrs: " << Tail << TailTail); DeadInstrs.insert(&Tail); - foldOffset(HiLUI, LoADDI, TailTail, Offset); + foldOffset(Hi, Lo, TailTail, Offset); return true; } } LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail); - foldOffset(HiLUI, LoADDI, Tail, Offset); + foldOffset(Hi, Lo, Tail, Offset); return true; } case RISCV::ADD: { @@ -290,10 +299,12 @@ // both hi 20 and lo 12 bits. // 2) LUI (offset20) // This happens in case the lower 12 bits of the offset are zeros. + if (Hi.getOpcode() != RISCV::LUI) + return false; int64_t Offset; if (!matchLargeOffset(Tail, DestReg, Offset)) return false; - foldOffset(HiLUI, LoADDI, Tail, Offset); + foldOffset(Hi, Lo, Tail, Offset); return true; } case RISCV::SH1ADD: @@ -305,7 +316,7 @@ int64_t Offset; if (!matchShiftedOffset(Tail, DestReg, Offset)) return false; - foldOffset(HiLUI, LoADDI, Tail, Offset); + foldOffset(Hi, Lo, Tail, Offset); return true; } case RISCV::LB: @@ -326,30 +337,43 @@ case RISCV::FSW: case RISCV::FSD: { // Transforms the sequence: Into: - // HiLUI: lui vreg1, %hi(foo) ---> lui vreg1, %hi(foo+8) - // LoADDI: addi vreg2, vreg1, %lo(foo) ---> lw vreg3, lo(foo+8)(vreg1) - // Tail: lw vreg3, 8(vreg2) + // Hi: lui vreg1, %hi(foo) ---> lui vreg1, %hi(foo+8) + // Lo: addi vreg2, vreg1, %lo(foo) ---> lw vreg3, lo(foo+8)(vreg1) + // Tail: lw vreg3, 8(vreg2) if (Tail.getOperand(1).isFI()) return false; - // Register defined by LoADDI should be used in the base part of the + // Register defined by Lo should be used in the base part of the // load\store instruction. Otherwise, no folding possible. Register BaseAddrReg = Tail.getOperand(1).getReg(); if (DestReg != BaseAddrReg) return false; - MachineOperand &TailImmOp = Tail.getOperand(2); - int64_t Offset = TailImmOp.getImm(); - // Update the offsets in global address lowering. - HiLUI.getOperand(1).setOffset(Offset); - // Update the immediate in the Tail instruction to add the offset. - Tail.removeOperand(2); - MachineOperand &ImmOp = LoADDI.getOperand(2); - ImmOp.setOffset(Offset); - Tail.addOperand(ImmOp); - // Update the base reg in the Tail instruction to feed from LUI. - // Output of HiLUI is only used in LoADDI, no need to use - // MRI->replaceRegWith(). - Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg()); - DeadInstrs.insert(&LoADDI); + if (Hi.getOpcode() == RISCV::LUI) { + MachineOperand &TailImmOp = Tail.getOperand(2); + int64_t Offset = TailImmOp.getImm(); + // Update the offsets in global address lowering. + Hi.getOperand(1).setOffset(Offset); + // Update the immediate in the Tail instruction to add the offset. + Tail.removeOperand(2); + MachineOperand &ImmOp = Lo.getOperand(2); + ImmOp.setOffset(Offset); + Tail.addOperand(ImmOp); + // Update the base reg in the Tail instruction to feed from LUI. + // Output of Hi is only used in Lo, no need to use + // MRI->replaceRegWith(). + Tail.getOperand(1).setReg(Hi.getOperand(0).getReg()); + } else if (Hi.getOpcode() == RISCV::AUIPC) { + MachineOperand &TailImmOp = Tail.getOperand(2); + int64_t Offset = TailImmOp.getImm(); + // Update the offsets in global address lowering. + Hi.getOperand(1).setOffset(Offset); + // Update the immediate in the Tail instruction with the %pcrel_lo offset. + Tail.removeOperand(2); + Tail.addOperand(Lo.getOperand(2)); + Tail.getOperand(1).setReg(Hi.getOperand(0).getReg()); + } else { + llvm_unreachable("Unexpected opcode"); + } + DeadInstrs.insert(&Lo); return true; } } @@ -367,14 +391,14 @@ MRI = &Fn.getRegInfo(); for (MachineBasicBlock &MBB : Fn) { LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n"); - for (MachineInstr &HiLUI : MBB) { - MachineInstr *LoADDI = nullptr; - if (!detectLuiAddiGlobal(HiLUI, LoADDI)) + for (MachineInstr &Hi : MBB) { + MachineInstr *Lo = nullptr; + if (!detectFoldable(Hi, Lo)) continue; LLVM_DEBUG(dbgs() << " Found lowered global address with one use: " - << *LoADDI->getOperand(2).getGlobal() << "\n"); + << *Hi.getOperand(2).getGlobal() << "\n"); // If the use count is only one, merge the offset - MadeChange |= detectAndFoldOffset(HiLUI, *LoADDI); + MadeChange |= detectAndFoldOffset(Hi, *Lo); } } // Delete dead instructions. diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll --- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll +++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll @@ -18,8 +18,7 @@ ; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM-NEXT: .Lpcrel_hi0: ; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G) -; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0) -; RV32I-MEDIUM-NEXT: lw a0, 0(a0) +; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) ; RV32I-MEDIUM-NEXT: ret %1 = load volatile i32, i32* @G ret i32 %1 @@ -41,9 +40,8 @@ ; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM-NEXT: .Lpcrel_hi1: ; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr) -; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1) ; RV32I-MEDIUM-NEXT: li a1, 1 -; RV32I-MEDIUM-NEXT: sw a1, 0(a0) +; RV32I-MEDIUM-NEXT: sw a1, %pcrel_lo(.Lpcrel_hi1)(a0) ; RV32I-MEDIUM-NEXT: ret store volatile i8* blockaddress(@lower_blockaddress, %block), i8** @addr ret void diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll --- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -49,8 +49,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi0: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_0) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_0 @@ -85,8 +84,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi1: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_1) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_1 @@ -121,8 +119,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi2: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_2) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_2 @@ -157,8 +154,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi3: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi3) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_4 @@ -192,8 +188,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi4: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi4) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_8 @@ -227,8 +222,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi5: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_16) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi5) -; RV64I-MEDIUM-NEXT: ld a0, 0(a0) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* @g_16 @@ -263,8 +257,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi6: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi6) -; RV64I-MEDIUM-NEXT: sd zero, 0(a0) +; RV64I-MEDIUM-NEXT: sd zero, %pcrel_lo(.Lpcrel_hi6)(a0) ; RV64I-MEDIUM-NEXT: ret entry: store i64 0, i64* @g_4 @@ -298,8 +291,7 @@ ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi7: ; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_8) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi7) -; RV64I-MEDIUM-NEXT: sd zero, 0(a0) +; RV64I-MEDIUM-NEXT: sd zero, %pcrel_lo(.Lpcrel_hi7)(a0) ; RV64I-MEDIUM-NEXT: ret entry: store i64 0, i64* @g_8 @@ -371,9 +363,8 @@ ; RV32I-MEDIUM-LABEL: load_ga: ; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM-NEXT: .Lpcrel_hi9: -; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga) -; RV32I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi9) -; RV32I-MEDIUM-NEXT: lw a0, 4(a0) +; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga+4) +; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi9)(a0) ; RV32I-MEDIUM-NEXT: ret ; ; RV64I-LABEL: load_ga: @@ -385,9 +376,8 @@ ; RV64I-MEDIUM-LABEL: load_ga: ; RV64I-MEDIUM: # %bb.0: ; RV64I-MEDIUM-NEXT: .Lpcrel_hi9: -; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi9) -; RV64I-MEDIUM-NEXT: lw a0, 4(a0) +; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga+4) +; RV64I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi9)(a0) ; RV64I-MEDIUM-NEXT: ret %1 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @ga, i32 0, i32 1), align 4 ret i32 %1 @@ -425,9 +415,8 @@ ; RV64I-MEDIUM-LABEL: load_ga_8: ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi10: -; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_8) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi10) -; RV64I-MEDIUM-NEXT: ld a0, 8(a0) +; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_8+8) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi10)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_8, i32 0, i32 1) @@ -460,9 +449,8 @@ ; RV64I-MEDIUM-LABEL: load_ga_16: ; RV64I-MEDIUM: # %bb.0: # %entry ; RV64I-MEDIUM-NEXT: .Lpcrel_hi11: -; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_16) -; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi11) -; RV64I-MEDIUM-NEXT: ld a0, 8(a0) +; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(ga_16+8) +; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi11)(a0) ; RV64I-MEDIUM-NEXT: ret entry: %0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_16, i32 0, i32 1) diff --git a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll --- a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll +++ b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll @@ -14,10 +14,9 @@ ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: .Lpcrel_hi0: ; RV32I-NEXT: auipc a2, %pcrel_hi(l) -; RV32I-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0) ; RV32I-NEXT: .LBB0_1: # %loop ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: lw a3, 0(a2) +; RV32I-NEXT: lw a3, %pcrel_lo(.Lpcrel_hi0)(a2) ; RV32I-NEXT: addi a1, a1, 1 ; RV32I-NEXT: blt a1, a0, .LBB0_1 ; RV32I-NEXT: # %bb.2: # %ret @@ -28,10 +27,9 @@ ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: .Lpcrel_hi0: ; RV64I-NEXT: auipc a2, %pcrel_hi(l) -; RV64I-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0) ; RV64I-NEXT: .LBB0_1: # %loop ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: lw a3, 0(a2) +; RV64I-NEXT: lw a3, %pcrel_lo(.Lpcrel_hi0)(a2) ; RV64I-NEXT: addiw a1, a1, 1 ; RV64I-NEXT: blt a1, a0, .LBB0_1 ; RV64I-NEXT: # %bb.2: # %ret