diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1769,7 +1769,8 @@ Constraint>; let ForceTailAgnostic = true in def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask; + Op2Class, Constraint>, + RISCVMaskedPseudo; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -451,13 +451,6 @@ multiclass VPatIntegerSetCCVL_VV { - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - vti.RegClass:$rs2, cc, - (vti.Mask true_mask), - VLOpFrag)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, - vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), vti.RegClass:$rs2, cc, (vti.Mask V0), @@ -473,13 +466,6 @@ multiclass VPatIntegerSetCCVL_VV_Swappable : VPatIntegerSetCCVL_VV { - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), - vti.RegClass:$rs1, invcc, - (vti.Mask true_mask), - VLOpFrag)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, - vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), vti.RegClass:$rs1, invcc, (vti.Mask V0), @@ -491,24 +477,13 @@ multiclass VPatIntegerSetCCVL_VX_Swappable { - defvar instruction = !cast(instruction_name#"_VX_"#vti.LMul.MX); defvar instruction_masked = !cast(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (SplatPat (XLenVT GPR:$rs2)), cc, - (vti.Mask true_mask), - VLOpFrag)), - (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), (SplatPat (XLenVT GPR:$rs2)), cc, (vti.Mask V0), VLOpFrag)), (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; - def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), - (vti.Vector vti.RegClass:$rs1), invcc, - (vti.Mask true_mask), - VLOpFrag)), - (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), (vti.Vector vti.RegClass:$rs1), invcc, (vti.Mask V0), @@ -519,13 +494,7 @@ multiclass VPatIntegerSetCCVL_VI_Swappable { - defvar instruction = !cast(instruction_name#"_VI_"#vti.LMul.MX); defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (SplatPat_simm5 simm5:$rs2), cc, - (vti.Mask true_mask), - VLOpFrag)), - (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), (SplatPat_simm5 simm5:$rs2), cc, (vti.Mask V0), @@ -533,11 +502,6 @@ (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, XLenVT:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; - def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), - (vti.Vector vti.RegClass:$rs1), invcc, - (vti.Mask true_mask), - VLOpFrag)), - (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), (vti.Vector vti.RegClass:$rs1), invcc, (vti.Mask V0), @@ -549,14 +513,7 @@ multiclass VPatIntegerSetCCVL_VIPlus1 { - defvar instruction = !cast(instruction_name#"_VI_"#vti.LMul.MX); defvar instruction_masked = !cast(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); - def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), - (splatpat_kind simm5:$rs2), cc, - (vti.Mask true_mask), - VLOpFrag)), - (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), - GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), (splatpat_kind simm5:$rs2), cc, (vti.Mask V0),