diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -92,6 +92,8 @@ addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); if (Subtarget.hasStdExtD()) addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); + if (Subtarget.hasStdExtZfinx()) + addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass); static const MVT::SimpleValueType BoolVecVTs[] = { MVT::nxv1i1, MVT::nxv2i1, MVT::nxv4i1, MVT::nxv8i1, @@ -328,7 +330,7 @@ setOperationAction(ISD::FPOWI, MVT::i32, Custom); } - if (Subtarget.hasStdExtF()) { + if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) { for (auto NT : FPLegalNodeTypes) setOperationAction(NT, MVT::f32, Legal); for (auto CC : FPCCToExpand) @@ -342,7 +344,8 @@ setTruncStoreAction(MVT::f32, MVT::f16, Expand); } - if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) + if ((Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) && + Subtarget.is64Bit()) setOperationAction(ISD::BITCAST, MVT::i32, Custom); if (Subtarget.hasStdExtD()) { @@ -368,7 +371,7 @@ ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT}, MVT::i32, Custom); - if (Subtarget.hasStdExtF()) { + if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) { setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, Custom); @@ -881,7 +884,7 @@ Custom); if (Subtarget.hasStdExtZfh()) setOperationAction(ISD::BITCAST, MVT::f16, Custom); - if (Subtarget.hasStdExtF()) + if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) setOperationAction(ISD::BITCAST, MVT::f32, Custom); if (Subtarget.hasStdExtD()) setOperationAction(ISD::BITCAST, MVT::f64, Custom); @@ -901,7 +904,7 @@ setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); - if (Subtarget.hasStdExtF()) + if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); if (Subtarget.hasStdExtZbp()) @@ -914,7 +917,7 @@ setTargetDAGCombine(ISD::BITREVERSE); if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb()) setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); - if (Subtarget.hasStdExtF()) + if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); if (Subtarget.hasVInstructions()) @@ -1219,7 +1222,7 @@ // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin. if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) return false; - if (VT == MVT::f32 && !Subtarget.hasStdExtF()) + if (VT == MVT::f32 && !Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfinx()) return false; if (VT == MVT::f64 && !Subtarget.hasStdExtD()) return false; @@ -1228,7 +1231,8 @@ bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const { return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || - (VT == MVT::f32 && Subtarget.hasStdExtF()) || + (VT == MVT::f32 && + (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) || (VT == MVT::f64 && Subtarget.hasStdExtD()); } @@ -1238,7 +1242,9 @@ // Use f32 to pass f16 if it is legal and Zfh is not enabled. // We might still end up using a GPR but that will be decided based on ABI. // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin. - if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) + if (VT == MVT::f16 && + (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) && + !Subtarget.hasStdExtZfh()) return MVT::f32; return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); @@ -1250,7 +1256,9 @@ // Use f32 to pass f16 if it is legal and Zfh is not enabled. // We might still end up using a GPR but that will be decided based on ABI. // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin. - if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) + if (VT == MVT::f16 && + (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) && + !Subtarget.hasStdExtZfh()) return 1; return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT); @@ -2993,7 +3001,7 @@ return FPConv; } if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && - Subtarget.hasStdExtF()) { + (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) { SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0); @@ -7001,7 +7009,7 @@ SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv)); } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() && - Subtarget.hasStdExtF()) { + (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())) { SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv)); @@ -9476,6 +9484,7 @@ case RISCV::Select_GPR_Using_CC_GPR: case RISCV::Select_FPR16_Using_CC_GPR: case RISCV::Select_FPR32_Using_CC_GPR: + case RISCV::Select_FPR32INX_Using_CC_GPR: case RISCV::Select_FPR64_Using_CC_GPR: return true; } @@ -9652,6 +9661,7 @@ case RISCV::Select_GPR_Using_CC_GPR: case RISCV::Select_FPR16_Using_CC_GPR: case RISCV::Select_FPR32_Using_CC_GPR: + case RISCV::Select_FPR32INX_Using_CC_GPR: case RISCV::Select_FPR64_Using_CC_GPR: return emitSelectPseudo(MI, BB, Subtarget); case RISCV::BuildPairF64Pseudo: @@ -9664,8 +9674,12 @@ return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget); case RISCV::PseudoQuietFLE_S: return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget); + case RISCV::PseudoQuietFLE_S_INX: + return emitQuietFCMP(MI, BB, RISCV::FLE_S_INX, RISCV::FEQ_S_INX, Subtarget); case RISCV::PseudoQuietFLT_S: return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget); + case RISCV::PseudoQuietFLT_S_INX: + return emitQuietFCMP(MI, BB, RISCV::FLT_S_INX, RISCV::FEQ_S_INX, Subtarget); case RISCV::PseudoQuietFLE_D: return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget); case RISCV::PseudoQuietFLT_D: @@ -11253,7 +11267,8 @@ case 'f': if (Subtarget.hasStdExtZfh() && VT == MVT::f16) return std::make_pair(0U, &RISCV::FPR16RegClass); - if (Subtarget.hasStdExtF() && VT == MVT::f32) + if ((Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) && + VT == MVT::f32) return std::make_pair(0U, &RISCV::FPR32RegClass); if (Subtarget.hasStdExtD() && VT == MVT::f64) return std::make_pair(0U, &RISCV::FPR64RegClass); @@ -11668,7 +11683,7 @@ case MVT::f16: return Subtarget.hasStdExtZfh(); case MVT::f32: - return Subtarget.hasStdExtF(); + return Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx(); case MVT::f64: return Subtarget.hasStdExtD(); default: @@ -11705,7 +11720,7 @@ case MVT::f16: return Subtarget.hasStdExtZfh(); case MVT::f32: - return Subtarget.hasStdExtF(); + return Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx(); case MVT::f64: return Subtarget.hasStdExtD(); default: diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -209,7 +209,7 @@ let isCodeGenOnly = 1; } -class PseudoQuietFCMP +class PseudoQuietFCMP : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> { let hasSideEffects = 1; let mayLoad = 0; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -988,6 +988,7 @@ break; case RISCV::FSGNJ_D: case RISCV::FSGNJ_S: + case RISCV::FSGNJ_S_INX: case RISCV::FSGNJ_H: // The canonical floating-point move is fsgnj rd, rs, rs. return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && @@ -1017,6 +1018,7 @@ break; case RISCV::FSGNJ_D: case RISCV::FSGNJ_S: + case RISCV::FSGNJ_S_INX: case RISCV::FSGNJ_H: // The canonical floating-point move is fsgnj rd, rs, rs. if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1252,7 +1252,7 @@ IntCCtoRISCVCC>; let usesCustomInserter = 1 in -class SelectCC_rrirr +class SelectCC_rrirr : Pseudo<(outs valty:$dst), (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm, valty:$truev, valty:$falsev), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -456,6 +456,29 @@ (FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; def : InstAlias<"fge.s $rd, $rs, $rt", (FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; + +// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them +// zero weight. +def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>; +def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>; +def : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>; + +def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>; +def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>; +def : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>; +def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>; +def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>; + +def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>; +def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>; +def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>; +def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>; +def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>; + +let usesCustomInserter = 1 in { +def PseudoQuietFLE_S_INX : PseudoQuietFCMP; +def PseudoQuietFLT_S_INX : PseudoQuietFCMP; +} } // Predicates = [HasStdExtZfinx] //===----------------------------------------------------------------------===// @@ -467,22 +490,50 @@ def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; /// Generic pattern classes -class PatSetCC +class PatSetCC : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>; +multiclass PatSetCC_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def Ext.Suffix : PatSetCC(Inst#Ext.Suffix)>; +} class PatFprFpr + DAGOperand RegTy> : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>; +multiclass PatFprFpr_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def Ext.Suffix : PatFprFpr(Inst#Ext.Suffix), + Ext.Reg>; +} class PatFprFprDynFrm + DAGOperand RegTy> : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>; +multiclass PatFprFprDynFrm_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def Ext.Suffix : PatFprFprDynFrm(Inst#Ext.Suffix), + Ext.Reg>; +} let Predicates = [HasStdExtF] in { - /// Float constants def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>; +} // Predicates = [HasStdExtF] + +let Predicates = [HasStdExtZfinx] in { +def : Pat<(f32 (fpimm0)), (COPY (f32 X0))>; +def : Pat<(f32 (fpimmneg0)), (FSGNJN_S_INX (COPY (f32 X0)), (COPY (f32 X0)))>; +} // Predicates = [HasStdExtZfinx] /// Float conversion operations @@ -490,18 +541,28 @@ // are defined later. /// Float arithmetic operations +defm : PatFprFprDynFrm_m; +defm : PatFprFprDynFrm_m; +defm : PatFprFprDynFrm_m; +defm : PatFprFprDynFrm_m; -def : PatFprFprDynFrm; -def : PatFprFprDynFrm; -def : PatFprFprDynFrm; -def : PatFprFprDynFrm; - +let Predicates = [HasStdExtF] in { def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; +} // Predicates = [HasStdExtF] -def : PatFprFpr; +let Predicates = [HasStdExtZfinx] in { +def : Pat<(any_fsqrt FPR32INX:$rs1), (FSQRT_S_INX FPR32INX:$rs1, 0b111)>; + +def : Pat<(fneg FPR32INX:$rs1), (FSGNJN_S_INX $rs1, $rs1)>; +def : Pat<(fabs FPR32INX:$rs1), (FSGNJX_S_INX $rs1, $rs1)>; +} // Predicates = [HasStdExtZfinx] + +defm : PatFprFpr_m; + +let Predicates = [HasStdExtF] in { def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; // fmadd: rs1 * rs2 + rs3 @@ -519,25 +580,47 @@ // fnmadd: -rs1 * rs2 - rs3 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; +} // Predicates = [HasStdExtF] + +let Predicates = [HasStdExtZfinx] in { +def : Pat<(fcopysign FPR32INX:$rs1, (fneg FPR32INX:$rs2)), (FSGNJN_S_INX $rs1, $rs2)>; + +// fmadd: rs1 * rs2 + rs3 +def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3), + (FMADD_S_INX $rs1, $rs2, $rs3, 0b111)>; + +// fmsub: rs1 * rs2 - rs3 +def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, (fneg FPR32INX:$rs3)), + (FMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>; + +// fnmsub: -rs1 * rs2 + rs3 +def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, FPR32INX:$rs3), + (FNMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>; + +// fnmadd: -rs1 * rs2 - rs3 +def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, (fneg FPR32INX:$rs3)), + (FNMADD_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, 0b111)>; +} // Predicates = [HasStdExtZfinx] // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // LLVM's fminnum and fmaxnum // . -def : PatFprFpr; -def : PatFprFpr; +defm : PatFprFpr_m; +defm : PatFprFpr_m; /// Setcc // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for // strict versions of those. // Match non-signaling FEQ_S -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; +let Predicates = [HasStdExtF] in { // Match signaling FEQ_S def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ), (AND (FLE_S $rs1, $rs2), @@ -550,12 +633,30 @@ (FLE_S $rs1, $rs1)>; def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ), (FLE_S $rs1, $rs1)>; +} // Predicates = [HasStdExtF] + +let Predicates = [HasStdExtZfinx] in { +// Match signaling FEQ_S +def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ), + (AND (FLE_S_INX $rs1, $rs2), + (FLE_S_INX $rs2, $rs1))>; +def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ), + (AND (FLE_S_INX $rs1, $rs2), + (FLE_S_INX $rs2, $rs1))>; +// If both operands are the same, use a single FLE. +def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ), + (FLE_S_INX $rs1, $rs1)>; +def : Pat<(strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETOEQ), + (FLE_S_INX $rs1, $rs1)>; +} // Predicates = [HasStdExtZfinx] + +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; +defm : PatSetCC_m; -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; -def : PatSetCC; +let Predicates = [HasStdExtF] in { def Select_FPR32_Using_CC_GPR : SelectCC_rrirr; /// Loads @@ -568,11 +669,30 @@ } // Predicates = [HasStdExtF] +let Predicates = [HasStdExtZfinx] in { +def Select_FPR32INX_Using_CC_GPR : SelectCC_rrirr; + +/// Loads +def : Pat<(f32 (load BaseAddr:$rs1)), (COPY (LW BaseAddr:$rs1, 0))>; + +/// Stores +def : Pat<(store (f32 FPR32INX:$rs2), BaseAddr:$rs1), + (SW (COPY FPR32INX:$rs2), BaseAddr:$rs1, 0)>; +} + let Predicates = [HasStdExtF, IsRV32] in { // Moves (no conversion) def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>; def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; +} // Predicates = [HasStdExtF, IsRV32] + +let Predicates = [HasStdExtZfinx, IsRV32] in { +// Moves (no conversion) +def : Pat<(f32 (bitconvert (i32 GPR:$rs1))), (COPY GPR:$rs1)>; +def : Pat<(i32 (bitconvert FPR32INX:$rs1)), (COPY FPR32INX:$rs1)>; +} // Predicates = [HasStdExtZfinx, IsRV32] +let Predicates = [HasStdExtF, IsRV32] in { // float->[u]int. Round-to-zero must be used. def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; @@ -592,6 +712,26 @@ def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; } // Predicates = [HasStdExtF, IsRV32] +let Predicates = [HasStdExtZfinx, IsRV32] in { +// float->[u]int. Round-to-zero must be used. +def : Pat<(i32 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b001)>; +def : Pat<(i32 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_WU_S_INX $rs1, 0b001)>; + +// Saturating float->[u]int32. +def : Pat<(i32 (riscv_fcvt_x FPR32INX:$rs1, timm:$frm)), (FCVT_W_S_INX $rs1, timm:$frm)>; +def : Pat<(i32 (riscv_fcvt_xu FPR32INX:$rs1, timm:$frm)), (FCVT_WU_S_INX $rs1, timm:$frm)>; + +// float->int32 with current rounding mode. +def : Pat<(i32 (any_lrint FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b111)>; + +// float->int32 rounded to nearest with ties rounded away from zero. +def : Pat<(i32 (any_lround FPR32INX:$rs1)), (FCVT_W_S_INX $rs1, 0b100)>; + +// [u]int->float. Match GCC and default to using dynamic rounding mode. +def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_INX $rs1, 0b111)>; +def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_INX $rs1, 0b111)>; +} // Predicates = [HasStdExtZfinx, IsRV32] + let Predicates = [HasStdExtF, IsRV64] in { // Moves (no conversion) def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; @@ -627,3 +767,39 @@ def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; } // Predicates = [HasStdExtF, IsRV64] + +let Predicates = [HasStdExtZfinx, IsRV64] in { +// Moves (no conversion) +def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (COPY GPR:$src)>; +def : Pat<(riscv_fmv_x_anyextw_rv64 GPRF32:$src), (COPY GPRF32:$src)>; +def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 GPRF32:$src), i32), + (COPY GPRF32:$src)>; + +// Use target specific isd nodes to help us remember the result is sign +// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be +// duplicated if it has another user that didn't need the sign_extend. +def : Pat<(riscv_any_fcvt_w_rv64 FPR32INX:$rs1, timm:$frm), (FCVT_W_S_INX $rs1, timm:$frm)>; +def : Pat<(riscv_any_fcvt_wu_rv64 FPR32INX:$rs1, timm:$frm), (FCVT_WU_S_INX $rs1, timm:$frm)>; + +// float->[u]int64. Round-to-zero must be used. +def : Pat<(i64 (any_fp_to_sint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b001)>; +def : Pat<(i64 (any_fp_to_uint FPR32INX:$rs1)), (FCVT_LU_S_INX $rs1, 0b001)>; + +// Saturating float->[u]int64. +def : Pat<(i64 (riscv_fcvt_x FPR32INX:$rs1, timm:$frm)), (FCVT_L_S_INX $rs1, timm:$frm)>; +def : Pat<(i64 (riscv_fcvt_xu FPR32INX:$rs1, timm:$frm)), (FCVT_LU_S_INX $rs1, timm:$frm)>; + +// float->int64 with current rounding mode. +def : Pat<(i64 (any_lrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b111)>; +def : Pat<(i64 (any_llrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b111)>; + +// float->int64 rounded to neartest with ties rounded away from zero. +def : Pat<(i64 (any_lround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b100)>; +def : Pat<(i64 (any_llround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, 0b100)>; + +// [u]int->fp. Match GCC and default to using dynamic rounding mode. +def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W_INX $rs1, 0b111)>; +def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU_INX $rs1, 0b111)>; +def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L_INX $rs1, 0b111)>; +def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU_INX $rs1, 0b111)>; +} // Predicates = [HasStdExtZfinx, IsRV64] diff --git a/llvm/test/CodeGen/RISCV/float-arith-strict.ll b/llvm/test/CodeGen/RISCV/float-arith-strict.ll --- a/llvm/test/CodeGen/RISCV/float-arith-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-arith-strict.ll @@ -1,25 +1,31 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=ilp32 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=lp64 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s define float @fadd_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fadd_s: ; RV32I: # %bb.0: @@ -44,15 +50,15 @@ declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) define float @fsub_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsub.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsub.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsub.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsub.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsub_s: ; RV32I: # %bb.0: @@ -77,15 +83,15 @@ declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) define float @fmul_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fmul_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmul.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmul_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmul.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmul_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmul.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmul_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmul.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmul_s: ; RV32I: # %bb.0: @@ -110,15 +116,15 @@ declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) define float @fdiv_s(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fdiv_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fdiv_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fdiv.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fdiv_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fdiv_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fdiv.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fdiv_s: ; RV32I: # %bb.0: @@ -143,15 +149,15 @@ declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) define float @fsqrt_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fsqrt_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsqrt_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsqrt_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsqrt_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsqrt.s a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsqrt_s: ; RV32I: # %bb.0: @@ -194,6 +200,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fmin_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call fminf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fmin_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call fminf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fmin_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -235,6 +259,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fmax_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call fmaxf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fmax_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call fmaxf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fmax_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -258,15 +300,15 @@ declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmadd_s: ; RV32I: # %bb.0: @@ -291,19 +333,18 @@ declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fmsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmsub_s: ; RV32I: # %bb.0: @@ -355,21 +396,20 @@ } define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa1, ft0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fnmadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fnmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmadd_s: ; RV32I: # %bb.0: @@ -435,21 +475,20 @@ } define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmadd_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmadd_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa0, ft0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fnmadd_s_2: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fnmadd.s a0, a1, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_2: ; RV32I: # %bb.0: @@ -515,19 +554,18 @@ } define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa0, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa0, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa0, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa1, fa2 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fnmsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fnmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmsub_s: ; RV32I: # %bb.0: @@ -577,19 +615,18 @@ } define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fnmsub_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fnmsub_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV64IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa0, fa2 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fnmsub_s_2: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fnmsub.s a0, a1, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_2: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -1,8 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ @@ -14,15 +18,15 @@ ; instructions that don't directly match a RISC-V instruction. define float @fadd_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fadd_s: ; RV32I: # %bb.0: @@ -46,15 +50,15 @@ } define float @fsub_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsub.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsub.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsub.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsub.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsub_s: ; RV32I: # %bb.0: @@ -78,15 +82,15 @@ } define float @fmul_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmul_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmul.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmul_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmul.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmul_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmul.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmul_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmul.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmul_s: ; RV32I: # %bb.0: @@ -110,15 +114,15 @@ } define float @fdiv_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fdiv_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fdiv_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fdiv.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fdiv_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fdiv.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fdiv_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fdiv.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fdiv_s: ; RV32I: # %bb.0: @@ -144,15 +148,15 @@ declare float @llvm.sqrt.f32(float) define float @fsqrt_s(float %a) nounwind { -; RV32IF-LABEL: fsqrt_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsqrt_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsqrt_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsqrt_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsqrt.s a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsqrt_s: ; RV32I: # %bb.0: @@ -178,15 +182,15 @@ declare float @llvm.copysign.f32(float, float) define float @fsgnj_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsgnj_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsgnj_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fsgnj.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsgnj_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsgnj_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsgnj.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsgnj_s: ; RV32I: # %bb.0: @@ -209,22 +213,20 @@ ret float %1 } -; This function performs extra work to ensure that -; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. define i32 @fneg_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fneg_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa0 -; RV32IF-NEXT: fneg.s ft1, ft0 -; RV32IF-NEXT: feq.s a0, ft0, ft1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fneg_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa0 +; CHECK-NEXT: fneg.s ft1, ft0 +; CHECK-NEXT: feq.s a0, ft0, ft1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fneg_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa0 -; RV64IF-NEXT: fneg.s ft1, ft0 -; RV64IF-NEXT: feq.s a0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fneg_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a0 +; CHECKZFINX-NEXT: fneg.s a1, a0 +; CHECKZFINX-NEXT: feq.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fneg_s: ; RV32I: # %bb.0: @@ -260,20 +262,18 @@ ret i32 %4 } -; This function performs extra work to ensure that -; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. define float @fsgnjn_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fsgnjn_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fsgnjn.s fa0, fa0, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fsgnjn_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fsgnjn.s fa0, fa0, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsgnjn_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fsgnjn.s fa0, fa0, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsgnjn_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a0, a1 +; CHECKZFINX-NEXT: fsgnjn.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fsgnjn_s: ; RV32I: # %bb.0: @@ -318,22 +318,20 @@ declare float @llvm.fabs.f32(float) -; This function performs extra work to ensure that -; DAGCombiner::visitBITCAST doesn't replace the fabs with an and. define float @fabs_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fabs_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fabs.s ft1, ft0 -; RV32IF-NEXT: fadd.s fa0, ft1, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fabs_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fabs.s ft1, ft0 +; CHECK-NEXT: fadd.s fa0, ft1, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fabs_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fabs.s ft1, ft0 -; RV64IF-NEXT: fadd.s fa0, ft1, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fabs_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: fabs.s a1, a0 +; CHECKZFINX-NEXT: fadd.s a0, a1, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fabs_s: ; RV32I: # %bb.0: @@ -369,15 +367,15 @@ declare float @llvm.minnum.f32(float, float) define float @fmin_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmin_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmin.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmin_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmin.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmin_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmin.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmin_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmin.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmin_s: ; RV32I: # %bb.0: @@ -403,15 +401,15 @@ declare float @llvm.maxnum.f32(float, float) define float @fmax_s(float %a, float %b) nounwind { -; RV32IF-LABEL: fmax_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmax.s fa0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmax_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmax.s fa0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmax_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmax.s fa0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmax_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmax.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmax_s: ; RV32I: # %bb.0: @@ -437,15 +435,15 @@ declare float @llvm.fma.f32(float, float, float) define float @fmadd_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmadd_s: ; RV32I: # %bb.0: @@ -469,19 +467,18 @@ } define float @fmsub_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmsub_s: ; RV32I: # %bb.0: @@ -526,28 +523,26 @@ ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret - %c_ = fadd float 0.0, %c ; avoid negation using xor - %negc = fsub float -0.0, %c_ + %c_ = fadd float 0.0, %c %negc = fsub float -0.0, %c_ %1 = call float @llvm.fma.f32(float %a, float %b, float %negc) ret float %1 } define float @fnmadd_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmadd_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa1, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmadd_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmadd_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fnmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmadd_s: ; RV32I: # %bb.0: @@ -613,21 +608,20 @@ } define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, fa0, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmadd_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmadd_s_2: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fnmadd.s a0, a1, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_2: ; RV32I: # %bb.0: @@ -693,19 +687,18 @@ } define float @fnmsub_s(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa0, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmsub_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa0, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmsub_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa0, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmsub_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fnmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmsub_s: ; RV32I: # %bb.0: @@ -755,19 +748,18 @@ } define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s_2: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_2: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft0, fa0, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmsub_s_2: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmsub_s_2: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fnmsub.s a0, a1, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_2: ; RV32I: # %bb.0: @@ -819,15 +811,15 @@ } define float @fmadd_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmadd_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmadd_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmadd_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmadd_s_contract: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmadd_s_contract: ; RV32I: # %bb.0: @@ -862,19 +854,18 @@ } define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fmsub_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmsub_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fmsub.s fa0, fa0, fa1, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmsub_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmsub_s_contract: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmsub_s_contract: ; RV32I: # %bb.0: @@ -925,30 +916,28 @@ ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret - %c_ = fadd float 0.0, %c ; avoid negation using xor - %1 = fmul contract float %a, %b + %c_ = fadd float 0.0, %c %1 = fmul contract float %a, %b %2 = fsub contract float %1, %c_ ret float %2 } define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmadd_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft2, fa1, ft0 -; RV32IF-NEXT: fadd.s ft0, fa2, ft0 -; RV32IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmadd_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft2, fa1, ft0 +; CHECK-NEXT: fadd.s ft0, fa2, ft0 +; CHECK-NEXT: fnmadd.s fa0, ft1, ft2, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmadd_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft2, fa1, ft0 -; RV64IF-NEXT: fadd.s ft0, fa2, ft0 -; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmadd_s_contract: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fadd.s a2, a2, zero +; CHECKZFINX-NEXT: fnmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmadd_s_contract: ; RV32I: # %bb.0: @@ -1017,31 +1006,27 @@ ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret - %a_ = fadd float 0.0, %a ; avoid negation using xor - %b_ = fadd float 0.0, %b ; avoid negation using xor - %c_ = fadd float 0.0, %c ; avoid negation using xor - %1 = fmul contract float %a_, %b_ + %a_ = fadd float 0.0, %a %b_ = fadd float 0.0, %b %c_ = fadd float 0.0, %c %1 = fmul contract float %a_, %b_ %2 = fneg float %1 %3 = fsub contract float %2, %c_ ret float %3 } define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { -; RV32IF-LABEL: fnmsub_s_contract: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, zero -; RV32IF-NEXT: fadd.s ft1, fa0, ft0 -; RV32IF-NEXT: fadd.s ft0, fa1, ft0 -; RV32IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fnmsub_s_contract: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, zero +; CHECK-NEXT: fadd.s ft1, fa0, ft0 +; CHECK-NEXT: fadd.s ft0, fa1, ft0 +; CHECK-NEXT: fnmsub.s fa0, ft1, ft0, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fnmsub_s_contract: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, zero -; RV64IF-NEXT: fadd.s ft1, fa0, ft0 -; RV64IF-NEXT: fadd.s ft0, fa1, ft0 -; RV64IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fnmsub_s_contract: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, zero +; CHECKZFINX-NEXT: fadd.s a1, a1, zero +; CHECKZFINX-NEXT: fnmsub.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fnmsub_s_contract: ; RV32I: # %bb.0: @@ -1098,9 +1083,7 @@ ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: ret - %a_ = fadd float 0.0, %a ; avoid negation using xor - %b_ = fadd float 0.0, %b ; avoid negation using xor - %1 = fmul contract float %a_, %b_ + %a_ = fadd float 0.0, %a %b_ = fadd float 0.0, %b %1 = fmul contract float %a_, %b_ %2 = fsub contract float %c, %1 ret float %2 } diff --git a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll --- a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll @@ -3,10 +3,14 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32IZFINX %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64IZFINX %s ; This file tests cases where simple floating point operations can be ; profitably handled though bit manipulation if a soft-float ABI is being used @@ -27,6 +31,12 @@ ; RV32IF-NEXT: xor a0, a0, a1 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fneg: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: xor a0, a0, a1 +; RV32IZFINX-NEXT: ret +; ; RV64I-LABEL: fneg: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 524288 @@ -38,6 +48,12 @@ ; RV64IF-NEXT: lui a1, 524288 ; RV64IF-NEXT: xor a0, a0, a1 ; RV64IF-NEXT: ret +; +; RV64IZFINX-LABEL: fneg: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: lui a1, 524288 +; RV64IZFINX-NEXT: xor a0, a0, a1 +; RV64IZFINX-NEXT: ret %1 = fneg float %a ret float %1 } @@ -57,6 +73,12 @@ ; RV32IF-NEXT: srli a0, a0, 1 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fabs: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: slli a0, a0, 1 +; RV32IZFINX-NEXT: srli a0, a0, 1 +; RV32IZFINX-NEXT: ret +; ; RV64I-LABEL: fabs: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 33 @@ -68,6 +90,12 @@ ; RV64IF-NEXT: slli a0, a0, 33 ; RV64IF-NEXT: srli a0, a0, 33 ; RV64IF-NEXT: ret +; +; RV64IZFINX-LABEL: fabs: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: slli a0, a0, 33 +; RV64IZFINX-NEXT: srli a0, a0, 33 +; RV64IZFINX-NEXT: ret %1 = call float @llvm.fabs.f32(float %a) ret float %1 } @@ -99,6 +127,13 @@ ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcopysign_fneg: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lui a2, 524288 +; RV32IZFINX-NEXT: xor a1, a1, a2 +; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1 +; RV32IZFINX-NEXT: ret +; ; RV64I-LABEL: fcopysign_fneg: ; RV64I: # %bb.0: ; RV64I-NEXT: not a1, a1 @@ -116,6 +151,11 @@ ; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret +; +; RV64IZFINX-LABEL: fcopysign_fneg: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fsgnjn.s a0, a0, a1 +; RV64IZFINX-NEXT: ret %1 = fneg float %b %2 = call float @llvm.copysign.f32(float %a, float %1) ret float %2 diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -3,6 +3,10 @@ ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefix=RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefix=RV64IZFINX %s declare void @abort() declare void @exit(i32) @@ -34,6 +38,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB0_2: # %if.else ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_false: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: li a0, 1 +; RV32IZFINX-NEXT: bnez a0, .LBB0_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.then +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB0_2: # %if.else +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_false: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: li a0, 1 +; RV64IZFINX-NEXT: bnez a0, .LBB0_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.then +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB0_2: # %if.else +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp false float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -69,6 +99,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB1_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_oeq: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: feq.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB1_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB1_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_oeq: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: feq.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB1_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB1_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -107,6 +163,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB2_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_oeq_alt: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: feq.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB2_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB2_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_oeq_alt: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: feq.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB2_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB2_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -142,6 +224,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB3_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ogt: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a0, a1, a0 +; RV32IZFINX-NEXT: bnez a0, .LBB3_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB3_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ogt: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a0, a1, a0 +; RV64IZFINX-NEXT: bnez a0, .LBB3_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB3_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ogt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -177,6 +285,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB4_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_oge: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: fle.s a0, a1, a0 +; RV32IZFINX-NEXT: bnez a0, .LBB4_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB4_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_oge: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: fle.s a0, a1, a0 +; RV64IZFINX-NEXT: bnez a0, .LBB4_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB4_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp oge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -212,6 +346,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB5_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_olt: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB5_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB5_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_olt: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB5_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB5_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp olt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -247,6 +407,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB6_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ole: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: fle.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB6_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB6_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ole: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: fle.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB6_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB6_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ole float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -286,6 +472,36 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB7_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_one: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a2, a0, a1 +; RV32IZFINX-NEXT: flt.s a0, a1, a0 +; RV32IZFINX-NEXT: or a0, a0, a2 +; RV32IZFINX-NEXT: bnez a0, .LBB7_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB7_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_one: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a2, a0, a1 +; RV64IZFINX-NEXT: flt.s a0, a1, a0 +; RV64IZFINX-NEXT: or a0, a0, a2 +; RV64IZFINX-NEXT: bnez a0, .LBB7_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB7_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp one float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -325,6 +541,36 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB8_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ord: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: feq.s a1, a1, a1 +; RV32IZFINX-NEXT: feq.s a0, a0, a0 +; RV32IZFINX-NEXT: and a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB8_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB8_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ord: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: feq.s a1, a1, a1 +; RV64IZFINX-NEXT: feq.s a0, a0, a0 +; RV64IZFINX-NEXT: and a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB8_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB8_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ord float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -364,6 +610,36 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB9_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ueq: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a2, a0, a1 +; RV32IZFINX-NEXT: flt.s a0, a1, a0 +; RV32IZFINX-NEXT: or a0, a0, a2 +; RV32IZFINX-NEXT: beqz a0, .LBB9_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB9_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ueq: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a2, a0, a1 +; RV64IZFINX-NEXT: flt.s a0, a1, a0 +; RV64IZFINX-NEXT: or a0, a0, a2 +; RV64IZFINX-NEXT: beqz a0, .LBB9_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB9_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ueq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -399,6 +675,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB10_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ugt: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: fle.s a0, a0, a1 +; RV32IZFINX-NEXT: beqz a0, .LBB10_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB10_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ugt: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: fle.s a0, a0, a1 +; RV64IZFINX-NEXT: beqz a0, .LBB10_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB10_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ugt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -434,6 +736,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB11_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_uge: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a0, a0, a1 +; RV32IZFINX-NEXT: beqz a0, .LBB11_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB11_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_uge: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a0, a0, a1 +; RV64IZFINX-NEXT: beqz a0, .LBB11_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB11_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp uge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -469,6 +797,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB12_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ult: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: fle.s a0, a1, a0 +; RV32IZFINX-NEXT: beqz a0, .LBB12_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB12_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ult: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: fle.s a0, a1, a0 +; RV64IZFINX-NEXT: beqz a0, .LBB12_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB12_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ult float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -504,6 +858,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB13_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_ule: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: flt.s a0, a1, a0 +; RV32IZFINX-NEXT: beqz a0, .LBB13_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB13_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_ule: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: flt.s a0, a1, a0 +; RV64IZFINX-NEXT: beqz a0, .LBB13_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB13_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp ule float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -539,6 +919,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB14_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_une: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: feq.s a0, a0, a1 +; RV32IZFINX-NEXT: beqz a0, .LBB14_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB14_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_une: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: feq.s a0, a0, a1 +; RV64IZFINX-NEXT: beqz a0, .LBB14_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB14_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp une float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -579,6 +985,36 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB15_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_uno: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: feq.s a1, a1, a1 +; RV32IZFINX-NEXT: feq.s a0, a0, a0 +; RV32IZFINX-NEXT: and a0, a0, a1 +; RV32IZFINX-NEXT: beqz a0, .LBB15_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB15_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_uno: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: feq.s a1, a1, a1 +; RV64IZFINX-NEXT: feq.s a0, a0, a0 +; RV64IZFINX-NEXT: and a0, a0, a1 +; RV64IZFINX-NEXT: beqz a0, .LBB15_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB15_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp uno float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -614,6 +1050,32 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB16_2: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_true: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: li a0, 1 +; RV32IZFINX-NEXT: bnez a0, .LBB16_2 +; RV32IZFINX-NEXT: # %bb.1: # %if.else +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB16_2: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_true: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: li a0, 1 +; RV64IZFINX-NEXT: bnez a0, .LBB16_2 +; RV64IZFINX-NEXT: # %bb.1: # %if.else +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB16_2: # %if.then +; RV64IZFINX-NEXT: call abort@plt %1 = fcmp true float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -674,6 +1136,48 @@ ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB17_3: # %if.then ; RV64IF-NEXT: call abort@plt +; +; RV32IZFINX-LABEL: br_fcmp_store_load_stack_slot: +; RV32IZFINX: # %bb.0: # %entry +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: call dummy@plt +; RV32IZFINX-NEXT: feq.s a0, a0, zero +; RV32IZFINX-NEXT: beqz a0, .LBB17_3 +; RV32IZFINX-NEXT: # %bb.1: # %if.end +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: call dummy@plt +; RV32IZFINX-NEXT: feq.s a0, a0, zero +; RV32IZFINX-NEXT: beqz a0, .LBB17_3 +; RV32IZFINX-NEXT: # %bb.2: # %if.end4 +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB17_3: # %if.then +; RV32IZFINX-NEXT: call abort@plt +; +; RV64IZFINX-LABEL: br_fcmp_store_load_stack_slot: +; RV64IZFINX: # %bb.0: # %entry +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: call dummy@plt +; RV64IZFINX-NEXT: feq.s a0, a0, zero +; RV64IZFINX-NEXT: beqz a0, .LBB17_3 +; RV64IZFINX-NEXT: # %bb.1: # %if.end +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: call dummy@plt +; RV64IZFINX-NEXT: feq.s a0, a0, zero +; RV64IZFINX-NEXT: beqz a0, .LBB17_3 +; RV64IZFINX-NEXT: # %bb.2: # %if.end4 +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB17_3: # %if.then +; RV64IZFINX-NEXT: call abort@plt entry: %call = call float @dummy(float 0.000000e+00) %cmp = fcmp une float %call, 0.000000e+00 diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll --- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll @@ -1,10 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=ilp32 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=lp64 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ @@ -15,15 +21,15 @@ ; support rounding mode. define i32 @fcvt_w_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_w_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_w_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_w_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s: ; RV32I: # %bb.0: @@ -48,15 +54,15 @@ declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) define i32 @fcvt_wu_s(float %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_wu_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_wu_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_wu_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s: ; RV32I: # %bb.0: @@ -83,25 +89,25 @@ ; Test where the fptoui has multiple uses, one of which causes a sext to be ; inserted on RV64. define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind { -; RV32IF-LABEL: fcvt_wu_s_multiple_use: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: beqz a1, .LBB2_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: .LBB2_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_multiple_use: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: beqz a1, .LBB2_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: .LBB2_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_multiple_use: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a1, fa0, rtz +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: beqz a1, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_wu_s_multiple_use: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a1, a0, rtz +; CHECKZFINX-NEXT: li a0, 1 +; CHECKZFINX-NEXT: beqz a1, .LBB2_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: mv a0, a1 +; CHECKZFINX-NEXT: .LBB2_2: +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_multiple_use: ; RV32I: # %bb.0: @@ -139,15 +145,15 @@ } define float @fcvt_s_w(i32 %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w: ; RV32I: # %bb.0: @@ -173,17 +179,17 @@ declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata) define float @fcvt_s_w_load(i32* %p) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_load: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lw a0, 0(a0) -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_load: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lw a0, 0(a0) -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_load: +; CHECK: # %bb.0: +; CHECK-NEXT: lw a0, 0(a0) +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_s_w_load: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: lw a0, 0(a0) +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_load: ; RV32I: # %bb.0: @@ -210,15 +216,15 @@ } define float @fcvt_s_wu(i32 %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu: ; RV32I: # %bb.0: @@ -256,6 +262,18 @@ ; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_wu_load: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lw a0, 0(a0) +; RV32IZFINX-NEXT: fcvt.s.wu a0, a0 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_wu_load: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: lwu a0, 0(a0) +; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_wu_load: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -295,6 +313,20 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_l_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_l_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_l_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -332,6 +364,20 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_lu_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_lu_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_lu_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -369,6 +415,20 @@ ; RV64IF-NEXT: fcvt.s.l fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_l: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __floatdisf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_l: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.s.l a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_l: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -406,6 +466,20 @@ ; RV64IF-NEXT: fcvt.s.lu fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_lu: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __floatundisf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_lu: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.s.lu a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_lu: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -429,15 +503,15 @@ declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata) define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w_i8: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i8: ; RV32I: # %bb.0: @@ -462,15 +536,15 @@ declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata) define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu_i8: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i8: ; RV32I: # %bb.0: @@ -495,15 +569,15 @@ declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata) define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_w_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w_i16: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i16: ; RV32I: # %bb.0: @@ -528,15 +602,15 @@ declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata) define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp { -; RV32IF-LABEL: fcvt_s_wu_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu_i16: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i16: ; RV32I: # %bb.0: @@ -576,6 +650,22 @@ ; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi a0, a0, 1 +; RV32IZFINX-NEXT: fcvt.s.w a2, a0 +; RV32IZFINX-NEXT: sw a2, 0(a1) +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addiw a2, a0, 1 +; RV64IZFINX-NEXT: addi a0, a0, 1 +; RV64IZFINX-NEXT: fcvt.s.w a0, a0 +; RV64IZFINX-NEXT: sw a0, 0(a1) +; RV64IZFINX-NEXT: mv a0, a2 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_w_demanded_bits: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -633,6 +723,20 @@ ; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi a0, a0, 1 +; RV32IZFINX-NEXT: fcvt.s.wu a2, a0 +; RV32IZFINX-NEXT: sw a2, 0(a1) +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addiw a0, a0, 1 +; RV64IZFINX-NEXT: fcvt.s.wu a2, a0 +; RV64IZFINX-NEXT: sw a2, 0(a1) +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_wu_demanded_bits: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -1,23 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s define i32 @fcvt_w_s(float %a) nounwind { -; RV32IF-LABEL: fcvt_w_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_w_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_w_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s: ; RV32I: # %bb.0: @@ -41,23 +45,25 @@ } define i32 @fcvt_w_s_sat(float %a) nounwind { -; RV32IF-LABEL: fcvt_w_s_sat: -; RV32IF: # %bb.0: # %start -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB1_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: .LBB1_2: # %start -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_w_s_sat: -; RV64IF: # %bb.0: # %start -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB1_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: .LBB1_2: # %start -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_w_s_sat: +; CHECK: # %bb.0: # %start +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: .LBB1_2: # %start +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_w_s_sat: +; CHECKZFINX: # %bb.0: # %start +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB1_2 +; CHECKZFINX-NEXT: # %bb.1: # %start +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB1_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_w_s_sat: ; RV32I: # %bb.0: # %start @@ -159,15 +165,15 @@ declare i32 @llvm.fptosi.sat.i32.f32(float) define i32 @fcvt_wu_s(float %a) nounwind { -; RV32IF-LABEL: fcvt_wu_s: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_wu_s: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_wu_s: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s: ; RV32I: # %bb.0: @@ -193,25 +199,25 @@ ; Test where the fptoui has multiple uses, one of which causes a sext to be ; inserted on RV64. define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind { -; RV32IF-LABEL: fcvt_wu_s_multiple_use: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: beqz a1, .LBB3_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: .LBB3_2: -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_multiple_use: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: beqz a1, .LBB3_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: .LBB3_2: -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_multiple_use: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a1, fa0, rtz +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: beqz a1, .LBB3_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_wu_s_multiple_use: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a1, a0, rtz +; CHECKZFINX-NEXT: li a0, 1 +; CHECKZFINX-NEXT: beqz a1, .LBB3_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: mv a0, a1 +; CHECKZFINX-NEXT: .LBB3_2: +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_multiple_use: ; RV32I: # %bb.0: @@ -249,23 +255,25 @@ } define i32 @fcvt_wu_s_sat(float %a) nounwind { -; RV32IF-LABEL: fcvt_wu_s_sat: -; RV32IF: # %bb.0: # %start -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB4_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: .LBB4_2: # %start -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_wu_s_sat: -; RV64IF: # %bb.0: # %start -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB4_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: .LBB4_2: # %start -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_wu_s_sat: +; CHECK: # %bb.0: # %start +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: .LBB4_2: # %start +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_wu_s_sat: +; CHECKZFINX: # %bb.0: # %start +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB4_2 +; CHECKZFINX-NEXT: # %bb.1: # %start +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB4_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_wu_s_sat: ; RV32I: # %bb.0: # %start @@ -343,17 +351,16 @@ declare i32 @llvm.fptoui.sat.i32.f32(float) define i32 @fmv_x_w(float %a, float %b) nounwind { -; RV32IF-LABEL: fmv_x_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fmv.x.w a0, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmv_x_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fmv.x.w a0, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmv_x_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fmv.x.w a0, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmv_x_w: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmv_x_w: ; RV32I: # %bb.0: @@ -379,15 +386,15 @@ } define float @fcvt_s_w(i32 %a) nounwind { -; RV32IF-LABEL: fcvt_s_w: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w: ; RV32I: # %bb.0: @@ -412,17 +419,17 @@ } define float @fcvt_s_w_load(i32* %p) nounwind { -; RV32IF-LABEL: fcvt_s_w_load: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lw a0, 0(a0) -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcvt_s_w_load: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lw a0, 0(a0) -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_load: +; CHECK: # %bb.0: +; CHECK-NEXT: lw a0, 0(a0) +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcvt_s_w_load: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: lw a0, 0(a0) +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_load: ; RV32I: # %bb.0: @@ -449,15 +456,15 @@ } define float @fcvt_s_wu(i32 %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu: ; RV32I: # %bb.0: @@ -494,6 +501,18 @@ ; RV64IF-NEXT: fcvt.s.wu fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_wu_load: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lw a0, 0(a0) +; RV32IZFINX-NEXT: fcvt.s.wu a0, a0 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_wu_load: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: lwu a0, 0(a0) +; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_wu_load: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -519,19 +538,17 @@ } define float @fmv_w_x(i32 %a, i32 %b) nounwind { -; RV32IF-LABEL: fmv_w_x: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: fmv.w.x ft1, a1 -; RV32IF-NEXT: fadd.s fa0, ft0, ft1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fmv_w_x: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fmv.w.x ft1, a1 -; RV64IF-NEXT: fadd.s fa0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fmv_w_x: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: fmv.w.x ft1, a1 +; CHECK-NEXT: fadd.s fa0, ft0, ft1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fmv_w_x: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmv_w_x: ; RV32I: # %bb.0: @@ -572,6 +589,20 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_l_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_l_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_l_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -658,6 +689,72 @@ ; RV64IF-NEXT: .LBB12_2: # %start ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_l_s_sat: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI12_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI12_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB12_2 +; RV32IZFINX-NEXT: # %bb.1: # %start +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB12_2: # %start +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI12_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI12_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB12_9 +; RV32IZFINX-NEXT: # %bb.3: # %start +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB12_10 +; RV32IZFINX-NEXT: .LBB12_4: # %start +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB12_11 +; RV32IZFINX-NEXT: .LBB12_5: # %start +; RV32IZFINX-NEXT: bnez a3, .LBB12_12 +; RV32IZFINX-NEXT: .LBB12_6: # %start +; RV32IZFINX-NEXT: bnez a2, .LBB12_8 +; RV32IZFINX-NEXT: .LBB12_7: # %start +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB12_8: # %start +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB12_9: # %start +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB12_4 +; RV32IZFINX-NEXT: .LBB12_10: # %start +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB12_5 +; RV32IZFINX-NEXT: .LBB12_11: # %start +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB12_6 +; RV32IZFINX-NEXT: .LBB12_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB12_7 +; RV32IZFINX-NEXT: j .LBB12_8 +; +; RV64IZFINX-LABEL: fcvt_l_s_sat: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB12_2 +; RV64IZFINX-NEXT: # %bb.1: # %start +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB12_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_l_s_sat: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -32 @@ -805,6 +902,20 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_lu_s: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_lu_s: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_lu_s: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -878,6 +989,58 @@ ; RV64IF-NEXT: .LBB14_2: # %start ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_lu_s_sat: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB14_2 +; RV32IZFINX-NEXT: # %bb.1: # %start +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB14_2: # %start +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI14_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI14_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB14_7 +; RV32IZFINX-NEXT: # %bb.3: # %start +; RV32IZFINX-NEXT: beqz s1, .LBB14_8 +; RV32IZFINX-NEXT: .LBB14_4: # %start +; RV32IZFINX-NEXT: bnez a4, .LBB14_6 +; RV32IZFINX-NEXT: .LBB14_5: # %start +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB14_6: # %start +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB14_7: # %start +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB14_4 +; RV32IZFINX-NEXT: .LBB14_8: # %start +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB14_5 +; RV32IZFINX-NEXT: j .LBB14_6 +; +; RV64IZFINX-LABEL: fcvt_lu_s_sat: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB14_2 +; RV64IZFINX-NEXT: # %bb.1: # %start +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB14_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_lu_s_sat: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -32 @@ -993,6 +1156,20 @@ ; RV64IF-NEXT: fcvt.s.l fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_l: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __floatdisf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_l: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.s.l a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_l: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1029,6 +1206,20 @@ ; RV64IF-NEXT: fcvt.s.lu fa0, a0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_lu: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __floatundisf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_lu: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.s.lu a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_lu: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1051,15 +1242,15 @@ } define float @fcvt_s_w_i8(i8 signext %a) nounwind { -; RV32IF-LABEL: fcvt_s_w_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w_i8: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i8: ; RV32I: # %bb.0: @@ -1083,15 +1274,15 @@ } define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu_i8: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu_i8: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu_i8: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i8: ; RV32I: # %bb.0: @@ -1115,15 +1306,15 @@ } define float @fcvt_s_w_i16(i16 signext %a) nounwind { -; RV32IF-LABEL: fcvt_s_w_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_w_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.w fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_w_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_w_i16: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.w a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_w_i16: ; RV32I: # %bb.0: @@ -1147,15 +1338,15 @@ } define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { -; RV32IF-LABEL: fcvt_s_wu_i16: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu fa0, a0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcvt_s_wu_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.s.wu fa0, a0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcvt_s_wu_i16: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu fa0, a0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcvt_s_wu_i16: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.s.wu a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcvt_s_wu_i16: ; RV32I: # %bb.0: @@ -1194,6 +1385,22 @@ ; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi a0, a0, 1 +; RV32IZFINX-NEXT: fcvt.s.w a2, a0 +; RV32IZFINX-NEXT: sw a2, 0(a1) +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addiw a2, a0, 1 +; RV64IZFINX-NEXT: addi a0, a0, 1 +; RV64IZFINX-NEXT: fcvt.s.w a0, a0 +; RV64IZFINX-NEXT: sw a0, 0(a1) +; RV64IZFINX-NEXT: mv a0, a2 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_w_demanded_bits: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1251,6 +1458,20 @@ ; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi a0, a0, 1 +; RV32IZFINX-NEXT: fcvt.s.wu a2, a0 +; RV32IZFINX-NEXT: sw a2, 0(a1) +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addiw a0, a0, 1 +; RV64IZFINX-NEXT: fcvt.s.wu a2, a0 +; RV64IZFINX-NEXT: sw a2, 0(a1) +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_s_wu_demanded_bits: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1303,6 +1524,16 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_w_s_i16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_w_s_i16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_w_s_i16: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1355,6 +1586,40 @@ ; RV64IF-NEXT: .LBB24_2: # %start ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_w_s_sat_i16: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: feq.s a1, a0, a0 +; RV32IZFINX-NEXT: bnez a1, .LBB24_2 +; RV32IZFINX-NEXT: # %bb.1: # %start +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB24_2: +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI24_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI24_0)(a1) +; RV32IZFINX-NEXT: lui a2, %hi(.LCPI24_1) +; RV32IZFINX-NEXT: lw a2, %lo(.LCPI24_1)(a2) +; RV32IZFINX-NEXT: fmax.s a0, a0, a1 +; RV32IZFINX-NEXT: fmin.s a0, a0, a2 +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_w_s_sat_i16: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB24_2 +; RV64IZFINX-NEXT: # %bb.1: # %start +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB24_2: +; RV64IZFINX-NEXT: lui a1, %hi(.LCPI24_0) +; RV64IZFINX-NEXT: lw a1, %lo(.LCPI24_0)(a1) +; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_1) +; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_1)(a2) +; RV64IZFINX-NEXT: fmax.s a0, a0, a1 +; RV64IZFINX-NEXT: fmin.s a0, a0, a2 +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -32 @@ -1463,6 +1728,16 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_wu_s_i16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_wu_s_i16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_wu_s_i16: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1505,6 +1780,24 @@ ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI26_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1) +; RV32IZFINX-NEXT: fmax.s a0, a0, zero +; RV32IZFINX-NEXT: fmin.s a0, a0, a1 +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: lui a1, %hi(.LCPI26_0) +; RV64IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1) +; RV64IZFINX-NEXT: fmax.s a0, a0, zero +; RV64IZFINX-NEXT: fmin.s a0, a0, a1 +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_wu_s_sat_i16: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -16 @@ -1595,6 +1888,16 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_w_s_i8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_w_s_i8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_w_s_i8: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1647,6 +1950,40 @@ ; RV64IF-NEXT: .LBB28_2: # %start ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_w_s_sat_i8: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: feq.s a1, a0, a0 +; RV32IZFINX-NEXT: bnez a1, .LBB28_2 +; RV32IZFINX-NEXT: # %bb.1: # %start +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB28_2: +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI28_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI28_0)(a1) +; RV32IZFINX-NEXT: lui a2, %hi(.LCPI28_1) +; RV32IZFINX-NEXT: lw a2, %lo(.LCPI28_1)(a2) +; RV32IZFINX-NEXT: fmax.s a0, a0, a1 +; RV32IZFINX-NEXT: fmin.s a0, a0, a2 +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_w_s_sat_i8: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB28_2 +; RV64IZFINX-NEXT: # %bb.1: # %start +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB28_2: +; RV64IZFINX-NEXT: lui a1, %hi(.LCPI28_0) +; RV64IZFINX-NEXT: lw a1, %lo(.LCPI28_0)(a1) +; RV64IZFINX-NEXT: lui a2, %hi(.LCPI28_1) +; RV64IZFINX-NEXT: lw a2, %lo(.LCPI28_1)(a2) +; RV64IZFINX-NEXT: fmax.s a0, a0, a1 +; RV64IZFINX-NEXT: fmin.s a0, a0, a2 +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -32 @@ -1753,6 +2090,16 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_wu_s_i8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_wu_s_i8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_wu_s_i8: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1795,6 +2142,24 @@ ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: fcvt_wu_s_sat_i8: +; RV32IZFINX: # %bb.0: # %start +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI30_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI30_0)(a1) +; RV32IZFINX-NEXT: fmax.s a0, a0, zero +; RV32IZFINX-NEXT: fmin.s a0, a0, a1 +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fcvt_wu_s_sat_i8: +; RV64IZFINX: # %bb.0: # %start +; RV64IZFINX-NEXT: lui a1, %hi(.LCPI30_0) +; RV64IZFINX-NEXT: lw a1, %lo(.LCPI30_0)(a1) +; RV64IZFINX-NEXT: fmax.s a0, a0, zero +; RV64IZFINX-NEXT: fmin.s a0, a0, a1 +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fcvt_wu_s_sat_i8: ; RV32I: # %bb.0: # %start ; RV32I-NEXT: addi sp, sp, -16 diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll --- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll @@ -1,25 +1,31 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=ilp32 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -disable-strictnode-mutation -target-abi=lp64 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_oeq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_oeq: ; RV32I: # %bb.0: @@ -47,21 +53,22 @@ declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata) define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ogt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a3 +; CHECKZFINX-NEXT: flt.s a2, a1, a0 +; CHECKZFINX-NEXT: fsflags a3 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ogt: ; RV32I: # %bb.0: @@ -88,21 +95,22 @@ } define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_oge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a3 +; CHECKZFINX-NEXT: fle.s a2, a1, a0 +; CHECKZFINX-NEXT: fsflags a3 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_oge: ; RV32I: # %bb.0: @@ -131,21 +139,22 @@ } define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_olt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a3 +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: fsflags a3 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_olt: ; RV32I: # %bb.0: @@ -172,21 +181,22 @@ } define i32 @fcmp_ole(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a1 -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: fsflags a1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a1 -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: fsflags a1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a1 +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: fsflags a1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ole: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a3 +; CHECKZFINX-NEXT: fle.s a2, a0, a1 +; CHECKZFINX-NEXT: fsflags a3 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ole: ; RV32I: # %bb.0: @@ -215,31 +225,32 @@ ; FIXME: We only need one frflags before the two flts and one fsflags after the ; two flts. define i32 @fcmp_one(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a2, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: or a0, a2, a1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a2, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: or a0, a2, a1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_one: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a2, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: or a0, a2, a1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_one: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a3, a0, a1 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a4, a1, a0 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: or a2, a4, a3 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_one: ; RV32I: # %bb.0: @@ -292,19 +303,19 @@ } define i32 @fcmp_ord(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ord: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a1, a1 +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ord: ; RV32I: # %bb.0: @@ -333,33 +344,34 @@ ; FIXME: We only need one frflags before the two flts and one fsflags after the ; two flts. define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a2, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: or a0, a2, a1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a2, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: or a0, a2, a1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a2, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: or a0, a2, a1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ueq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a3, a0, a1 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a4, a1, a0 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: or a2, a4, a3 +; CHECKZFINX-NEXT: xori a2, a2, 1 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ueq: ; RV32I: # %bb.0: @@ -412,23 +424,24 @@ } define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ugt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: fle.s a3, a0, a1 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: xori a2, a3, 1 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: ; RV32I: # %bb.0: @@ -455,23 +468,24 @@ } define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa0, fa1 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa0, fa1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa0, fa1 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa0, fa1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa0, fa1 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa0, fa1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_uge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a3, a0, a1 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: xori a2, a3, 1 +; CHECKZFINX-NEXT: feq.s zero, a0, a1 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: ; RV32I: # %bb.0: @@ -500,23 +514,24 @@ } define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: fle.s a1, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: fle.s a1, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: fle.s a1, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ult: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: fle.s a3, a1, a0 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: xori a2, a3, 1 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: ; RV32I: # %bb.0: @@ -543,23 +558,24 @@ } define i32 @fcmp_ule(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: frflags a0 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: fsflags a0 -; RV32IF-NEXT: xori a0, a1, 1 -; RV32IF-NEXT: feq.s zero, fa1, fa0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: frflags a0 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: fsflags a0 -; RV64IF-NEXT: xori a0, a1, 1 -; RV64IF-NEXT: feq.s zero, fa1, fa0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: frflags a0 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: fsflags a0 +; CHECK-NEXT: xori a0, a1, 1 +; CHECK-NEXT: feq.s zero, fa1, fa0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ule: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: frflags a2 +; CHECKZFINX-NEXT: flt.s a3, a1, a0 +; CHECKZFINX-NEXT: fsflags a2 +; CHECKZFINX-NEXT: xori a2, a3, 1 +; CHECKZFINX-NEXT: feq.s zero, a1, a0 +; CHECKZFINX-NEXT: mv a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: ; RV32I: # %bb.0: @@ -586,17 +602,17 @@ } define i32 @fcmp_une(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_une: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_une: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_une: ; RV32I: # %bb.0: @@ -623,21 +639,21 @@ } define i32 @fcmp_uno(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmp_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_uno: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a1, a1 +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uno: ; RV32I: # %bb.0: @@ -664,19 +680,19 @@ } define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_oeq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a2, a1, a0 +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: and a0, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_oeq: ; RV32I: # %bb.0: @@ -704,15 +720,15 @@ declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata) define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmps_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmps_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmps_ogt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ogt: ; RV32I: # %bb.0: @@ -739,15 +755,15 @@ } define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmps_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmps_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmps_oge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a1, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_oge: ; RV32I: # %bb.0: @@ -776,15 +792,15 @@ } define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmps_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmps_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmps_olt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_olt: ; RV32I: # %bb.0: @@ -811,15 +827,15 @@ } define i32 @fcmps_ole(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmps_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmps_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmps_ole: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ole: ; RV32I: # %bb.0: @@ -846,19 +862,19 @@ } define i32 @fcmps_one(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_one: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_one: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: or a0, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_one: ; RV32I: # %bb.0: @@ -911,19 +927,19 @@ } define i32 @fcmps_ord(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa1 -; RV32IF-NEXT: fle.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa1 -; RV64IF-NEXT: fle.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa1 +; CHECK-NEXT: fle.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_ord: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a1, a1, a1 +; CHECKZFINX-NEXT: fle.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ord: ; RV32I: # %bb.0: @@ -950,21 +966,21 @@ } define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_ueq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: or a0, a0, a2 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ueq: ; RV32I: # %bb.0: @@ -1017,17 +1033,17 @@ } define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_ugt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ugt: ; RV32I: # %bb.0: @@ -1054,17 +1070,17 @@ } define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_uge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_uge: ; RV32I: # %bb.0: @@ -1093,17 +1109,17 @@ } define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_ult: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a1, a0 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ult: ; RV32I: # %bb.0: @@ -1130,17 +1146,17 @@ } define i32 @fcmps_ule(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_ule: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_ule: ; RV32I: # %bb.0: @@ -1167,21 +1183,21 @@ } define i32 @fcmps_une(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: fle.s a1, fa0, fa1 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: fle.s a1, fa0, fa1 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_une: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: fle.s a1, fa0, fa1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_une: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a2, a1, a0 +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: and a0, a0, a2 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_une: ; RV32I: # %bb.0: @@ -1208,21 +1224,21 @@ } define i32 @fcmps_uno(float %a, float %b) nounwind strictfp { -; RV32IF-LABEL: fcmps_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa1 -; RV32IF-NEXT: fle.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmps_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa1 -; RV64IF-NEXT: fle.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmps_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa1 +; CHECK-NEXT: fle.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmps_uno: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a1, a1, a1 +; CHECKZFINX-NEXT: fle.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmps_uno: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -1,23 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s define i32 @fcmp_false(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_false: -; RV32IF: # %bb.0: -; RV32IF-NEXT: li a0, 0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_false: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_false: -; RV64IF: # %bb.0: -; RV64IF-NEXT: li a0, 0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_false: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_false: ; RV32I: # %bb.0: @@ -34,15 +38,15 @@ } define i32 @fcmp_oeq(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_oeq: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_oeq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_oeq: ; RV32I: # %bb.0: @@ -69,15 +73,15 @@ } define i32 @fcmp_ogt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_ogt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ogt: ; RV32I: # %bb.0: @@ -104,15 +108,15 @@ } define i32 @fcmp_oge(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_oge: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_oge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a1, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_oge: ; RV32I: # %bb.0: @@ -141,15 +145,15 @@ } define i32 @fcmp_olt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_olt: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_olt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_olt: ; RV32I: # %bb.0: @@ -176,15 +180,15 @@ } define i32 @fcmp_ole(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: ret +; CHECK-LABEL: fcmp_ole: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fcmp_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fcmp_ole: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ole: ; RV32I: # %bb.0: @@ -211,19 +215,19 @@ } define i32 @fcmp_one(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_one: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_one: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: or a0, a0, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_one: ; RV32I: # %bb.0: @@ -276,19 +280,19 @@ } define i32 @fcmp_ord(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ord: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ord: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a1, a1 +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ord: ; RV32I: # %bb.0: @@ -315,21 +319,21 @@ } define i32 @fcmp_ueq(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ueq: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: flt.s a1, fa1, fa0 +; CHECK-NEXT: or a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ueq: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: or a0, a0, a2 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ueq: ; RV32I: # %bb.0: @@ -382,17 +386,17 @@ } define i32 @fcmp_ugt(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ugt: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: ; RV32I: # %bb.0: @@ -419,17 +423,17 @@ } define i32 @fcmp_uge(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uge: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_uge: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: ; RV32I: # %bb.0: @@ -458,17 +462,17 @@ } define i32 @fcmp_ult(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ult: +; CHECK: # %bb.0: +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ult: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fle.s a0, a1, a0 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: ; RV32I: # %bb.0: @@ -495,17 +499,17 @@ } define i32 @fcmp_ule(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_ule: +; CHECK: # %bb.0: +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_ule: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: ; RV32I: # %bb.0: @@ -532,17 +536,17 @@ } define i32 @fcmp_une(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_une: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa1 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_une: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_une: ; RV32I: # %bb.0: @@ -569,21 +573,21 @@ } define i32 @fcmp_uno(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_uno: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa1, fa1 +; CHECK-NEXT: feq.s a1, fa0, fa0 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_uno: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a1, a1 +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: and a0, a0, a1 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uno: ; RV32I: # %bb.0: @@ -610,15 +614,15 @@ } define i32 @fcmp_true(float %a, float %b) nounwind { -; RV32IF-LABEL: fcmp_true: -; RV32IF: # %bb.0: -; RV32IF-NEXT: li a0, 1 -; RV32IF-NEXT: ret -; -; RV64IF-LABEL: fcmp_true: -; RV64IF: # %bb.0: -; RV64IF-NEXT: li a0, 1 -; RV64IF-NEXT: ret +; CHECK-LABEL: fcmp_true: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: ret +; +; CHECKZFINX-LABEL: fcmp_true: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: li a0, 1 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_true: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll --- a/llvm/test/CodeGen/RISCV/float-frem.ll +++ b/llvm/test/CodeGen/RISCV/float-frem.ll @@ -3,6 +3,10 @@ ; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64IZFINX %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ @@ -27,6 +31,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: frem_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call fmodf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: frem_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call fmodf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: frem_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll --- a/llvm/test/CodeGen/RISCV/float-imm.ll +++ b/llvm/test/CodeGen/RISCV/float-imm.ll @@ -1,39 +1,49 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX %s ; TODO: constant pool shouldn't be necessary for RV64IF. define float @float_imm() nounwind { -; RV32IF-LABEL: float_imm: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lui a0, %hi(.LCPI0_0) -; RV32IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0) -; RV32IF-NEXT: ret +; CHECK-LABEL: float_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI0_0) +; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0) +; CHECK-NEXT: ret ; -; RV64IF-LABEL: float_imm: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lui a0, %hi(.LCPI0_0) -; RV64IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0) -; RV64IF-NEXT: ret +; RV32IZFINX-LABEL: float_imm: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lui a0, 263313 +; RV32IZFINX-NEXT: addi a0, a0, -37 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: float_imm: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: lui a0, %hi(.LCPI0_0) +; RV64IZFINX-NEXT: lw a0, %lo(.LCPI0_0)(a0) +; RV64IZFINX-NEXT: ret ret float 3.14159274101257324218750 } define float @float_imm_op(float %a) nounwind { -; RV32IF-LABEL: float_imm_op: -; RV32IF: # %bb.0: -; RV32IF-NEXT: lui a0, %hi(.LCPI1_0) -; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) -; RV32IF-NEXT: fadd.s fa0, fa0, ft0 -; RV32IF-NEXT: ret +; CHECK-LABEL: float_imm_op: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI1_0) +; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a0) +; CHECK-NEXT: fadd.s fa0, fa0, ft0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: float_imm_op: -; RV64IF: # %bb.0: -; RV64IF-NEXT: lui a0, %hi(.LCPI1_0) -; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) -; RV64IF-NEXT: fadd.s fa0, fa0, ft0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: float_imm_op: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: lui a1, %hi(.LCPI1_0) +; CHECKZFINX-NEXT: lw a1, %lo(.LCPI1_0)(a1) +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: ret %1 = fadd float %a, 1.0 ret float %1 } diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll --- a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll @@ -1,10 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \ -; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \ -; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \ +; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \ +; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64 \ +; RUN: | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: -verify-machineinstrs -disable-strictnode-mutation \ ; RUN: | FileCheck -check-prefix=RV32I %s @@ -15,15 +21,15 @@ declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata) define float @sqrt_f32(float %a) nounwind strictfp { -; RV32IF-LABEL: sqrt_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fsqrt.s fa0, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: sqrt_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fsqrt.s fa0, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: sqrt_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fsqrt.s fa0, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: sqrt_f32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fsqrt.s a0, a0 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: sqrt_f32: ; RV32I: # %bb.0: @@ -68,6 +74,25 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: powi_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __powisf2@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: powi_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sext.w a1, a1 +; RV64IZFINX-NEXT: call __powisf2@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: powi_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -111,6 +136,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: sin_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: sin_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: sin_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -153,6 +196,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: cos_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: cos_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: cos_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -212,6 +273,42 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: sincos_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: mv s1, a0 +; RV32IZFINX-NEXT: mv a0, s0 +; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: fadd.s a0, s1, a0 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: sincos_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -32 +; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: mv s0, a0 +; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: mv s1, a0 +; RV64IZFINX-NEXT: mv a0, s0 +; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: fadd.s a0, s1, a0 +; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 32 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: sincos_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -278,6 +375,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: pow_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call powf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: pow_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call powf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: pow_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -320,6 +435,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: exp_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call expf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: exp_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call expf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: exp_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -362,6 +495,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: exp2_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call exp2f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: exp2_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call exp2f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: exp2_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -404,6 +555,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: log_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call logf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: log_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call logf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -446,6 +615,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: log10_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call log10f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: log10_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call log10f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log10_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -488,6 +675,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: log2_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call log2f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: log2_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call log2f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log2_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -512,15 +717,15 @@ declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) define float @fma_f32(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fma_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fma_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fma_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fma_f32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fma_f32: ; RV32I: # %bb.0: @@ -546,15 +751,15 @@ declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata) define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp { -; RV32IF-LABEL: fmuladd_f32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV32IF-NEXT: ret +; CHECK-LABEL: fmuladd_f32: +; CHECK: # %bb.0: +; CHECK-NEXT: fmadd.s fa0, fa0, fa1, fa2 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fmuladd_f32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fmuladd_f32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; CHECKZFINX-NEXT: ret ; ; RV32I-LABEL: fmuladd_f32: ; RV32I: # %bb.0: @@ -608,6 +813,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: minnum_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call fminf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: minnum_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call fminf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: minnum_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -650,6 +873,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: maxnum_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call fmaxf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: maxnum_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call fmaxf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: maxnum_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -709,6 +950,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: floor_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: floor_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call floorf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: floor_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -751,6 +1010,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: ceil_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: ceil_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call ceilf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: ceil_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -793,6 +1070,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: trunc_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: trunc_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call truncf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: trunc_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -835,6 +1130,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: rint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call rintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: rint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call rintf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: rint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -877,6 +1190,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: nearbyint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call nearbyintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: nearbyint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call nearbyintf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: nearbyint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -919,6 +1250,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: round_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: round_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call roundf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: round_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -961,6 +1310,24 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: roundeven_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: roundeven_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call roundevenf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: roundeven_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -995,6 +1362,16 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: lrint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: lrint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: lrint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1029,6 +1406,16 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: lround_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: lround_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: lround_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1067,6 +1454,20 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0 ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: llrint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call llrintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: llrint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: llrint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1105,6 +1506,20 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret ; +; RV32IZFINX-LABEL: llround_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call llroundf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: llround_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: llround_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -2,12 +2,18 @@ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ ; RUN: -verify-machineinstrs -target-abi=ilp32f \ ; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \ +; RUN: -verify-machineinstrs -target-abi=ilp32 \ +; RUN: | FileCheck -check-prefix=RV32IZFINX %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ ; RUN: -verify-machineinstrs -target-abi=ilp32f \ ; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ ; RUN: -verify-machineinstrs -target-abi=lp64f \ ; RUN: | FileCheck -check-prefix=RV64IF %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \ +; RUN: -verify-machineinstrs -target-abi=lp64 \ +; RUN: | FileCheck -check-prefix=RV64IZFINX %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ ; RUN: -verify-machineinstrs -target-abi=lp64d \ ; RUN: | FileCheck -check-prefix=RV64IF %s @@ -24,11 +30,21 @@ ; RV32IF-NEXT: fsqrt.s fa0, fa0 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: sqrt_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fsqrt.s a0, a0 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: sqrt_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsqrt.s fa0, fa0 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: sqrt_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fsqrt.s a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: sqrt_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -62,6 +78,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: powi_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call __powisf2@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: powi_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -72,6 +97,16 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: powi_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sext.w a1, a1 +; RV64IZFINX-NEXT: call __powisf2@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: powi_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -106,6 +141,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: sin_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: sin_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -115,6 +159,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: sin_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: sin_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -148,6 +201,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: cos_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: cos_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -157,6 +219,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: cos_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: cos_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -198,6 +269,42 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: sincos_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: call sinf@plt +; RV32IZFINX-NEXT: mv s1, a0 +; RV32IZFINX-NEXT: mv a0, s0 +; RV32IZFINX-NEXT: call cosf@plt +; RV32IZFINX-NEXT: fadd.s a0, s1, a0 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: sincos_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -32 +; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: mv s0, a0 +; RV64IZFINX-NEXT: call sinf@plt +; RV64IZFINX-NEXT: mv s1, a0 +; RV64IZFINX-NEXT: mv a0, s0 +; RV64IZFINX-NEXT: call cosf@plt +; RV64IZFINX-NEXT: fadd.s a0, s1, a0 +; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 32 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: sincos_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -255,6 +362,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: pow_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call powf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: pow_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -264,6 +380,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: pow_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call powf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: pow_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -297,6 +422,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: exp_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call expf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: exp_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -306,6 +440,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: exp_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call expf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: exp_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -339,6 +482,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: exp2_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call exp2f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: exp2_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -348,6 +500,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: exp2_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call exp2f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: exp2_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -381,6 +542,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: log_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call logf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: log_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -390,6 +560,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: log_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call logf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -423,6 +602,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: log10_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call log10f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: log10_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -432,6 +620,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: log10_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call log10f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log10_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -465,6 +662,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: log2_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call log2f@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: log2_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -474,6 +680,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: log2_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call log2f@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: log2_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -503,11 +718,21 @@ ; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fma_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: fma_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: fma_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fma_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -537,11 +762,21 @@ ; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fmuladd_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: fmuladd_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: fmuladd_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fmuladd_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -581,11 +816,23 @@ ; RV32IF-NEXT: fabs.s fa0, fa0 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: fabs_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: slli a0, a0, 1 +; RV32IZFINX-NEXT: srli a0, a0, 1 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: fabs_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fabs.s fa0, fa0 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: fabs_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: slli a0, a0, 33 +; RV64IZFINX-NEXT: srli a0, a0, 33 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: fabs_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 1 @@ -609,11 +856,21 @@ ; RV32IF-NEXT: fmin.s fa0, fa0, fa1 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: minnum_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fmin.s a0, a0, a1 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: minnum_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmin.s fa0, fa0, fa1 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: minnum_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fmin.s a0, a0, a1 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: minnum_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -643,11 +900,21 @@ ; RV32IF-NEXT: fmax.s fa0, fa0, fa1 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: maxnum_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fmax.s a0, a0, a1 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: maxnum_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmax.s fa0, fa0, fa1 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: maxnum_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fmax.s a0, a0, a1 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: maxnum_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -694,11 +961,21 @@ ; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: copysign_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: copysign_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: copysign_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fsgnj.s a0, a0, a1 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: copysign_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a2, 524288 @@ -732,6 +1009,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: floor_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: floor_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -741,6 +1027,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: floor_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call floorf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: floor_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -774,6 +1069,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: ceil_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: ceil_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -783,6 +1087,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: ceil_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call ceilf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: ceil_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -816,6 +1129,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: trunc_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: trunc_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -825,6 +1147,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: trunc_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call truncf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: trunc_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -858,6 +1189,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: rint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call rintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: rint_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -867,6 +1207,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: rint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call rintf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: rint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -900,6 +1249,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: nearbyint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call nearbyintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: nearbyint_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -909,6 +1267,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: nearbyint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call nearbyintf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: nearbyint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -942,6 +1309,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: round_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: round_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -951,6 +1327,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: round_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call roundf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: round_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -984,6 +1369,15 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: roundeven_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: roundeven_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: addi sp, sp, -16 @@ -993,6 +1387,15 @@ ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: roundeven_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: call roundevenf@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: roundeven_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1022,11 +1425,21 @@ ; RV32IF-NEXT: fcvt.w.s a0, fa0 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: lrint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: lrint_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: lrint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: lrint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1056,11 +1469,21 @@ ; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: lround_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: lround_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: lround_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: lround_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1094,11 +1517,25 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: llrint_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call llrintf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: llrint_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0 ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: llrint_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0 +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: llrint_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 @@ -1132,11 +1569,25 @@ ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; +; RV32IZFINX-LABEL: llround_f32: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call llroundf@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; ; RV64IF-LABEL: llround_f32: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret ; +; RV64IZFINX-LABEL: llround_f32: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret +; ; RV32I-LABEL: llround_f32: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 diff --git a/llvm/test/CodeGen/RISCV/float-isnan.ll b/llvm/test/CodeGen/RISCV/float-isnan.ll --- a/llvm/test/CodeGen/RISCV/float-isnan.ll +++ b/llvm/test/CodeGen/RISCV/float-isnan.ll @@ -1,35 +1,39 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV32IF %s +; RUN: < %s | FileCheck -check-prefixes=CHECK %s ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \ -; RUN: < %s | FileCheck -check-prefix=RV64IF %s +; RUN: < %s | FileCheck -check-prefixes=CHECK %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -target-abi ilp32 -verify-machineinstrs \ +; RUN: < %s | FileCheck -check-prefixes=CHECKZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi lp64 -verify-machineinstrs \ +; RUN: < %s | FileCheck -check-prefixes=CHECKZFINX %s define zeroext i1 @float_is_nan(float %a) nounwind { -; RV32IF-LABEL: float_is_nan: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: xori a0, a0, 1 -; RV32IF-NEXT: ret +; CHECK-LABEL: float_is_nan: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: xori a0, a0, 1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: float_is_nan: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: xori a0, a0, 1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: float_is_nan: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: xori a0, a0, 1 +; CHECKZFINX-NEXT: ret %1 = fcmp uno float %a, 0.000000e+00 ret i1 %1 } define zeroext i1 @float_not_nan(float %a) nounwind { -; RV32IF-LABEL: float_not_nan: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: ret +; CHECK-LABEL: float_not_nan: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: float_not_nan: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: float_not_nan: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a0, a0, a0 +; CHECKZFINX-NEXT: ret %1 = fcmp ord float %a, 0.000000e+00 ret i1 %1 } diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll --- a/llvm/test/CodeGen/RISCV/float-mem.ll +++ b/llvm/test/CodeGen/RISCV/float-mem.ll @@ -1,23 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s define dso_local float @flw(float *%a) nounwind { -; RV32IF-LABEL: flw: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flw ft0, 0(a0) -; RV32IF-NEXT: flw ft1, 12(a0) -; RV32IF-NEXT: fadd.s fa0, ft0, ft1 -; RV32IF-NEXT: ret +; CHECK-LABEL: flw: +; CHECK: # %bb.0: +; CHECK-NEXT: flw ft0, 0(a0) +; CHECK-NEXT: flw ft1, 12(a0) +; CHECK-NEXT: fadd.s fa0, ft0, ft1 +; CHECK-NEXT: ret ; -; RV64IF-LABEL: flw: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flw ft0, 0(a0) -; RV64IF-NEXT: flw ft1, 12(a0) -; RV64IF-NEXT: fadd.s fa0, ft0, ft1 -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: flw: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: lw a1, 0(a0) +; CHECKZFINX-NEXT: lw a0, 12(a0) +; CHECKZFINX-NEXT: fadd.s a0, a1, a0 +; CHECKZFINX-NEXT: ret %1 = load float, float* %a %2 = getelementptr float, float* %a, i32 3 %3 = load float, float* %2 @@ -30,19 +34,19 @@ define dso_local void @fsw(float *%a, float %b, float %c) nounwind { ; Use %b and %c in an FP op to ensure floating point registers are used, even ; for the soft float ABI -; RV32IF-LABEL: fsw: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s ft0, fa0, fa1 -; RV32IF-NEXT: fsw ft0, 0(a0) -; RV32IF-NEXT: fsw ft0, 32(a0) -; RV32IF-NEXT: ret +; CHECK-LABEL: fsw: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s ft0, fa0, fa1 +; CHECK-NEXT: fsw ft0, 0(a0) +; CHECK-NEXT: fsw ft0, 32(a0) +; CHECK-NEXT: ret ; -; RV64IF-LABEL: fsw: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s ft0, fa0, fa1 -; RV64IF-NEXT: fsw ft0, 0(a0) -; RV64IF-NEXT: fsw ft0, 32(a0) -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: fsw: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a1, a1, a2 +; CHECKZFINX-NEXT: sw a1, 0(a0) +; CHECKZFINX-NEXT: sw a1, 32(a0) +; CHECKZFINX-NEXT: ret %1 = fadd float %b, %c store float %1, float* %a %2 = getelementptr float, float* %a, i32 8 @@ -56,27 +60,27 @@ define dso_local float @flw_fsw_global(float %a, float %b) nounwind { ; Use %a and %b in an FP op to ensure floating point registers are used, even ; for the soft float ABI -; RV32IF-LABEL: flw_fsw_global: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fadd.s fa0, fa0, fa1 -; RV32IF-NEXT: lui a0, %hi(G) -; RV32IF-NEXT: flw ft0, %lo(G)(a0) -; RV32IF-NEXT: fsw fa0, %lo(G)(a0) -; RV32IF-NEXT: addi a0, a0, %lo(G) -; RV32IF-NEXT: flw ft0, 36(a0) -; RV32IF-NEXT: fsw fa0, 36(a0) -; RV32IF-NEXT: ret +; CHECK-LABEL: flw_fsw_global: +; CHECK: # %bb.0: +; CHECK-NEXT: fadd.s fa0, fa0, fa1 +; CHECK-NEXT: lui a0, %hi(G) +; CHECK-NEXT: flw ft0, %lo(G)(a0) +; CHECK-NEXT: fsw fa0, %lo(G)(a0) +; CHECK-NEXT: addi a0, a0, %lo(G) +; CHECK-NEXT: flw ft0, 36(a0) +; CHECK-NEXT: fsw fa0, 36(a0) +; CHECK-NEXT: ret ; -; RV64IF-LABEL: flw_fsw_global: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fadd.s fa0, fa0, fa1 -; RV64IF-NEXT: lui a0, %hi(G) -; RV64IF-NEXT: flw ft0, %lo(G)(a0) -; RV64IF-NEXT: fsw fa0, %lo(G)(a0) -; RV64IF-NEXT: addi a0, a0, %lo(G) -; RV64IF-NEXT: flw ft0, 36(a0) -; RV64IF-NEXT: fsw fa0, 36(a0) -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: flw_fsw_global: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fadd.s a0, a0, a1 +; CHECKZFINX-NEXT: lui a1, %hi(G) +; CHECKZFINX-NEXT: lw a2, %lo(G)(a1) +; CHECKZFINX-NEXT: sw a0, %lo(G)(a1) +; CHECKZFINX-NEXT: addi a1, a1, %lo(G) +; CHECKZFINX-NEXT: lw a2, 36(a1) +; CHECKZFINX-NEXT: sw a0, 36(a1) +; CHECKZFINX-NEXT: ret %1 = fadd float %a, %b %2 = load volatile float, float* @G store float %1, float* @G @@ -104,6 +108,23 @@ ; RV64IF-NEXT: fadd.s fa0, fa0, ft0 ; RV64IF-NEXT: fsw fa0, -273(a0) ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: flw_fsw_constant: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: lui a1, 912092 +; RV32IZFINX-NEXT: lw a2, -273(a1) +; RV32IZFINX-NEXT: fadd.s a0, a0, a2 +; RV32IZFINX-NEXT: sw a0, -273(a1) +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: flw_fsw_constant: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: lui a1, 228023 +; RV64IZFINX-NEXT: slli a1, a1, 2 +; RV64IZFINX-NEXT: lw a2, -273(a1) +; RV64IZFINX-NEXT: fadd.s a0, a0, a2 +; RV64IZFINX-NEXT: sw a0, -273(a1) +; RV64IZFINX-NEXT: ret %1 = inttoptr i32 3735928559 to float* %2 = load volatile float, float* %1 %3 = fadd float %a, %2 @@ -143,6 +164,36 @@ ; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: flw_stack: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: addi a0, sp, 4 +; RV32IZFINX-NEXT: call notdead@plt +; RV32IZFINX-NEXT: lw a0, 4(sp) +; RV32IZFINX-NEXT: fadd.s a0, a0, s0 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: flw_stack: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -32 +; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: mv s0, a0 +; RV64IZFINX-NEXT: addi a0, sp, 12 +; RV64IZFINX-NEXT: call notdead@plt +; RV64IZFINX-NEXT: lw a0, 12(sp) +; RV64IZFINX-NEXT: fadd.s a0, a0, s0 +; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 32 +; RV64IZFINX-NEXT: ret %1 = alloca float, align 4 %2 = bitcast float* %1 to i8* call void @notdead(i8* %2) @@ -175,6 +226,30 @@ ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: fsw_stack: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: fadd.s a0, a0, a1 +; RV32IZFINX-NEXT: sw a0, 8(sp) +; RV32IZFINX-NEXT: addi a0, sp, 8 +; RV32IZFINX-NEXT: call notdead@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: fsw_stack: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: addi sp, sp, -16 +; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZFINX-NEXT: fadd.s a0, a0, a1 +; RV64IZFINX-NEXT: sw a0, 4(sp) +; RV64IZFINX-NEXT: addi a0, sp, 4 +; RV64IZFINX-NEXT: call notdead@plt +; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFINX-NEXT: addi sp, sp, 16 +; RV64IZFINX-NEXT: ret %1 = fadd float %a, %b ; force store from FPR32 %2 = alloca float, align 4 store float %1, float* %2 diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -1,27 +1,33 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s define signext i32 @test_floor_si32(float %x) { -; RV32IF-LABEL: test_floor_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB0_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV32IF-NEXT: .LBB0_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_floor_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rdn +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_floor_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB0_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV64IF-NEXT: .LBB0_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_floor_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB0_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB0_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rdn +; CHECKZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -92,29 +98,98 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn ; RV64IF-NEXT: .LBB1_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI1_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI1_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB1_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB1_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI1_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI1_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB1_9 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB1_10 +; RV32IZFINX-NEXT: .LBB1_4: +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB1_11 +; RV32IZFINX-NEXT: .LBB1_5: +; RV32IZFINX-NEXT: bnez a3, .LBB1_12 +; RV32IZFINX-NEXT: .LBB1_6: +; RV32IZFINX-NEXT: bnez a2, .LBB1_8 +; RV32IZFINX-NEXT: .LBB1_7: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB1_8: +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB1_9: +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB1_4 +; RV32IZFINX-NEXT: .LBB1_10: +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB1_5 +; RV32IZFINX-NEXT: .LBB1_11: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB1_6 +; RV32IZFINX-NEXT: .LBB1_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB1_7 +; RV32IZFINX-NEXT: j .LBB1_8 +; +; RV64IZFINX-LABEL: test_floor_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB1_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB1_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i64 @llvm.fptosi.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_floor_ui32(float %x) { -; RV32IF-LABEL: test_floor_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB2_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV32IF-NEXT: .LBB2_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_floor_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rdn +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_floor_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB2_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV64IF-NEXT: .LBB2_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_floor_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB2_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB2_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rdn +; CHECKZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -172,29 +247,84 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn ; RV64IF-NEXT: .LBB3_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB3_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB3_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI3_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI3_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB3_7 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: beqz s1, .LBB3_8 +; RV32IZFINX-NEXT: .LBB3_4: +; RV32IZFINX-NEXT: bnez a4, .LBB3_6 +; RV32IZFINX-NEXT: .LBB3_5: +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB3_6: +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB3_7: +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB3_4 +; RV32IZFINX-NEXT: .LBB3_8: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB3_5 +; RV32IZFINX-NEXT: j .LBB3_6 +; +; RV64IZFINX-LABEL: test_floor_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB3_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB3_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = call i64 @llvm.fptoui.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_ceil_si32(float %x) { -; RV32IF-LABEL: test_ceil_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB4_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rup -; RV32IF-NEXT: .LBB4_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_ceil_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rup +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_ceil_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB4_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rup -; RV64IF-NEXT: .LBB4_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_ceil_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB4_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB4_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rup +; CHECKZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -265,29 +395,98 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rup ; RV64IF-NEXT: .LBB5_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI5_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI5_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB5_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB5_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI5_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI5_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB5_9 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB5_10 +; RV32IZFINX-NEXT: .LBB5_4: +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB5_11 +; RV32IZFINX-NEXT: .LBB5_5: +; RV32IZFINX-NEXT: bnez a3, .LBB5_12 +; RV32IZFINX-NEXT: .LBB5_6: +; RV32IZFINX-NEXT: bnez a2, .LBB5_8 +; RV32IZFINX-NEXT: .LBB5_7: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB5_8: +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB5_9: +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB5_4 +; RV32IZFINX-NEXT: .LBB5_10: +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB5_5 +; RV32IZFINX-NEXT: .LBB5_11: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB5_6 +; RV32IZFINX-NEXT: .LBB5_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB5_7 +; RV32IZFINX-NEXT: j .LBB5_8 +; +; RV64IZFINX-LABEL: test_ceil_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB5_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB5_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i64 @llvm.fptosi.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_ceil_ui32(float %x) { -; RV32IF-LABEL: test_ceil_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB6_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV32IF-NEXT: .LBB6_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_ceil_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB6_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rup +; CHECK-NEXT: .LBB6_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_ceil_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB6_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV64IF-NEXT: .LBB6_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_ceil_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB6_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB6_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rup +; CHECKZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -345,29 +544,84 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup ; RV64IF-NEXT: .LBB7_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB7_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB7_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI7_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI7_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB7_7 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: beqz s1, .LBB7_8 +; RV32IZFINX-NEXT: .LBB7_4: +; RV32IZFINX-NEXT: bnez a4, .LBB7_6 +; RV32IZFINX-NEXT: .LBB7_5: +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB7_6: +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB7_7: +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB7_4 +; RV32IZFINX-NEXT: .LBB7_8: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB7_5 +; RV32IZFINX-NEXT: j .LBB7_6 +; +; RV64IZFINX-LABEL: test_ceil_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB7_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB7_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = call i64 @llvm.fptoui.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_trunc_si32(float %x) { -; RV32IF-LABEL: test_trunc_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB8_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: .LBB8_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_trunc_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB8_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: .LBB8_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_trunc_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB8_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: .LBB8_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_trunc_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB8_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB8_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rtz +; CHECKZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -438,29 +692,98 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: .LBB9_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI9_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI9_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB9_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB9_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI9_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI9_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB9_9 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB9_10 +; RV32IZFINX-NEXT: .LBB9_4: +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB9_11 +; RV32IZFINX-NEXT: .LBB9_5: +; RV32IZFINX-NEXT: bnez a3, .LBB9_12 +; RV32IZFINX-NEXT: .LBB9_6: +; RV32IZFINX-NEXT: bnez a2, .LBB9_8 +; RV32IZFINX-NEXT: .LBB9_7: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB9_8: +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB9_9: +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB9_4 +; RV32IZFINX-NEXT: .LBB9_10: +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB9_5 +; RV32IZFINX-NEXT: .LBB9_11: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB9_6 +; RV32IZFINX-NEXT: .LBB9_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB9_7 +; RV32IZFINX-NEXT: j .LBB9_8 +; +; RV64IZFINX-LABEL: test_trunc_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB9_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB9_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i64 @llvm.fptosi.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_trunc_ui32(float %x) { -; RV32IF-LABEL: test_trunc_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB10_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: .LBB10_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_trunc_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: .LBB10_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_trunc_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB10_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: .LBB10_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_trunc_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB10_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB10_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -518,29 +841,84 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: .LBB11_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB11_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB11_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI11_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI11_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB11_7 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: beqz s1, .LBB11_8 +; RV32IZFINX-NEXT: .LBB11_4: +; RV32IZFINX-NEXT: bnez a4, .LBB11_6 +; RV32IZFINX-NEXT: .LBB11_5: +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB11_6: +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB11_7: +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB11_4 +; RV32IZFINX-NEXT: .LBB11_8: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB11_5 +; RV32IZFINX-NEXT: j .LBB11_6 +; +; RV64IZFINX-LABEL: test_trunc_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB11_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB11_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = call i64 @llvm.fptoui.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_round_si32(float %x) { -; RV32IF-LABEL: test_round_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB12_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV32IF-NEXT: .LBB12_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_round_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB12_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rmm +; CHECK-NEXT: .LBB12_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_round_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB12_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV64IF-NEXT: .LBB12_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_round_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB12_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB12_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rmm +; CHECKZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -611,29 +989,98 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: .LBB13_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI13_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI13_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB13_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB13_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI13_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI13_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB13_9 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB13_10 +; RV32IZFINX-NEXT: .LBB13_4: +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB13_11 +; RV32IZFINX-NEXT: .LBB13_5: +; RV32IZFINX-NEXT: bnez a3, .LBB13_12 +; RV32IZFINX-NEXT: .LBB13_6: +; RV32IZFINX-NEXT: bnez a2, .LBB13_8 +; RV32IZFINX-NEXT: .LBB13_7: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB13_8: +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB13_9: +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB13_4 +; RV32IZFINX-NEXT: .LBB13_10: +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB13_5 +; RV32IZFINX-NEXT: .LBB13_11: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB13_6 +; RV32IZFINX-NEXT: .LBB13_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB13_7 +; RV32IZFINX-NEXT: j .LBB13_8 +; +; RV64IZFINX-LABEL: test_round_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB13_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB13_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i64 @llvm.fptosi.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_round_ui32(float %x) { -; RV32IF-LABEL: test_round_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB14_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV32IF-NEXT: .LBB14_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_round_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB14_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rmm +; CHECK-NEXT: .LBB14_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_round_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB14_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV64IF-NEXT: .LBB14_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_round_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB14_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB14_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rmm +; CHECKZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -691,29 +1138,84 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm ; RV64IF-NEXT: .LBB15_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB15_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB15_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI15_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI15_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB15_7 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: beqz s1, .LBB15_8 +; RV32IZFINX-NEXT: .LBB15_4: +; RV32IZFINX-NEXT: bnez a4, .LBB15_6 +; RV32IZFINX-NEXT: .LBB15_5: +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB15_6: +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB15_7: +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB15_4 +; RV32IZFINX-NEXT: .LBB15_8: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB15_5 +; RV32IZFINX-NEXT: j .LBB15_6 +; +; RV64IZFINX-LABEL: test_round_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB15_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB15_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = call i64 @llvm.fptoui.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_roundeven_si32(float %x) { -; RV32IF-LABEL: test_roundeven_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB16_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rne -; RV32IF-NEXT: .LBB16_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_roundeven_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB16_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.w.s a0, fa0, rne +; CHECK-NEXT: .LBB16_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_roundeven_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB16_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rne -; RV64IF-NEXT: .LBB16_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_roundeven_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB16_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB16_2: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rne +; CHECKZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i32 @llvm.fptosi.sat.i32.f32(float %a) ret i32 %b @@ -784,29 +1286,98 @@ ; RV64IF-NEXT: fcvt.l.s a0, fa0, rne ; RV64IF-NEXT: .LBB17_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI17_0)(a1) +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, a1, a0 +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: mv a2, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB17_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a2, 0 +; RV32IZFINX-NEXT: .LBB17_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI17_1) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI17_1)(a0) +; RV32IZFINX-NEXT: flt.s a3, a0, s0 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a3, .LBB17_9 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: beqz a2, .LBB17_10 +; RV32IZFINX-NEXT: .LBB17_4: +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: beqz s1, .LBB17_11 +; RV32IZFINX-NEXT: .LBB17_5: +; RV32IZFINX-NEXT: bnez a3, .LBB17_12 +; RV32IZFINX-NEXT: .LBB17_6: +; RV32IZFINX-NEXT: bnez a2, .LBB17_8 +; RV32IZFINX-NEXT: .LBB17_7: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: .LBB17_8: +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB17_9: +; RV32IZFINX-NEXT: mv a0, a2 +; RV32IZFINX-NEXT: feq.s a2, s0, s0 +; RV32IZFINX-NEXT: bnez a2, .LBB17_4 +; RV32IZFINX-NEXT: .LBB17_10: +; RV32IZFINX-NEXT: li a0, 0 +; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: bnez s1, .LBB17_5 +; RV32IZFINX-NEXT: .LBB17_11: +; RV32IZFINX-NEXT: lui a1, 524288 +; RV32IZFINX-NEXT: beqz a3, .LBB17_6 +; RV32IZFINX-NEXT: .LBB17_12: +; RV32IZFINX-NEXT: addi a1, a4, -1 +; RV32IZFINX-NEXT: beqz a2, .LBB17_7 +; RV32IZFINX-NEXT: j .LBB17_8 +; +; RV64IZFINX-LABEL: test_roundeven_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB17_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB17_2: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i64 @llvm.fptosi.sat.i64.f32(float %a) ret i64 %b } define signext i32 @test_roundeven_ui32(float %x) { -; RV32IF-LABEL: test_roundeven_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa0 -; RV32IF-NEXT: beqz a0, .LBB18_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV32IF-NEXT: .LBB18_2: -; RV32IF-NEXT: ret +; CHECK-LABEL: test_roundeven_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: feq.s a0, fa0, fa0 +; CHECK-NEXT: beqz a0, .LBB18_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rne +; CHECK-NEXT: .LBB18_2: +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_roundeven_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa0 -; RV64IF-NEXT: beqz a0, .LBB18_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV64IF-NEXT: .LBB18_2: -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_roundeven_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: feq.s a1, a0, a0 +; CHECKZFINX-NEXT: bnez a1, .LBB18_2 +; CHECKZFINX-NEXT: # %bb.1: +; CHECKZFINX-NEXT: li a0, 0 +; CHECKZFINX-NEXT: ret +; CHECKZFINX-NEXT: .LBB18_2: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rne +; CHECKZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i32 @llvm.fptoui.sat.i32.f32(float %a) ret i32 %b @@ -864,6 +1435,59 @@ ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne ; RV64IF-NEXT: .LBB19_2: ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s s1, zero, a0 +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: mv a3, a0 +; RV32IZFINX-NEXT: bnez s1, .LBB19_2 +; RV32IZFINX-NEXT: # %bb.1: +; RV32IZFINX-NEXT: li a3, 0 +; RV32IZFINX-NEXT: .LBB19_2: +; RV32IZFINX-NEXT: lui a0, %hi(.LCPI19_0) +; RV32IZFINX-NEXT: lw a0, %lo(.LCPI19_0)(a0) +; RV32IZFINX-NEXT: flt.s a4, a0, s0 +; RV32IZFINX-NEXT: li a2, -1 +; RV32IZFINX-NEXT: li a0, -1 +; RV32IZFINX-NEXT: beqz a4, .LBB19_7 +; RV32IZFINX-NEXT: # %bb.3: +; RV32IZFINX-NEXT: beqz s1, .LBB19_8 +; RV32IZFINX-NEXT: .LBB19_4: +; RV32IZFINX-NEXT: bnez a4, .LBB19_6 +; RV32IZFINX-NEXT: .LBB19_5: +; RV32IZFINX-NEXT: mv a2, a1 +; RV32IZFINX-NEXT: .LBB19_6: +; RV32IZFINX-NEXT: mv a1, a2 +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; RV32IZFINX-NEXT: .LBB19_7: +; RV32IZFINX-NEXT: mv a0, a3 +; RV32IZFINX-NEXT: bnez s1, .LBB19_4 +; RV32IZFINX-NEXT: .LBB19_8: +; RV32IZFINX-NEXT: li a1, 0 +; RV32IZFINX-NEXT: beqz a4, .LBB19_5 +; RV32IZFINX-NEXT: j .LBB19_6 +; +; RV64IZFINX-LABEL: test_roundeven_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: feq.s a1, a0, a0 +; RV64IZFINX-NEXT: bnez a1, .LBB19_2 +; RV64IZFINX-NEXT: # %bb.1: +; RV64IZFINX-NEXT: li a0, 0 +; RV64IZFINX-NEXT: ret +; RV64IZFINX-NEXT: .LBB19_2: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = call i64 @llvm.fptoui.sat.i64.f32(float %a) ret i64 %b diff --git a/llvm/test/CodeGen/RISCV/float-round-conv.ll b/llvm/test/CodeGen/RISCV/float-round-conv.ll --- a/llvm/test/CodeGen/RISCV/float-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv.ll @@ -1,8 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKZFINX,RV32IZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKZFINX,RV64IZFINX %s define signext i8 @test_floor_si8(float %x) { ; RV32IF-LABEL: test_floor_si8: @@ -14,6 +18,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_si8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rdn +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_si8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptosi float %a to i8 ret i8 %b @@ -29,21 +43,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_si16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rdn +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_si16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptosi float %a to i16 ret i16 %b } define signext i32 @test_floor_si32(float %x) { -; RV32IF-LABEL: test_floor_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV32IF-NEXT: ret +; CHECK-LABEL: test_floor_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rdn +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_floor_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_floor_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rdn +; CHECKZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptosi float %a to i32 ret i32 %b @@ -66,6 +90,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptosi float %a to i64 ret i64 %b @@ -81,6 +122,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_ui8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rdn +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_ui8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptoui float %a to i8 ret i8 %b @@ -96,21 +147,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_ui16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rdn +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_ui16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptoui float %a to i16 ret i16 %b } define signext i32 @test_floor_ui32(float %x) { -; RV32IF-LABEL: test_floor_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV32IF-NEXT: ret +; CHECK-LABEL: test_floor_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rdn +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_floor_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_floor_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rdn +; CHECKZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptoui float %a to i32 ret i32 %b @@ -133,6 +194,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_floor_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call floorf@plt +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_floor_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rdn +; RV64IZFINX-NEXT: ret %a = call float @llvm.floor.f32(float %x) %b = fptoui float %a to i64 ret i64 %b @@ -148,6 +226,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_si8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rup +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_si8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptosi float %a to i8 ret i8 %b @@ -163,21 +251,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_si16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rup +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_si16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptosi float %a to i16 ret i16 %b } define signext i32 @test_ceil_si32(float %x) { -; RV32IF-LABEL: test_ceil_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rup -; RV32IF-NEXT: ret +; CHECK-LABEL: test_ceil_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rup +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_ceil_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rup -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_ceil_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rup +; CHECKZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptosi float %a to i32 ret i32 %b @@ -200,6 +298,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptosi float %a to i64 ret i64 %b @@ -215,6 +330,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_ui8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rup +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_ui8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptoui float %a to i8 ret i8 %b @@ -230,21 +355,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_ui16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rup +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_ui16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptoui float %a to i16 ret i16 %b } define signext i32 @test_ceil_ui32(float %x) { -; RV32IF-LABEL: test_ceil_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV32IF-NEXT: ret +; CHECK-LABEL: test_ceil_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rup +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_ceil_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_ceil_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rup +; CHECKZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptoui float %a to i32 ret i32 %b @@ -267,6 +402,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_ceil_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call ceilf@plt +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_ceil_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rup +; RV64IZFINX-NEXT: ret %a = call float @llvm.ceil.f32(float %x) %b = fptoui float %a to i64 ret i64 %b @@ -282,6 +434,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_si8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_si8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptosi float %a to i8 ret i8 %b @@ -297,21 +459,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_si16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_si16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptosi float %a to i16 ret i16 %b } define signext i32 @test_trunc_si32(float %x) { -; RV32IF-LABEL: test_trunc_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: test_trunc_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_trunc_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_trunc_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rtz +; CHECKZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptosi float %a to i32 ret i32 %b @@ -334,6 +506,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptosi float %a to i64 ret i64 %b @@ -349,6 +538,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_ui8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_ui8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptoui float %a to i8 ret i8 %b @@ -364,21 +563,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_ui16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_ui16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptoui float %a to i16 ret i16 %b } define signext i32 @test_trunc_ui32(float %x) { -; RV32IF-LABEL: test_trunc_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV32IF-NEXT: ret +; CHECK-LABEL: test_trunc_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rtz +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_trunc_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_trunc_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptoui float %a to i32 ret i32 %b @@ -401,6 +610,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_trunc_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call truncf@plt +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_trunc_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz +; RV64IZFINX-NEXT: ret %a = call float @llvm.trunc.f32(float %x) %b = fptoui float %a to i64 ret i64 %b @@ -416,6 +642,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_si8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_si8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptosi float %a to i8 ret i8 %b @@ -431,21 +667,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_si16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_si16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptosi float %a to i16 ret i16 %b } define signext i32 @test_round_si32(float %x) { -; RV32IF-LABEL: test_round_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV32IF-NEXT: ret +; CHECK-LABEL: test_round_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rmm +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_round_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_round_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rmm +; CHECKZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptosi float %a to i32 ret i32 %b @@ -468,6 +714,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptosi float %a to i64 ret i64 %b @@ -483,6 +746,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_ui8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_ui8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptoui float %a to i8 ret i8 %b @@ -498,21 +771,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_ui16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rmm +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_ui16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptoui float %a to i16 ret i16 %b } define signext i32 @test_round_ui32(float %x) { -; RV32IF-LABEL: test_round_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV32IF-NEXT: ret +; CHECK-LABEL: test_round_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rmm +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_round_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_round_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rmm +; CHECKZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptoui float %a to i32 ret i32 %b @@ -535,6 +818,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_round_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call roundf@plt +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_round_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rmm +; RV64IZFINX-NEXT: ret %a = call float @llvm.round.f32(float %x) %b = fptoui float %a to i64 ret i64 %b @@ -550,6 +850,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_si8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rne +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_si8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptosi float %a to i8 ret i8 %b @@ -565,21 +875,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_si16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rne +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_si16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptosi float %a to i16 ret i16 %b } define signext i32 @test_roundeven_si32(float %x) { -; RV32IF-LABEL: test_roundeven_si32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.w.s a0, fa0, rne -; RV32IF-NEXT: ret +; CHECK-LABEL: test_roundeven_si32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.w.s a0, fa0, rne +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_roundeven_si32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.w.s a0, fa0, rne -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_roundeven_si32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.w.s a0, a0, rne +; CHECKZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptosi float %a to i32 ret i32 %b @@ -602,6 +922,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.l.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_si64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: call __fixsfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_si64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptosi float %a to i64 ret i64 %b @@ -617,6 +954,16 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_ui8: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rne +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_ui8: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptoui float %a to i8 ret i8 %b @@ -632,21 +979,31 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_ui16: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rne +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_ui16: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptoui float %a to i16 ret i16 %b } define signext i32 @test_roundeven_ui32(float %x) { -; RV32IF-LABEL: test_roundeven_ui32: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV32IF-NEXT: ret +; CHECK-LABEL: test_roundeven_ui32: +; CHECK: # %bb.0: +; CHECK-NEXT: fcvt.wu.s a0, fa0, rne +; CHECK-NEXT: ret ; -; RV64IF-LABEL: test_roundeven_ui32: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne -; RV64IF-NEXT: ret +; CHECKZFINX-LABEL: test_roundeven_ui32: +; CHECKZFINX: # %bb.0: +; CHECKZFINX-NEXT: fcvt.wu.s a0, a0, rne +; CHECKZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptoui float %a to i32 ret i32 %b @@ -669,6 +1026,23 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne ; RV64IF-NEXT: ret +; +; RV32IZFINX-LABEL: test_roundeven_ui64: +; RV32IZFINX: # %bb.0: +; RV32IZFINX-NEXT: addi sp, sp, -16 +; RV32IZFINX-NEXT: .cfi_def_cfa_offset 16 +; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFINX-NEXT: .cfi_offset ra, -4 +; RV32IZFINX-NEXT: call roundevenf@plt +; RV32IZFINX-NEXT: call __fixunssfdi@plt +; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFINX-NEXT: addi sp, sp, 16 +; RV32IZFINX-NEXT: ret +; +; RV64IZFINX-LABEL: test_roundeven_ui64: +; RV64IZFINX: # %bb.0: +; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rne +; RV64IZFINX-NEXT: ret %a = call float @llvm.roundeven.f32(float %x) %b = fptoui float %a to i64 ret i64 %b diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll @@ -1,370 +1,374 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s +; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s +; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX %s define float @select_fcmp_false(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_false: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_false: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_false: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_false: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: ret %1 = fcmp false float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_oeq(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: bnez a0, .LBB1_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB1_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_oeq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB1_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB1_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: bnez a0, .LBB1_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB1_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_oeq: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: feq.s a2, a0, a1 +; CHECKIZFINX-NEXT: bnez a2, .LBB1_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB1_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp oeq float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ogt(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ogt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: bnez a0, .LBB2_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB2_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ogt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa1, fa0 +; CHECKIF-NEXT: bnez a0, .LBB2_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB2_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ogt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: bnez a0, .LBB2_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB2_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ogt: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a1, a0 +; CHECKIZFINX-NEXT: bnez a2, .LBB2_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB2_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ogt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_oge(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_oge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: bnez a0, .LBB3_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB3_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_oge: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa1, fa0 +; CHECKIF-NEXT: bnez a0, .LBB3_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB3_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_oge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: bnez a0, .LBB3_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB3_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_oge: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: fle.s a2, a1, a0 +; CHECKIZFINX-NEXT: bnez a2, .LBB3_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB3_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp oge float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_olt(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_olt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: bnez a0, .LBB4_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB4_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_olt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB4_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB4_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_olt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: bnez a0, .LBB4_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB4_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_olt: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a0, a1 +; CHECKIZFINX-NEXT: bnez a2, .LBB4_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB4_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp olt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ole(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ole: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: bnez a0, .LBB5_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB5_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ole: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa0, fa1 +; CHECKIF-NEXT: bnez a0, .LBB5_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB5_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ole: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: bnez a0, .LBB5_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB5_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ole: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: fle.s a2, a0, a1 +; CHECKIZFINX-NEXT: bnez a2, .LBB5_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB5_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ole float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_one(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_one: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: bnez a0, .LBB6_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB6_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_one: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: flt.s a1, fa1, fa0 +; CHECKIF-NEXT: or a0, a1, a0 +; CHECKIF-NEXT: bnez a0, .LBB6_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB6_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_one: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: bnez a0, .LBB6_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB6_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_one: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a0, a1 +; CHECKIZFINX-NEXT: flt.s a3, a1, a0 +; CHECKIZFINX-NEXT: or a2, a3, a2 +; CHECKIZFINX-NEXT: bnez a2, .LBB6_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB6_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp one float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ord(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ord: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: bnez a0, .LBB7_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB7_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ord: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa1, fa1 +; CHECKIF-NEXT: feq.s a1, fa0, fa0 +; CHECKIF-NEXT: and a0, a1, a0 +; CHECKIF-NEXT: bnez a0, .LBB7_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB7_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ord: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: bnez a0, .LBB7_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB7_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ord: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: feq.s a2, a1, a1 +; CHECKIZFINX-NEXT: feq.s a3, a0, a0 +; CHECKIZFINX-NEXT: and a2, a3, a2 +; CHECKIZFINX-NEXT: bnez a2, .LBB7_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB7_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ord float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ueq(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ueq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: flt.s a1, fa1, fa0 -; RV32IF-NEXT: or a0, a1, a0 -; RV32IF-NEXT: beqz a0, .LBB8_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB8_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ueq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: flt.s a1, fa1, fa0 +; CHECKIF-NEXT: or a0, a1, a0 +; CHECKIF-NEXT: beqz a0, .LBB8_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB8_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ueq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: flt.s a1, fa1, fa0 -; RV64IF-NEXT: or a0, a1, a0 -; RV64IF-NEXT: beqz a0, .LBB8_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB8_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ueq: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a0, a1 +; CHECKIZFINX-NEXT: flt.s a3, a1, a0 +; CHECKIZFINX-NEXT: or a2, a3, a2 +; CHECKIZFINX-NEXT: beqz a2, .LBB8_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB8_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ueq float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ugt(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ugt: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: beqz a0, .LBB9_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB9_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ugt: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB9_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB9_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ugt: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: beqz a0, .LBB9_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB9_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ugt: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: fle.s a2, a0, a1 +; CHECKIZFINX-NEXT: beqz a2, .LBB9_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB9_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ugt float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_uge(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_uge: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: beqz a0, .LBB10_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB10_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_uge: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB10_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB10_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_uge: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: beqz a0, .LBB10_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB10_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_uge: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a0, a1 +; CHECKIZFINX-NEXT: beqz a2, .LBB10_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB10_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp uge float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ult(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ult: -; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: beqz a0, .LBB11_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB11_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ult: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: fle.s a0, fa1, fa0 +; CHECKIF-NEXT: beqz a0, .LBB11_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB11_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ult: -; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: beqz a0, .LBB11_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB11_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ult: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: fle.s a2, a1, a0 +; CHECKIZFINX-NEXT: beqz a2, .LBB11_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB11_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ult float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_ule(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_ule: -; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: beqz a0, .LBB12_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB12_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_ule: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: flt.s a0, fa1, fa0 +; CHECKIF-NEXT: beqz a0, .LBB12_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB12_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_ule: -; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: beqz a0, .LBB12_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB12_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_ule: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: flt.s a2, a1, a0 +; CHECKIZFINX-NEXT: beqz a2, .LBB12_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB12_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp ule float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_une(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_une: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa0, fa1 -; RV32IF-NEXT: beqz a0, .LBB13_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB13_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_une: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa0, fa1 +; CHECKIF-NEXT: beqz a0, .LBB13_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB13_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_une: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa0, fa1 -; RV64IF-NEXT: beqz a0, .LBB13_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB13_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_une: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: feq.s a2, a0, a1 +; CHECKIZFINX-NEXT: beqz a2, .LBB13_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB13_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp une float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_uno(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_uno: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a0, fa1, fa1 -; RV32IF-NEXT: feq.s a1, fa0, fa0 -; RV32IF-NEXT: and a0, a1, a0 -; RV32IF-NEXT: beqz a0, .LBB14_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: fmv.s fa0, fa1 -; RV32IF-NEXT: .LBB14_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_uno: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a0, fa1, fa1 +; CHECKIF-NEXT: feq.s a1, fa0, fa0 +; CHECKIF-NEXT: and a0, a1, a0 +; CHECKIF-NEXT: beqz a0, .LBB14_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: fmv.s fa0, fa1 +; CHECKIF-NEXT: .LBB14_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_uno: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a0, fa1, fa1 -; RV64IF-NEXT: feq.s a1, fa0, fa0 -; RV64IF-NEXT: and a0, a1, a0 -; RV64IF-NEXT: beqz a0, .LBB14_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: fmv.s fa0, fa1 -; RV64IF-NEXT: .LBB14_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_uno: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: feq.s a2, a1, a1 +; CHECKIZFINX-NEXT: feq.s a3, a0, a0 +; CHECKIZFINX-NEXT: and a2, a3, a2 +; CHECKIZFINX-NEXT: beqz a2, .LBB14_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a1 +; CHECKIZFINX-NEXT: .LBB14_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp uno float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 } define float @select_fcmp_true(float %a, float %b) nounwind { -; RV32IF-LABEL: select_fcmp_true: -; RV32IF: # %bb.0: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: select_fcmp_true: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: select_fcmp_true: -; RV64IF: # %bb.0: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: select_fcmp_true: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: ret %1 = fcmp true float %a, %b %2 = select i1 %1, float %a, float %b ret float %2 @@ -372,23 +376,24 @@ ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type. define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind { -; RV32IF-LABEL: i32_select_fcmp_oeq: -; RV32IF: # %bb.0: -; RV32IF-NEXT: feq.s a2, fa0, fa1 -; RV32IF-NEXT: bnez a2, .LBB16_2 -; RV32IF-NEXT: # %bb.1: -; RV32IF-NEXT: mv a0, a1 -; RV32IF-NEXT: .LBB16_2: -; RV32IF-NEXT: ret +; CHECKIF-LABEL: i32_select_fcmp_oeq: +; CHECKIF: # %bb.0: +; CHECKIF-NEXT: feq.s a2, fa0, fa1 +; CHECKIF-NEXT: bnez a2, .LBB16_2 +; CHECKIF-NEXT: # %bb.1: +; CHECKIF-NEXT: mv a0, a1 +; CHECKIF-NEXT: .LBB16_2: +; CHECKIF-NEXT: ret ; -; RV64IF-LABEL: i32_select_fcmp_oeq: -; RV64IF: # %bb.0: -; RV64IF-NEXT: feq.s a2, fa0, fa1 -; RV64IF-NEXT: bnez a2, .LBB16_2 -; RV64IF-NEXT: # %bb.1: -; RV64IF-NEXT: mv a0, a1 -; RV64IF-NEXT: .LBB16_2: -; RV64IF-NEXT: ret +; CHECKIZFINX-LABEL: i32_select_fcmp_oeq: +; CHECKIZFINX: # %bb.0: +; CHECKIZFINX-NEXT: feq.s a1, a0, a1 +; CHECKIZFINX-NEXT: mv a0, a2 +; CHECKIZFINX-NEXT: bnez a1, .LBB16_2 +; CHECKIZFINX-NEXT: # %bb.1: +; CHECKIZFINX-NEXT: mv a0, a3 +; CHECKIZFINX-NEXT: .LBB16_2: +; CHECKIZFINX-NEXT: ret %1 = fcmp oeq float %a, %b %2 = select i1 %1, i32 %c, i32 %d ret i32 %2