diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -95,6 +95,9 @@
   // compiler has free to select either one.
   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
+
+  HasFPRndModeOpShift = UsesMaskPolicyShift + 1,
+  HasFPRndModeOpMask = 1 << HasFPRndModeOpShift,
 };
 
 // Match with the definitions in RISCVInstrFormats.td
@@ -168,6 +171,9 @@
   return TSFlags & UsesMaskPolicyMask;
 }
 
+static inline bool hasFPRndModeOp(uint64_t TSFlags) {
+  return TSFlags & HasFPRndModeOpMask;
+}
 // RISC-V Specific Machine Operand Flags
 enum {
   MO_None = 0,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9529,6 +9529,26 @@
 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
                                                         SDNode *Node) const {
   // Add FRM dependency to any instructions with dynamic rounding mode.
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  if (RISCVII::hasFPRndModeOp(TSFlags)) {
+    bool HasPolicy = RISCVII::hasVecPolicyOp(TSFlags);
+    bool HasVL = RISCVII::hasVLOp(TSFlags);
+    bool HasSEW = RISCVII::hasSEWOp(TSFlags);
+    (void)HasVL;
+    (void)HasSEW;
+    assert(HasVL && HasSEW);
+    unsigned Idx = MI.getNumExplicitOperands() - HasPolicy - 3;
+    const MachineOperand &RndModeOp = MI.getOperand(Idx);
+    if (RndModeOp.getImm() != RISCVFPRndMode::DYN)
+      return;
+    // If the instruction already reads FRM, don't add another read.
+    if (MI.readsRegister(RISCV::FRM))
+      return;
+    MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false,
+                                            /*isImp*/ true));
+    return;
+  }
+
   unsigned Opc = MI.getOpcode();
   auto Idx = RISCV::getNamedOperandIdx(Opc, RISCV::OpName::frm);
   if (Idx < 0)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -200,6 +200,9 @@
 
   bit UsesMaskPolicy = 0;
   let TSFlags{18} = UsesMaskPolicy;
+
+  bit HasFPRndModeOp = 0;
+  let TSFlags{19} =  HasFPRndModeOp;
 }
 
 // Pseudo instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -42,6 +42,8 @@
 defvar TAIL_UNDISTURBED = 0;
 defvar TAIL_AGNOSTIC = 1;
 
+defvar FPRM_DYN = 7;
+
 //===----------------------------------------------------------------------===//
 // Utilities.
 //===----------------------------------------------------------------------===//
@@ -2678,15 +2680,38 @@
   }
 }
 
+multiclass VPseudoConversionRM<VReg RetClass,
+                               VReg Op1Class,
+                               LMULInfo MInfo,
+                               string Constraint = ""> {
+  let VLMul = MInfo.value, HasFPRndModeOp = 1 in {
+    let InOperandList = (ins Op1Class:$rs2, ixlenimm:$rm, AVL:$vl, ixlenimm:$sew) in
+      def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
+    let InOperandList = (ins RetClass:$merge, Op1Class:$rs2, ixlenimm:$rm, AVL:$vl, ixlenimm:$sew) in
+      def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
+    let InOperandList = (ins GetVRegNoV0<RetClass>.R:$merge, Op1Class:$rs2,
+                             VMaskOp:$vm, ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy) in
+    def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
+                                                      Constraint>,
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+  }
+}
+
 multiclass VPseudoVCVTI_V {
   foreach m = MxListF in
     defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
               Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>;
 }
 
-multiclass VPseudoVCVTF_V {
+multiclass VPseudoVCVTI_RM_V {
   foreach m = MxListF in
-    defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
+    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
+              Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>;
+}
+
+multiclass VPseudoVCVTF_RM_V {
+  foreach m = MxListF in
+    defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
               Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>;
 }
 
@@ -2703,17 +2728,24 @@
               Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>;
 }
 
-multiclass VPseudoVWCVTF_V {
+multiclass VPseudoVWCVTI_RM_V {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListFW in
+    defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
+              Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>;
+}
+
+multiclass VPseudoVWCVTF_RM_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListW in
-    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
+    defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
               Sched<[WriteVFWCvtIToFV, ReadVFWCvtIToFV, ReadVMask]>;
 }
 
-multiclass VPseudoVWCVTD_V {
+multiclass VPseudoVWCVTD_RM_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in
-    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
+    defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
               Sched<[WriteVFWCvtFToFV, ReadVFWCvtFToFV, ReadVMask]>;
 }
 
@@ -2724,10 +2756,17 @@
               Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>;
 }
 
-multiclass VPseudoVNCVTF_W {
+multiclass VPseudoVNCVTI_RM_W {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListW in
+    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
+              Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>;
+}
+
+multiclass VPseudoVNCVTF_RM_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in
-    defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
+    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
               Sched<[WriteVFNCvtIToFV, ReadVFNCvtIToFV, ReadVMask]>;
 }
 
@@ -2738,6 +2777,13 @@
               Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>;
 }
 
+multiclass VPseudoVNCVTD_RM_W {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListFW in
+    defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
+              Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>;
+}
+
 multiclass VPseudoUSSegLoad<bit isFF> {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
@@ -2881,6 +2927,22 @@
                    (op2_type op2_reg_class:$rs2),
                    GPR:$vl, sew)>;
 
+class VPatUnaryNoMaskFRM<string intrinsic_name,
+                         string inst,
+                         string kind,
+                         ValueType result_type,
+                         ValueType op2_type,
+                         int sew,
+                         LMULInfo vlmul,
+                         VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                   (result_type undef),
+                   (op2_type op2_reg_class:$rs2),
+                   VLOpFrag)),
+      (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
+                   (op2_type op2_reg_class:$rs2),
+                   FPRM_DYN, GPR:$vl, sew)>;
+
 class VPatUnaryNoMaskTU<string intrinsic_name,
                         string inst,
                         string kind,
@@ -2919,6 +2981,24 @@
                    (op2_type op2_reg_class:$rs2),
                    (mask_type V0), GPR:$vl, sew)>;
 
+class VPatUnaryNoMaskTUFRM<string intrinsic_name,
+                           string inst,
+                           string kind,
+                           ValueType result_type,
+                           ValueType op2_type,
+                           int sew,
+                           LMULInfo vlmul,
+                           VReg result_reg_class,
+                           VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   VLOpFrag)),
+      (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_TU")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   FPRM_DYN, GPR:$vl, sew)>;
+
 class VPatUnaryMaskTA<string intrinsic_name,
                       string inst,
                       string kind,
@@ -2939,6 +3019,26 @@
                    (op2_type op2_reg_class:$rs2),
                    (mask_type V0), GPR:$vl, sew, (XLenVT timm:$policy))>;
 
+class VPatUnaryMaskTAFRM<string intrinsic_name,
+                         string inst,
+                         string kind,
+                         ValueType result_type,
+                         ValueType op2_type,
+                         ValueType mask_type,
+                         int sew,
+                         LMULInfo vlmul,
+                         VReg result_reg_class,
+                         VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0),
+                   VLOpFrag, (XLenVT timm:$policy))),
+      (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0), FPRM_DYN, GPR:$vl, sew, (XLenVT timm:$policy))>;
+
 class VPatMaskUnaryNoMask<string intrinsic_name,
                           string inst,
                           MTypeInfo mti> :
@@ -3535,6 +3635,25 @@
                         mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
 }
 
+multiclass VPatConversionTAFRM<string intrinsic,
+                              string inst,
+                              string kind,
+                              ValueType result_type,
+                              ValueType op1_type,
+                              ValueType mask_type,
+                              int sew,
+                              LMULInfo vlmul,
+                              VReg result_reg_class,
+                              VReg op1_reg_class>
+{
+  def : VPatUnaryNoMaskFRM<intrinsic, inst, kind, result_type, op1_type,
+                           sew, vlmul, op1_reg_class>;
+  def : VPatUnaryNoMaskTUFRM<intrinsic, inst, kind, result_type, op1_type,
+                             sew, vlmul, result_reg_class, op1_reg_class>;
+  def : VPatUnaryMaskTAFRM<intrinsic, inst, kind, result_type, op1_type,
+                           mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
+}
+
 multiclass VPatBinaryV_VV<string intrinsic, string instruction,
                           list<VTypeInfo> vtilist> {
   foreach vti = vtilist in
@@ -4106,16 +4225,29 @@
   }
 }
 
-multiclass VPatConversionVF_VI<string intrinsic,
-                               string instruction>
+multiclass VPatConversionFRM_VI_VF<string intrinsic,
+                                   string instruction>
 {
   foreach fvti = AllFloatVectors in
   {
     defvar ivti = GetIntVTypeInfo<fvti>.Vti;
 
-    defm : VPatConversionTA<intrinsic, instruction, "V",
-                            fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
-                            ivti.LMul, fvti.RegClass, ivti.RegClass>;
+    defm : VPatConversionTAFRM<intrinsic, instruction, "V",
+                               ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
+                               fvti.LMul, ivti.RegClass, fvti.RegClass>;
+  }
+}
+
+multiclass VPatConversionFRM_VF_VI<string intrinsic,
+                                   string instruction>
+{
+  foreach fvti = AllFloatVectors in
+  {
+    defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+
+    defm : VPatConversionTAFRM<intrinsic, instruction, "V",
+                               fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
+                               ivti.LMul, fvti.RegClass, ivti.RegClass>;
   }
 }
 
@@ -4131,27 +4263,39 @@
   }
 }
 
-multiclass VPatConversionWF_VI<string intrinsic, string instruction> {
+multiclass VPatConversionFRM_WI_VF<string intrinsic, string instruction> {
+  foreach fvtiToFWti = AllWidenableFloatVectors in
+  {
+    defvar fvti = fvtiToFWti.Vti;
+    defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
+
+    defm : VPatConversionTAFRM<intrinsic, instruction, "V",
+                               iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
+                               fvti.LMul, iwti.RegClass, fvti.RegClass>;
+  }
+}
+
+multiclass VPatConversionFRM_WF_VI<string intrinsic, string instruction> {
   foreach vtiToWti = AllWidenableIntToFloatVectors in
   {
     defvar vti = vtiToWti.Vti;
     defvar fwti = vtiToWti.Wti;
 
-    defm : VPatConversionTA<intrinsic, instruction, "V",
-                            fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
-                            vti.LMul, fwti.RegClass, vti.RegClass>;
+    defm : VPatConversionTAFRM<intrinsic, instruction, "V",
+                               fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
+                               vti.LMul, fwti.RegClass, vti.RegClass>;
   }
 }
 
-multiclass VPatConversionWF_VF <string intrinsic, string instruction> {
+multiclass VPatConversionFRM_WF_VF <string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableFloatVectors in
   {
     defvar fvti = fvtiToFWti.Vti;
     defvar fwti = fvtiToFWti.Wti;
 
-    defm : VPatConversionTA<intrinsic, instruction, "V",
-                            fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
-                            fvti.LMul, fwti.RegClass, fvti.RegClass>;
+    defm : VPatConversionTAFRM<intrinsic, instruction, "V",
+                               fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
+                               fvti.LMul, fwti.RegClass, fvti.RegClass>;
   }
 }
 
@@ -4167,15 +4311,27 @@
   }
 }
 
-multiclass VPatConversionVF_WI <string intrinsic, string instruction> {
+multiclass VPatConversionFRM_VI_WF <string intrinsic, string instruction> {
+  foreach vtiToWti = AllWidenableIntToFloatVectors in
+  {
+    defvar vti = vtiToWti.Vti;
+    defvar fwti = vtiToWti.Wti;
+
+    defm : VPatConversionTAFRM<intrinsic, instruction, "W",
+                               vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
+                               vti.LMul, vti.RegClass, fwti.RegClass>;
+  }
+}
+
+multiclass VPatConversionFRM_VF_WI <string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableFloatVectors in
   {
     defvar fvti = fvtiToFWti.Vti;
     defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
 
-    defm : VPatConversionTA<intrinsic, instruction, "W",
-                            fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
-                            fvti.LMul, fvti.RegClass, iwti.RegClass>;
+    defm : VPatConversionTAFRM<intrinsic, instruction, "W",
+                               fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
+                               fvti.LMul, fvti.RegClass, iwti.RegClass>;
   }
 }
 
@@ -4191,6 +4347,18 @@
   }
 }
 
+multiclass VPatConversionFRM_VF_WF <string intrinsic, string instruction> {
+  foreach fvtiToFWti = AllWidenableFloatVectors in
+  {
+    defvar fvti = fvtiToFWti.Vti;
+    defvar fwti = fvtiToFWti.Wti;
+
+    defm : VPatConversionTAFRM<intrinsic, instruction, "W",
+                               fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
+                               fvti.LMul, fvti.RegClass, fwti.RegClass>;
+  }
+}
+
 multiclass VPatCompare_VI<string intrinsic, string inst,
                           ImmLeaf ImmType> {
   foreach vti = AllIntegerVectors in {
@@ -4706,35 +4874,50 @@
 //===----------------------------------------------------------------------===//
 // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm PseudoVFCVT_XU_F : VPseudoVCVTI_V;
-defm PseudoVFCVT_X_F : VPseudoVCVTI_V;
-defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
-defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
-defm PseudoVFCVT_F_XU : VPseudoVCVTF_V;
-defm PseudoVFCVT_F_X : VPseudoVCVTF_V;
+let mayRaiseFPException = true, hasPostISelHook = 1 in {
+  defm PseudoVFCVT_XU_F : VPseudoVCVTI_RM_V;
+  defm PseudoVFCVT_X_F : VPseudoVCVTI_RM_V;
+  defm PseudoVFCVT_F_XU : VPseudoVCVTF_RM_V;
+  defm PseudoVFCVT_F_X : VPseudoVCVTF_RM_V;
+}
+
+let mayRaiseFPException = true in {
+  defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
+  defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
+}
 
 //===----------------------------------------------------------------------===//
 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm PseudoVFWCVT_XU_F     : VPseudoVWCVTI_V;
-defm PseudoVFWCVT_X_F      : VPseudoVWCVTI_V;
-defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
-defm PseudoVFWCVT_RTZ_X_F  : VPseudoVWCVTI_V;
-defm PseudoVFWCVT_F_XU     : VPseudoVWCVTF_V;
-defm PseudoVFWCVT_F_X      : VPseudoVWCVTF_V;
-defm PseudoVFWCVT_F_F      : VPseudoVWCVTD_V;
+let mayRaiseFPException = true, hasPostISelHook = 1 in {
+  defm PseudoVFWCVT_XU_F     : VPseudoVWCVTI_RM_V;
+  defm PseudoVFWCVT_X_F      : VPseudoVWCVTI_RM_V;
+  defm PseudoVFWCVT_F_XU     : VPseudoVWCVTF_RM_V;
+  defm PseudoVFWCVT_F_X      : VPseudoVWCVTF_RM_V;
+  defm PseudoVFWCVT_F_F      : VPseudoVWCVTD_RM_V;
+}
+
+let mayRaiseFPException = true in {
+  defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
+  defm PseudoVFWCVT_RTZ_X_F  : VPseudoVWCVTI_V;
+}
 
 //===----------------------------------------------------------------------===//
 // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm PseudoVFNCVT_XU_F     : VPseudoVNCVTI_W;
-defm PseudoVFNCVT_X_F      : VPseudoVNCVTI_W;
-defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
-defm PseudoVFNCVT_RTZ_X_F  : VPseudoVNCVTI_W;
-defm PseudoVFNCVT_F_XU     : VPseudoVNCVTF_W;
-defm PseudoVFNCVT_F_X      : VPseudoVNCVTF_W;
-defm PseudoVFNCVT_F_F      : VPseudoVNCVTD_W;
-defm PseudoVFNCVT_ROD_F_F  : VPseudoVNCVTD_W;
+let mayRaiseFPException = true, hasPostISelHook = 1 in {
+  defm PseudoVFNCVT_XU_F     : VPseudoVNCVTI_RM_W;
+  defm PseudoVFNCVT_X_F      : VPseudoVNCVTI_RM_W;
+  defm PseudoVFNCVT_F_XU     : VPseudoVNCVTF_RM_W;
+  defm PseudoVFNCVT_F_X      : VPseudoVNCVTF_RM_W;
+  defm PseudoVFNCVT_F_F      : VPseudoVNCVTD_RM_W;
+}
+
+let mayRaiseFPException = true in {
+  defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
+  defm PseudoVFNCVT_RTZ_X_F  : VPseudoVNCVTI_W;
+  defm PseudoVFNCVT_ROD_F_F  : VPseudoVNCVTD_W;
+}
 } // Predicates = [HasVInstructionsAnyF]
 
 let Predicates = [HasVInstructions] in {
@@ -5296,34 +5479,34 @@
 //===----------------------------------------------------------------------===//
 // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm : VPatConversionVI_VF<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">;
+defm : VPatConversionFRM_VI_VF<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">;
 defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;
-defm : VPatConversionVI_VF<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">;
+defm : VPatConversionFRM_VI_VF<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">;
 defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_x_f_v", "PseudoVFCVT_RTZ_X_F">;
-defm : VPatConversionVF_VI<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X">;
-defm : VPatConversionVF_VI<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU">;
+defm : VPatConversionFRM_VF_VI<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X">;
+defm : VPatConversionFRM_VF_VI<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU">;
 
 //===----------------------------------------------------------------------===//
 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm : VPatConversionWI_VF<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">;
-defm : VPatConversionWI_VF<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">;
+defm : VPatConversionFRM_WI_VF<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">;
+defm : VPatConversionFRM_WI_VF<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">;
 defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;
 defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_x_f_v", "PseudoVFWCVT_RTZ_X_F">;
-defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU">;
-defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X">;
-defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">;
+defm : VPatConversionFRM_WF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU">;
+defm : VPatConversionFRM_WF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X">;
+defm : VPatConversionFRM_WF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">;
 
 //===----------------------------------------------------------------------===//
 // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
-defm : VPatConversionVI_WF<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;
-defm : VPatConversionVI_WF<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;
+defm : VPatConversionFRM_VI_WF<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;
+defm : VPatConversionFRM_VI_WF<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;
 defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;
 defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
-defm : VPatConversionVF_WI <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
-defm : VPatConversionVF_WI <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
-defm : VPatConversionVF_WF<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
+defm : VPatConversionFRM_VF_WI <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
+defm : VPatConversionFRM_VF_WI <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
+defm : VPatConversionFRM_VF_WF<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
 defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
 } // Predicates = [HasVInstructionsAnyF]
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -286,7 +286,7 @@
     defvar ivti = GetIntVTypeInfo<fvti>.Vti;
     def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
-                  ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
+                  ivti.RegClass:$rs1, FPRM_DYN, fvti.AVL, fvti.Log2SEW)>;
   }
 }
 
@@ -305,7 +305,7 @@
     defvar fwti = vtiToWti.Wti;
     def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
-                  ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>;
+                  ivti.RegClass:$rs1, FPRM_DYN, ivti.AVL, ivti.Log2SEW)>;
   }
 }
 
@@ -325,7 +325,7 @@
     defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
     def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
-                  iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
+                  iwti.RegClass:$rs1, FPRM_DYN, fvti.AVL, fvti.Log2SEW)>;
   }
 }
 
@@ -964,7 +964,7 @@
   defvar fwti = fvtiToFWti.Wti;
   def : Pat<(fwti.Vector (fpextend (fvti.Vector fvti.RegClass:$rs1))),
             (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
-                fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
+                fvti.RegClass:$rs1, FPRM_DYN, fvti.AVL, fvti.Log2SEW)>;
 }
 
 // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -977,7 +977,7 @@
   defvar fwti = fvtiToFWti.Wti;
   def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
             (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
-                fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
+                fwti.RegClass:$rs1, FPRM_DYN, fvti.AVL, fvti.Log2SEW)>;
 }
 } // Predicates = [HasVInstructionsAnyF]
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -627,7 +627,7 @@
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
-                  (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+                  (ivti.Mask V0), FPRM_DYN, GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
@@ -653,7 +653,7 @@
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
                   (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
-                  (ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>;
+                  (ivti.Mask V0), FPRM_DYN, GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
@@ -679,7 +679,7 @@
                                 VLOpFrag)),
               (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
-                  (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+                  (iwti.Mask V0), FPRM_DYN, GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
@@ -1642,7 +1642,7 @@
                                               VLOpFrag)),
               (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK")
                   (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
-                  (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+                  (fvti.Mask V0), FPRM_DYN, GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 
   // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -1658,7 +1658,7 @@
                                              VLOpFrag)),
               (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
-                  (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+                  (fwti.Mask V0), FPRM_DYN, GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
 
     def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1),
                                                (fwti.Mask true_mask),
diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -155,6 +155,8 @@
     --NumOps;
   if (RISCVII::hasVLOp(TSFlags))
     --NumOps;
+  if (RISCVII::hasFPRndModeOp(TSFlags))
+    --NumOps;
   if (RISCVII::hasSEWOp(TSFlags))
     --NumOps;