diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -281,6 +281,11 @@
   if (I->isTerminator() && llvm::any_of(successors(I), HasPhis))
     return false;
 
+  // Make sure there are no potentially eflags clobbering constant
+  // materializations in between.
+  if (llvm::any_of(I->operands(), [](Value *V) { return isa<Constant>(V); }))
+    return false;
+
   CC = TmpCC;
   return true;
 }
diff --git a/llvm/test/CodeGen/X86/pr54369.ll b/llvm/test/CodeGen/X86/pr54369.ll
--- a/llvm/test/CodeGen/X86/pr54369.ll
+++ b/llvm/test/CodeGen/X86/pr54369.ll
@@ -1,16 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-- -O0 < %s | FileCheck %s
 
-; FIXME: This is currently miscompiled due to an eflags clobber.
 define i64 @adder(i64 %lhs, i64 %rhs) {
 ; CHECK-LABEL: adder:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    seto %dl
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $rax killed $eax
 ; CHECK-NEXT:    movl $148, %ecx
-; CHECK-NEXT:    cmovoq %rcx, %rax
+; CHECK-NEXT:    testb $1, %dl
+; CHECK-NEXT:    cmovneq %rcx, %rax
 ; CHECK-NEXT:    retq
 	%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
 	%errorbit = extractvalue { i64, i1 } %res, 1
@@ -24,11 +24,12 @@
 ; CHECK-LABEL: adder_constexpr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    seto %dl
 ; CHECK-NEXT:    movq a@GOTPCREL(%rip), %rax
 ; CHECK-NEXT:    addq $5, %rax
 ; CHECK-NEXT:    movl $148, %ecx
-; CHECK-NEXT:    cmovoq %rcx, %rax
+; CHECK-NEXT:    testb $1, %dl
+; CHECK-NEXT:    cmovneq %rcx, %rax
 ; CHECK-NEXT:    retq
   %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
   %errorbit = extractvalue { i64, i1 } %res, 1