Index: llvm/test/CodeGen/Lanai/isel_debug_single.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/Lanai/isel_debug_single.ll @@ -0,0 +1,97 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=lanai -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s + +; Test Selection DAG debug output generation + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +define i64 @i64_test(i64 %i) nounwind readnone { +; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test: +; CHECK: SelectionDAG has 22 nodes: +; CHECK-NEXT: t0: ch = EntryToken +; CHECK-NEXT: t5: i32,ch = LDW_RI TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0> +; CHECK-NEXT: t29: i32 = OR_I_LO t7, TargetConstant:i32<4> +; CHECK-NEXT: t22: i32,ch = LDW_RI t29, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t24: i32 = ADD_R t5, t22, TargetConstant:i32<0> +; CHECK-NEXT: t3: i32,ch = LDW_RI TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t19: i32,ch = LDW_RI TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t25: i32 = ADD_R t3, t19, TargetConstant:i32<0> +; CHECK-NEXT: t30: i32,glue = SFSUB_F_RR t24, t5 +; CHECK-NEXT: t31: i32 = SCC TargetConstant:i32<4>, t30:1 +; CHECK-NEXT: t28: i32 = ADD_R t25, t31, TargetConstant:i32<0> +; CHECK-NEXT: t15: ch,glue = CopyToReg t0, Register:i32 $rv, t28 +; CHECK-NEXT: t17: ch,glue = CopyToReg t15, Register:i32 $r9, t24, t15:1 +; CHECK-NEXT: t18: ch = RET Register:i32 $rv, Register:i32 $r9, t17, t17:1 +; CHECK-EMPTY: + %loc = alloca i64 + %j = load i64, i64 * %loc + %r = add i64 %i, %j + ret i64 %r +} + +define i64 @i32_test(i32 %i) nounwind readnone { +; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test: +; CHECK: SelectionDAG has 14 nodes: +; CHECK-NEXT: t0: ch = EntryToken +; CHECK-NEXT: t21: i32,ch = CopyFromReg t0, Register:i32 $r0 +; CHECK-NEXT: t13: ch,glue = CopyToReg t0, Register:i32 $rv, t21 +; CHECK-NEXT: t3: i32,ch = LDW_RI TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t6: i32,ch = LDW_RI TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t7: i32 = ADD_R t3, t6, TargetConstant:i32<0> +; CHECK-NEXT: t15: ch,glue = CopyToReg t13, Register:i32 $r9, t7, t13:1 +; CHECK-NEXT: t16: ch = RET Register:i32 $rv, Register:i32 $r9, t15, t15:1 +; CHECK-EMPTY: + %loc = alloca i32 + %j = load i32, i32 * %loc + %r = add i32 %i, %j + %ext = zext i32 %r to i64 + ret i64 %ext +} + +define i64 @i16_test(i16 %i) nounwind readnone { +; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test: +; CHECK: SelectionDAG has 19 nodes: +; CHECK-NEXT: t0: ch = EntryToken +; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0 +; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33 +; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0> +; CHECK-NEXT: t21: i32 = OR_I_LO t1, TargetConstant:i32<2> +; CHECK-NEXT: t23: i32,ch = LDHz_RI t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t22: i32,ch = LDHz_RI TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t24: i32 = ADD_R t23, t22, TargetConstant:i32<0> +; CHECK-NEXT: t27: i32 = AND_I_HI t24, TargetConstant:i32<0> +; CHECK-NEXT: t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1 +; CHECK-NEXT: t28: i32 = TargetConstant<65535> +; CHECK-NEXT: t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1 +; CHECK-EMPTY: + %loc = alloca i16 + %j = load i16, i16 * %loc + %r = add i16 %i, %j + %ext = zext i16 %r to i64 + ret i64 %ext +} + +define i64 @i8_test(i8 %i) nounwind readnone { +; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test: +; CHECK: SelectionDAG has 20 nodes: +; CHECK-NEXT: t0: ch = EntryToken +; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0 +; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33 +; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0> +; CHECK-NEXT: t21: i32 = OR_I_LO t1, TargetConstant:i32<3> +; CHECK-NEXT: t23: i32,ch = LDBz_RI t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t22: i32,ch = LDBz_RI TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 +; CHECK-NEXT: t24: i32 = ADD_R t23, t22, TargetConstant:i32<0> +; CHECK-NEXT: t26: i32 = SLI TargetConstant:i32<255> +; CHECK-NEXT: t27: i32 = AND_R t24, t26, TargetConstant:i32<0> +; CHECK-NEXT: t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1 +; CHECK-NEXT: t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1 +; CHECK-EMPTY: + %loc = alloca i8 + %j = load i8, i8 * %loc + %r = add i8 %i, %j + %ext = zext i8 %r to i64 + ret i64 %ext +} Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s define i64 @i64_test(i64 %i) nounwind readnone { -; CHECK-LABEL: i64_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test: ; CHECK: SelectionDAG has 9 nodes: ; CHECK-NEXT: t0: ch = EntryToken ; CHECK-NEXT: t11: ch,glue = CopyToReg t0, Register:i32 $vgpr0, IMPLICIT_DEF:i32 @@ -17,7 +17,7 @@ } define i64 @i32_test(i32 %i) nounwind readnone { -; CHECK-LABEL: i32_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test: ; CHECK: SelectionDAG has 8 nodes: ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0> ; CHECK-NEXT: t0: ch = EntryToken @@ -33,7 +33,7 @@ } define i64 @i16_test(i16 %i) nounwind readnone { -; CHECK-LABEL: i16_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test: ; CHECK: SelectionDAG has 8 nodes: ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0> ; CHECK-NEXT: t0: ch = EntryToken @@ -49,7 +49,7 @@ } define i64 @i8_test(i8 %i) nounwind readnone { -; CHECK-LABEL: i8_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test: ; CHECK: SelectionDAG has 8 nodes: ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0> ; CHECK-NEXT: t0: ch = EntryToken Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=lanai -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s define i64 @i64_test(i64 %i) nounwind readnone { -; CHECK-LABEL: i64_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i64_test: ; CHECK: SelectionDAG has 22 nodes: ; CHECK-NEXT: t0: ch = EntryToken ; CHECK-NEXT: t5: i32,ch = LDW_RI TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0 @@ -27,7 +27,7 @@ } define i64 @i32_test(i32 %i) nounwind readnone { -; CHECK-LABEL: i32_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i32_test: ; CHECK: SelectionDAG has 14 nodes: ; CHECK-NEXT: t0: ch = EntryToken ; CHECK-NEXT: t21: i32,ch = CopyFromReg t0, Register:i32 $r0 @@ -46,7 +46,7 @@ } define i64 @i16_test(i16 %i) nounwind readnone { -; CHECK-LABEL: i16_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i16_test: ; CHECK: SelectionDAG has 19 nodes: ; CHECK-NEXT: t0: ch = EntryToken ; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0 @@ -69,7 +69,7 @@ } define i64 @i8_test(i8 %i) nounwind readnone { -; CHECK-LABEL: i8_test: +; CHECK-LABEL: Selected selection DAG:{{.*}}i8_test: ; CHECK: SelectionDAG has 20 nodes: ; CHECK-NEXT: t0: ch = EntryToken ; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0 Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=x86_64-windows -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=WIN define i64 @i64_test(i64 %i) nounwind readnone { -; PIC-LABEL: i64_test: +; PIC-LABEL: Selected selection DAG:{{.*}}i64_test: ; PIC: SelectionDAG has 12 nodes: ; PIC-NEXT: t0: ch = EntryToken ; PIC-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0 @@ -12,7 +12,7 @@ ; PIC-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1 ; PIC-EMPTY: ; -; WIN-LABEL: i64_test: +; WIN-LABEL: Selected selection DAG:{{.*}}i64_test: ; WIN: SelectionDAG has 12 nodes: ; WIN-NEXT: t0: ch = EntryToken ; WIN-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0 @@ -27,7 +27,7 @@ } define i64 @i32_test(i32 %i) nounwind readnone { -; PIC-LABEL: i32_test: +; PIC-LABEL: Selected selection DAG:{{.*}}i32_test: ; PIC: SelectionDAG has 15 nodes: ; PIC-NEXT: t0: ch = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 @@ -37,7 +37,7 @@ ; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; PIC-EMPTY: ; -; WIN-LABEL: i32_test: +; WIN-LABEL: Selected selection DAG:{{.*}}i32_test: ; WIN: SelectionDAG has 15 nodes: ; WIN-NEXT: t0: ch = EntryToken ; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 @@ -54,7 +54,7 @@ } define i64 @i16_test(i16 %i) nounwind readnone { -; PIC-LABEL: i16_test: +; PIC-LABEL: Selected selection DAG:{{.*}}i16_test: ; PIC: SelectionDAG has 18 nodes: ; PIC-NEXT: t0: ch = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 @@ -66,7 +66,7 @@ ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; -; WIN-LABEL: i16_test: +; WIN-LABEL: Selected selection DAG:{{.*}}i16_test: ; WIN: SelectionDAG has 16 nodes: ; WIN-NEXT: t0: ch = EntryToken ; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0 @@ -84,7 +84,7 @@ } define i64 @i8_test(i8 %i) nounwind readnone { -; PIC-LABEL: i8_test: +; PIC-LABEL: Selected selection DAG:{{.*}}i8_test: ; PIC: SelectionDAG has 18 nodes: ; PIC-NEXT: t0: ch = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 @@ -96,7 +96,7 @@ ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; -; WIN-LABEL: i8_test: +; WIN-LABEL: Selected selection DAG:{{.*}}i8_test: ; WIN: SelectionDAG has 16 nodes: ; WIN-NEXT: t0: ch = EntryToken ; WIN-NEXT: t2: i8,ch = CopyFromReg t0, Register:i8 %0 Index: llvm/utils/UpdateTestChecks/isel.py =================================================================== --- llvm/utils/UpdateTestChecks/isel.py +++ llvm/utils/UpdateTestChecks/isel.py @@ -50,7 +50,7 @@ def add_checks(output_lines, comment_marker, prefix_list, func_dict, func_name, is_filtered): # Label format is based on iSel string. - check_label_format = '{} %s-LABEL: %s%s:'.format(comment_marker) + check_label_format = '{} %s-LABEL: Selected selection DAG:{{{{.*}}}}%s%s:'.format(comment_marker) global_vars_seen_dict = {} common.add_checks(output_lines, comment_marker, prefix_list, func_dict, func_name, check_label_format, True, False,