Index: include/llvm/IR/IntrinsicsX86.td
===================================================================
--- include/llvm/IR/IntrinsicsX86.td
+++ include/llvm/IR/IntrinsicsX86.td
@@ -3545,6 +3545,24 @@
 }
 
 //===----------------------------------------------------------------------===//
+// SMAP
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_clac : GCCBuiltin<"__builtin_ia32_clac">,
+              Intrinsic<[], [], []>;
+  def int_x86_stac : GCCBuiltin<"__builtin_ia32_stac">,
+              Intrinsic<[], [], []>;
+}
+
+//===----------------------------------------------------------------------===//
+// LGDT, SGDT
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_lgdt : GCCBuiltin<"__builtin_ia32_lgdt">,
+              Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_x86_sgdt : GCCBuiltin<"__builtin_ia32_sgdt">,
+              Intrinsic<[], [llvm_ptr_ty], []>;
+}
+
+//===----------------------------------------------------------------------===//
 // Half float conversion
 
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
Index: lib/Target/X86/X86InstrSystem.td
===================================================================
--- lib/Target/X86/X86InstrSystem.td
+++ lib/Target/X86/X86InstrSystem.td
@@ -391,18 +391,20 @@
 // Descriptor-table support instructions
 
 let SchedRW = [WriteSystem] in {
-def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
+def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
               "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
-def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
-              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
-def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
-              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
-def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
+def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
+              "sgdt{l}\t$dst", [(int_x86_sgdt addr:$dst)], IIC_SGDT>, OpSize32, TB,
+              Requires <[Not64BitMode]>;
+def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
+              "sgdt{q}\t$dst", [(int_x86_sgdt addr:$dst)], IIC_SGDT>, TB,
+              Requires <[In64BitMode]>;
+def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
               "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
-def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
-              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
-def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
-              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
+def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
+              "sidt{l}\t$dst", [], IIC_SIDT>, OpSize32, TB, Requires <[Not64BitMode]>;
+def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
+              "sidt{q}\t$dst", [], IIC_SIDT>, TB, Requires <[In64BitMode]>;
 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
                 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
@@ -420,9 +422,11 @@
 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
               "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
-              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
+              "lgdt{l}\t$src", [(int_x86_lgdt addr:$src)], IIC_LGDT>, OpSize32, TB,
+              Requires<[Not64BitMode]>;
 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
-              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
+              "lgdt{q}\t$src", [(int_x86_lgdt addr:$src)], IIC_LGDT>, TB,
+              Requires<[In64BitMode]>;
 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
               "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
@@ -576,8 +580,8 @@
 //===----------------------------------------------------------------------===//
 // SMAP Instruction
 let Defs = [EFLAGS] in {
-  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
-  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
+  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [(int_x86_clac)]>, TB;
+  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [(int_x86_stac)]>, TB;
 }
 
 //===----------------------------------------------------------------------===//
Index: test/CodeGen/X86/system-intrinsics.ll
===================================================================
--- test/CodeGen/X86/system-intrinsics.ll
+++ test/CodeGen/X86/system-intrinsics.ll
@@ -15,3 +15,35 @@
   ret void;
 }
 declare void @llvm.x86.fxrstor(i8*)
+
+define void @test_clac() {
+; CHECK-LABEL: test_clac
+; CHECK: clac
+  call void @llvm.x86.clac()
+  ret void;
+}
+declare void @llvm.x86.clac()
+
+define void @test_stac() {
+; CHECK-LABEL: test_stac
+; CHECK: stac
+  call void @llvm.x86.stac()
+  ret void;
+}
+declare void @llvm.x86.stac()
+
+define void @test_lgdt(i8* %ptr) {
+; CHECK-LABEL: test_lgdt
+; CHECK: lgdtl
+  call void @llvm.x86.lgdt(i8* %ptr)
+  ret void;
+}
+declare void @llvm.x86.lgdt(i8*)
+
+define void @test_sgdt(i8* %ptr) {
+; CHECK-LABEL: test_sgdt
+; CHECK: sgdtl
+  call void @llvm.x86.sgdt(i8* %ptr)
+  ret void;
+}
+declare void @llvm.x86.sgdt(i8*)