Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -972,10 +972,11 @@
 def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 
-// setge X, 0 is canonicalized to setgt X, -1.
-// FIXME: This can be generalized to more immediates by using SLTI.
-def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
+// setge X, Imm is canonicalized to setgt X, (Imm - 1).
+def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
 
 def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
Index: llvm/test/CodeGen/RISCV/rv32zbt.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zbt.ll
+++ llvm/test/CodeGen/RISCV/rv32zbt.ll
@@ -336,8 +336,7 @@
 ; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sgt i32 %b, 2046
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -358,8 +357,7 @@
 ; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sgt i32 %b, -2049
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -398,8 +396,7 @@
 ; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, 2047
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -420,8 +417,7 @@
 ; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, -2048
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -519,8 +515,7 @@
 ; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ugt i32 %b, 2046
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -541,8 +536,7 @@
 ; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ugt i32 %b, 4294965247
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -581,8 +575,7 @@
 ; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i32 %b, 2047
   %cond = select i1 %tobool, i32 %a, i32 %c
@@ -603,8 +596,7 @@
 ; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i32 %b, 4294965248
   %cond = select i1 %tobool, i32 %a, i32 %c
Index: llvm/test/CodeGen/RISCV/rv64zbt.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbt.ll
+++ llvm/test/CodeGen/RISCV/rv64zbt.ll
@@ -404,8 +404,7 @@
 ; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sgt i64 %b, 2046
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -426,8 +425,7 @@
 ; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sgt i64 %b, -2049
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -466,8 +464,7 @@
 ; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, 2047
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -488,8 +485,7 @@
 ; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, -2048
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -587,8 +583,7 @@
 ; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp ugt i64 %b, 2046
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -609,8 +604,7 @@
 ; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp ugt i64 %b, 18446744073709549567
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -649,8 +643,7 @@
 ; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp uge i64 %b, 2047
   %cond = select i1 %tobool, i64 %a, i64 %c
@@ -671,8 +664,7 @@
 ; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp uge i64 %b, 18446744073709549568
   %cond = select i1 %tobool, i64 %a, i64 %c
Index: llvm/test/CodeGen/RISCV/select-cc.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-cc.ll
+++ llvm/test/CodeGen/RISCV/select-cc.ll
@@ -62,11 +62,23 @@
 ; RV32I-NEXT:  # %bb.21:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_22:
-; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    lw a3, 0(a1)
 ; RV32I-NEXT:    bgez a2, .LBB0_24
 ; RV32I-NEXT:  # %bb.23:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_24:
+; RV32I-NEXT:    lw a3, 0(a1)
+; RV32I-NEXT:    li a4, 1024
+; RV32I-NEXT:    blt a4, a3, .LBB0_26
+; RV32I-NEXT:  # %bb.25:
+; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:  .LBB0_26:
+; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    li a3, 2046
+; RV32I-NEXT:    bltu a3, a2, .LBB0_28
+; RV32I-NEXT:  # %bb.27:
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:  .LBB0_28:
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: foo:
@@ -98,14 +110,20 @@
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a3, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a0, a2
+; RV32IBT-NEXT:    lw a5, 0(a1)
 ; RV32IBT-NEXT:    cmov a0, a4, a0, a2
+; RV32IBT-NEXT:    slt a2, a3, a0
+; RV32IBT-NEXT:    cmov a0, a2, a3, a0
+; RV32IBT-NEXT:    slti a2, a5, 1
+; RV32IBT-NEXT:    lw a3, 0(a1)
+; RV32IBT-NEXT:    cmov a0, a2, a0, a5
 ; RV32IBT-NEXT:    lw a2, 0(a1)
-; RV32IBT-NEXT:    slt a4, a3, a0
+; RV32IBT-NEXT:    slti a4, a5, 0
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a1, 0(a1)
-; RV32IBT-NEXT:    slti a3, a2, 1
-; RV32IBT-NEXT:    cmov a0, a3, a0, a2
-; RV32IBT-NEXT:    sltz a2, a2
+; RV32IBT-NEXT:    slti a3, a2, 1025
+; RV32IBT-NEXT:    cmov a0, a3, a2, a0
+; RV32IBT-NEXT:    sltiu a2, a5, 2047
 ; RV32IBT-NEXT:    cmov a0, a2, a1, a0
 ; RV32IBT-NEXT:    ret
   %val1 = load volatile i32, i32* %b
@@ -156,7 +174,14 @@
   %tst12 = icmp sgt i32 %val21, -1
   %val24 = select i1 %tst12, i32 %val22, i32 %val23
 
-  ret i32 %val24
+  %val25 = load volatile i32, i32* %b
+  %tst13 = icmp sgt i32 %val25, 1024
+  %val26 = select i1 %tst13, i32 %val24, i32 %val25
+
+  %val27 = load volatile i32, i32* %b
+  %tst14 = icmp ugt i32 %val21, 2046
+  %val28 = select i1 %tst14, i32 %val26, i32 %val27
+  ret i32 %val28
 }
 
 ; Test that we can ComputeNumSignBits across basic blocks when the live out is