diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -3997,7 +3997,7 @@
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in {
-let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
+let Uses = [EDI], Predicates = [HasAVX] in
 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
            (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
@@ -4010,7 +4010,7 @@
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>,
            VEX, VEX_WIG;
 
-let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
+let Uses = [EDI], Predicates = [UseSSE2] in
 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -516,6 +516,14 @@
            "LEA has segment specified!");
     break;
 
+  case X86::MASKMOVDQU:
+  case X86::VMASKMOVDQU: {
+    const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
+    // A address-size prefix is need in X32
+    if (Subtarget.is64Bit())
+      OutMI.setFlags(X86::IP_HAS_AD_SIZE);
+    break;
+  }
   case X86::MULX32Hrr:
   case X86::MULX32Hrm:
   case X86::MULX64Hrr:
diff --git a/llvm/test/CodeGen/X86/maskmovdqu.ll b/llvm/test/CodeGen/X86/maskmovdqu.ll
--- a/llvm/test/CodeGen/X86/maskmovdqu.ll
+++ b/llvm/test/CodeGen/X86/maskmovdqu.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686--    -mattr=+sse2,-avx | FileCheck %s --check-prefix=i686_SSE2
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_64_SSE2
+; RUN: llc < %s -mtriple=x86_64--gnux32 -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_x32_SSE2
 ; RUN: llc < %s -mtriple=i686--    -mattr=+avx | FileCheck %s --check-prefix=i686_AVX
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefix=x86_64_AVX
+; RUN: llc < %s -mtriple=x86_64--gnux32 -mattr=+avx | FileCheck %s --check-prefix=x86_x32_AVX
 ; rdar://6573467
 
 define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
@@ -20,6 +22,13 @@
 ; x86_64_SSE2-NEXT:    maskmovdqu %xmm1, %xmm0
 ; x86_64_SSE2-NEXT:    retq
 ;
+; x86_x32_SSE2-LABEL: test:
+; x86_x32_SSE2:       # %bb.0: # %entry
+; x86_x32_SSE2-NEXT:    movq %rsi, %rdi
+; x86_x32_SSE2-NEXT:    # kill: def $edi killed $edi killed $rdi
+; x86_x32_SSE2-NEXT:    addr32 maskmovdqu %xmm1, %xmm0
+; x86_x32_SSE2-NEXT:    retq
+;
 ; i686_AVX-LABEL: test:
 ; i686_AVX:       # %bb.0: # %entry
 ; i686_AVX-NEXT:    pushl %edi
@@ -33,6 +42,12 @@
 ; x86_64_AVX-NEXT:    movq %rsi, %rdi
 ; x86_64_AVX-NEXT:    vmaskmovdqu %xmm1, %xmm0
 ; x86_64_AVX-NEXT:    retq
+; x86_x32_AVX-LABEL: test:
+; x86_x32_AVX:       # %bb.0: # %entry
+; x86_x32_AVX-NEXT:    movq %rsi, %rdi
+; x86_x32_AVX-NEXT:    # kill: def $edi killed $edi killed $rdi
+; x86_x32_AVX-NEXT:    addr32 vmaskmovdqu %xmm1, %xmm0
+; x86_x32_AVX-NEXT:    retq
 entry:
 	tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
 	ret void
diff --git a/llvm/test/MC/X86/maskmovdqu.s b/llvm/test/MC/X86/maskmovdqu.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/X86/maskmovdqu.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple i386-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple i386-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// CHECK-NOT: addr32
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+maskmovdqu %xmm1, %xmm0
+
+// CHECK-NOT: addr32
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+vmaskmovdqu %xmm1, %xmm0
diff --git a/llvm/test/MC/X86/maskmovdqu64.s b/llvm/test/MC/X86/maskmovdqu64.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/X86/maskmovdqu64.s
@@ -0,0 +1,27 @@
+// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// CHECK-NOT: addr32
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+maskmovdqu %xmm1, %xmm0
+
+// CHECK-NOT: addr32
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+vmaskmovdqu %xmm1, %xmm0
+
+// CHECK:  addr32
+// ENCODING:  encoding: [0x67]
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+addr32 maskmovdqu %xmm1, %xmm0
+
+// CHECK:  addr32
+// ENCODING:  encoding: [0x67]
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+addr32 vmaskmovdqu %xmm1, %xmm0