Index: llvm/test/CodeGen/SystemZ/call-zos-01.ll =================================================================== --- llvm/test/CodeGen/SystemZ/call-zos-01.ll +++ llvm/test/CodeGen/SystemZ/call-zos-01.ll @@ -126,9 +126,9 @@ ; CHECK: larl [[GENREG:[0-9]+]], @{{CPI[0-9]+_[0-9]+}} ; CHECK-NEXT: ld 1, 0([[GENREG]]) ; CHECK-NEXT: ld 3, 8([[GENREG]]) -; CHECK: lxr 5, 0 -; CHECK: lxr 0, 1 -; CHECK: lxr 4, 5 +; CHECK: lxr [[TEMPFPR:[0-9]+]], 0 +; CHECK: lxr 0, 1 +; CHECK: lxr 4, [[TEMPFPR]] define i64 @call_floats0(fp128 %arg0, double %arg1) { entry: %ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1) Index: llvm/test/CodeGen/SystemZ/call-zos-vararg.ll =================================================================== --- llvm/test/CodeGen/SystemZ/call-zos-vararg.ll +++ llvm/test/CodeGen/SystemZ/call-zos-vararg.ll @@ -13,13 +13,13 @@ } ; CHECK-LABEL: call_vararg_double1 -; CHECK: llihf 0, 1074118262 -; CHECK-NEXT: oilf 0, 3367254360 -; CHECK: llihf 3, 1074340036 -; CHECK-NEXT: oilf 3, 2611340116 -; CHECK: lghi 1, 1 -; CHECK: lghi 2, 2 -; CHECK: stg 0, 2200(4) +; CHECK-DAG: llihf 0, 1074118262 +; CHECK-DAG: oilf 0, 3367254360 +; CHECK-DAG: llihf 3, 1074340036 +; CHECK-DAG: oilf 3, 2611340116 +; CHECK-DAG: lghi 1, 1 +; CHECK-DAG: lghi 2, 2 +; CHECK-DAG: stg 0, 2200(4) define i64 @call_vararg_double1() { entry: %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, double 3.141000e+00, double 2.718000e+00) @@ -39,15 +39,15 @@ } ; CHECK-LABEL: call_vararg_double3 -; CHECK: llihf 0, 1072703839 -; CHECK-NEXT: oilf 0, 2861204133 -; CHECK: llihf 1, 1074118262 -; CHECK-NEXT: oilf 1, 3367254360 -; CHECK: llihf 2, 1074340036 -; CHECK-NEXT: oilf 2, 2611340116 -; CHECK: llihf 3, 1073127358 -; CHECK-NEXT: oilf 3, 1992864825 -; CHECK: stg 0, 2200(4) +; CHECK-DAG: llihf 0, 1072703839 +; CHECK-DAG: oilf 0, 2861204133 +; CHECK-DAG: llihf 1, 1074118262 +; CHECK-DAG: oilf 1, 3367254360 +; CHECK-DAG: llihf 2, 1074340036 +; CHECK-DAG: oilf 2, 2611340116 +; CHECK-DAG: llihf 3, 1073127358 +; CHECK-DAG: oilf 3, 1992864825 +; CHECK-DAG: stg 0, 2200(4) define i64 @call_vararg_double3() { entry: %retval = call i64 (...) @pass_vararg3(double 2.718000e+00, double 3.141000e+00, double 1.414000e+00, double 1.010101e+00) @@ -66,11 +66,11 @@ ; CHECK: larl 1, @CPI5_0 ; CHECK-NEXT: ld 0, 0(1) ; CHECK-NEXT: ld 2, 8(1) -; CHECK-NEXT: lgdr 3, 0 -; CHECK: lghi 1, 1 -; CHECK: lghi 2, 2 -; CHECK: std 0, 2192(4) -; CHECK-NEXT: std 2, 2200(4) +; CHECK-DAG: lgdr 3, 0 +; CHECK-DAG: lghi 1, 1 +; CHECK-DAG: lghi 2, 2 +; CHECK-DAG: std 0, 2192(4) +; CHECK-DAG: std 2, 2200(4) define i64 @call_vararg_long_double0() { entry: %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, fp128 0xLE0FC1518450562CD4000921FB5444261) @@ -124,50 +124,50 @@ ; ARCH12-LABEL: call_vec_vararg_test1 ; ARCH12: larl 1, @CPI10_0 ; ARCH12: vl 0, 0(1), 3 -; ARCH12: vlgvg 3, 24, 0 -; ARCH12: vrepg 2, 0, 1 -; ARCH12: vst 25, 2208(4), 3 -; ARCH12: vst 24, 2192(4), 3 +; ARCH12-DAG: vlgvg 3, 24, 0 +; ARCH12-DAG: vrepg 2, 0, 1 +; ARCH12-DAG: vst 25, 2208(4), 3 +; ARCH12-DAG: vst 24, 2192(4), 3 define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) { %retval = call i64(fp128, ...) @pass_vararg1(fp128 0xLE0FC1518450562CD4000921FB5444261, <4 x i32> %v, <2 x i64> %w) ret void } ; ARCH12-LABEL: call_vec_char_vararg_straddle -; ARCH12: vlgvg 3, 24, 0 -; ARCH12: lghi 1, 1 -; ARCH12: lghi 2, 2 -; ARCH12: vst 24, 2192(4), 3 +; ARCH12-DAG: vlgvg 3, 24, 0 +; ARCH12-DAG: vst 24, 2192(4), 3 +; ARCH12-DAG: lghi 1, 1 +; ARCH12-DAG: lghi 2, 2 define void @call_vec_char_vararg_straddle(<16 x i8> %v) { %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <16 x i8> %v) ret void } ; ARCH12-LABEL: call_vec_short_vararg_straddle -; ARCH12: vlgvg 3, 24, 0 -; ARCH12: lghi 1, 1 -; ARCH12: lghi 2, 2 -; ARCH12: vst 24, 2192(4), 3 +; ARCH12-DAG: vlgvg 3, 24, 0 +; ARCH12-DAG: vst 24, 2192(4), 3 +; ARCH12-DAG: lghi 1, 1 +; ARCH12-DAG: lghi 2, 2 define void @call_vec_short_vararg_straddle(<8 x i16> %v) { %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <8 x i16> %v) ret void } ; ARCH12-LABEL: call_vec_int_vararg_straddle -; ARCH12: vlgvg 3, 24, 0 -; ARCH12: lghi 1, 1 -; ARCH12: lghi 2, 2 -; ARCH12: vst 24, 2192(4), 3 +; ARCH12-DAG: vlgvg 3, 24, 0 +; ARCH12-DAG: vst 24, 2192(4), 3 +; ARCH12-DAG: lghi 1, 1 +; ARCH12-DAG: lghi 2, 2 define void @call_vec_int_vararg_straddle(<4 x i32> %v) { %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <4 x i32> %v) ret void } ; ARCH12-LABEL: call_vec_double_vararg_straddle -; ARCH12: vlgvg 3, 24, 0 -; ARCH12: lghi 1, 1 -; ARCH12: lghi 2, 2 -; ARCH12: vst 24, 2192(4), 3 +; ARCH12-DAG: vlgvg 3, 24, 0 +; ARCH12-DAG: vst 24, 2192(4), 3 +; ARCH12-DAG: lghi 1, 1 +; ARCH12-DAG: lghi 2, 2 define void @call_vec_double_vararg_straddle(<2 x double> %v) { %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <2 x double> %v) ret void Index: llvm/test/CodeGen/SystemZ/call-zos-vec.ll =================================================================== --- llvm/test/CodeGen/SystemZ/call-zos-vec.ll +++ llvm/test/CodeGen/SystemZ/call-zos-vec.ll @@ -44,8 +44,8 @@ ; Verify that 3 is not allocated for passing integral types ; if 24 and %f0 are used. ; CHECK-LABEL: call_vecs1 -; CHECK: vlr 24, 25 -; CHECK: stg 1, 2200(4) +; CHECK-DAG: vlr 24, 25 +; CHECK-DAG: stg 1, 2200(4) define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) { entry: %ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n) Index: llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll =================================================================== --- llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll +++ llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll @@ -298,8 +298,8 @@ ; to force use of agfi before stmg. ; CHECK64: lgr 0, 4 ; CHECK64: agfi 4, -1040192 -; CHECK64: stmg 4, 9, 2048(4) -; CHECK64: lgr 8, 4 +; CHECK64-DAG: stmg 4, 9, 2048(4) +; CHECK64-DAG: lgr 8, 4 ; TODO Will change to basr with ADA introduction. ; CHECK64: brasl 7, @@ALCAXP ; CHECK64-NEXT: bcr 0, 3