diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -990,6 +990,12 @@
   // hasGFX90AInsts is also true.
   bool hasGFX940Insts() const { return GFX940Insts; }
 
+  bool isGFX908Subtarget() const { return HasMAIInsts && !GFX90AInsts; };
+
+  bool isGFX90ASubtarget() const { return GFX90AInsts && !GFX940Insts; };
+
+  bool isGFX940Subtarget() const { return GFX940Insts; };
+
   /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
   /// SGPRs
   unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -551,8 +551,7 @@
                                RegScavenger &RS,
                                Register ImpDefSuperReg = Register(),
                                Register ImpUseSuperReg = Register()) {
-  assert((TII.getSubtarget().hasMAIInsts() &&
-          !TII.getSubtarget().hasGFX90AInsts()) &&
+  assert(TII.getSubtarget().isGFX908Subtarget() &&
          "Expected GFX908 subtarget.");
 
   assert((AMDGPU::SReg_32RegClass.contains(SrcReg) ||
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -697,7 +697,7 @@
 
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
   // VGPR available at all times.
-  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
+  if (ST.isGFX908Subtarget()) {
     reserveRegisterTuples(Reserved, AMDGPU::VGPR32);
   }