diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -37,213 +37,226 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, - unsigned RegMask, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder); -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder); -static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, + const MCDisassembler *Decoder); template static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template -static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder); + const MCDisassembler *Decoder); static bool Check(DecodeStatus &Out, DecodeStatus In) { switch (In) { @@ -400,7 +413,7 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -410,9 +423,9 @@ return Success; } -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 15) return Fail; return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); @@ -420,7 +433,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -432,7 +445,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -444,7 +457,7 @@ static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -456,7 +469,7 @@ static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -466,9 +479,9 @@ return Success; } -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 30) return Fail; @@ -481,7 +494,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -491,10 +504,9 @@ return Success; } -static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 22) return Fail; if (RegNo & 1) @@ -509,7 +521,7 @@ static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -518,10 +530,10 @@ return Success; } -static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 3) return Fail; @@ -534,7 +546,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -546,7 +558,7 @@ static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -558,7 +570,7 @@ static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; @@ -570,7 +582,7 @@ static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return Fail; return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); @@ -578,7 +590,7 @@ static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 7) return Fail; return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); @@ -586,7 +598,7 @@ static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -597,7 +609,7 @@ static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -608,7 +620,7 @@ static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void* Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -617,10 +629,10 @@ return Success; } -static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, - unsigned RegMask, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, + uint64_t Address, + const MCDisassembler *Decoder) { if (RegMask > 0xFF) return Fail; Inst.addOperand(MCOperand::createImm(RegMask)); @@ -641,7 +653,8 @@ template static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned LastReg = (1 << NumBitsForTile) - 1; if (RegNo > LastReg) return Fail; @@ -651,7 +664,8 @@ } static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 15) return Fail; @@ -663,7 +677,7 @@ static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void* Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 7) return Fail; @@ -672,7 +686,8 @@ } static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -682,7 +697,8 @@ } static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -693,7 +709,7 @@ static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -703,7 +719,8 @@ } static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -713,7 +730,8 @@ } static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -724,7 +742,7 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return Fail; unsigned Register = @@ -735,7 +753,7 @@ static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { // scale{5} is asserted as 1 in tblgen. Imm |= 0x20; Inst.addOperand(MCOperand::createImm(64 - Imm)); @@ -744,29 +762,29 @@ static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(64 - Imm)); return Success; } static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { int64_t ImmVal = Imm; - const AArch64Disassembler *Dis = - static_cast(Decoder); // Sign-extend 19-bit immediate. if (ImmVal & (1 << (19 - 1))) ImmVal |= ~((1LL << 19) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, - Inst.getOpcode() != AArch64::LDRXl, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand( + Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 4)) Inst.addOperand(MCOperand::createImm(ImmVal)); return Success; } static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); Inst.addOperand(MCOperand::createImm(Imm & 1)); return Success; @@ -774,7 +792,7 @@ static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(Imm)); // Every system register in the encoding space is valid with the syntax @@ -784,7 +802,7 @@ static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(Imm)); return Success; @@ -792,7 +810,7 @@ static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // This decoder exists to add the dummy Lane operand to the MCInst, which must // be 1 in assembly but has no other real manifestation. unsigned Rd = fieldFromInstruction(Insn, 0, 5); @@ -826,66 +844,74 @@ } static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 64); } static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); } static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 32); } static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); } static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 16); } static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); } static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 8); } static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 64); } static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 32); } static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 16); } static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 8); } -static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rm = fieldFromInstruction(insn, 16, 5); @@ -947,7 +973,7 @@ static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned imm = fieldFromInstruction(insn, 5, 16); unsigned shift = fieldFromInstruction(insn, 21, 2); @@ -978,14 +1004,12 @@ return Success; } -static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned offset = fieldFromInstruction(insn, 10, 12); - const AArch64Disassembler *Dis = - static_cast(Decoder); switch (Inst.getOpcode()) { default: @@ -1034,14 +1058,14 @@ } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) Inst.addOperand(MCOperand::createImm(offset)); return Success; } static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); int64_t offset = fieldFromInstruction(insn, 12, 9); @@ -1237,9 +1261,9 @@ return Success; } -static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rt2 = fieldFromInstruction(insn, 10, 5); @@ -1322,7 +1346,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rt2 = fieldFromInstruction(insn, 10, 5); @@ -1456,7 +1480,7 @@ static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | @@ -1489,7 +1513,7 @@ static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rm = fieldFromInstruction(insn, 16, 5); @@ -1546,7 +1570,7 @@ static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Datasize = fieldFromInstruction(insn, 31, 1); @@ -1577,7 +1601,7 @@ static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; @@ -1616,7 +1640,7 @@ static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; @@ -1633,26 +1657,26 @@ } static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; imm |= fieldFromInstruction(insn, 29, 2); - const AArch64Disassembler *Dis = - static_cast(Decoder); // Sign-extend the 21-bit immediate. if (imm & (1 << (21 - 1))) imm |= ~((1LL << 21) - 1); DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) Inst.addOperand(MCOperand::createImm(imm)); return Success; } static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Imm = fieldFromInstruction(insn, 10, 14); @@ -1661,8 +1685,6 @@ unsigned ShifterVal = (Imm >> 12) & 3; unsigned ImmVal = Imm & 0xFFF; - const AArch64Disassembler *Dis = - static_cast(Decoder); if (ShifterVal != 0 && ShifterVal != 1) return Fail; @@ -1681,7 +1703,7 @@ DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); } - if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) Inst.addOperand(MCOperand::createImm(ImmVal)); Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); return Success; @@ -1689,24 +1711,22 @@ static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { int64_t imm = fieldFromInstruction(insn, 0, 26); - const AArch64Disassembler *Dis = - static_cast(Decoder); // Sign-extend the 26-bit immediate. if (imm & (1 << (26 - 1))) imm |= ~((1LL << 26) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::createImm(imm)); return Success; } -static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, + const MCDisassembler *Decoder) { uint64_t op1 = fieldFromInstruction(insn, 16, 3); uint64_t op2 = fieldFromInstruction(insn, 5, 3); uint64_t crm = fieldFromInstruction(insn, 8, 4); @@ -1726,22 +1746,20 @@ Inst.addOperand(MCOperand::createImm(pstate_field)); Inst.addOperand(MCOperand::createImm(crm)); - const AArch64Disassembler *Dis = - static_cast(Decoder); auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); - if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) + if (PState && + PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) return Success; return Fail; } static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { uint64_t Rt = fieldFromInstruction(insn, 0, 5); uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; bit |= fieldFromInstruction(insn, 19, 5); int64_t dst = fieldFromInstruction(insn, 5, 14); - const AArch64Disassembler *Dis = - static_cast(Decoder); // Sign-extend 14-bit immediate. if (dst & (1 << (14 - 1))) @@ -1752,17 +1770,16 @@ else DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::createImm(bit)); - if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) + if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::createImm(dst)); return Success; } -static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, - unsigned RegClassID, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, + unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder) { // Register number must be even (see CASP instruction) if (RegNo & 0x1) return Fail; @@ -1772,27 +1789,25 @@ return Success; } -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeGPRSeqPairsClassRegisterClass(Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder); } -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, + const MCDisassembler *Decoder) { return DecodeGPRSeqPairsClassRegisterClass(Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder); } -static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Zdn = fieldFromInstruction(insn, 0, 5); unsigned imm = fieldFromInstruction(insn, 5, 13); if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) @@ -1808,7 +1823,7 @@ template static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Imm & ~((1LL << Bits) - 1)) return Fail; @@ -1822,8 +1837,8 @@ // Decode 8-bit signed/unsigned immediate for a given element width. template -static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { +static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { unsigned Val = (uint8_t)Imm; unsigned Shift = (Imm & 0x100) ? 8 : 0; if (ElementWidth == 8 && Shift) @@ -1835,13 +1850,14 @@ // Decode uimm4 ranged from 1-16. static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(Imm + 1)); return Success; } static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { Inst.addOperand(MCOperand::createImm(Imm)); return Success; @@ -1851,7 +1867,7 @@ static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rs = fieldFromInstruction(insn, 16, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); @@ -1876,7 +1892,7 @@ static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rm = fieldFromInstruction(insn, 16, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -73,7 +73,8 @@ } static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); // Our branches take a simm16, but we need two extra bits to account for the @@ -86,8 +87,8 @@ return addOperand(Inst, MCOperand::createImm(Imm)); } -static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { +static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); int64_t Offset; if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. @@ -98,20 +99,19 @@ return addOperand(Inst, MCOperand::createImm(Offset)); } -static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, - uint64_t Addr, const void *Decoder) { +static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeBoolReg(Val)); } -#define DECODE_OPERAND(StaticDecoderName, DecoderName) \ -static DecodeStatus StaticDecoderName(MCInst &Inst, \ - unsigned Imm, \ - uint64_t /*Addr*/, \ - const void *Decoder) { \ - auto DAsm = static_cast(Decoder); \ - return addOperand(Inst, DAsm->DecoderName(Imm)); \ -} +#define DECODE_OPERAND(StaticDecoderName, DecoderName) \ + static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ + uint64_t /*Addr*/, \ + const MCDisassembler *Decoder) { \ + auto DAsm = static_cast(Decoder); \ + return addOperand(Inst, DAsm->DecoderName(Imm)); \ + } #define DECODE_OPERAND_REG(RegClass) \ DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) @@ -150,149 +150,136 @@ DECODE_OPERAND_REG(AV_128) DECODE_OPERAND_REG(AV_512) -static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); } -static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, - unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, + uint64_t Addr, + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); } -static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); } -static DecodeStatus decodeOperand_VS_16(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); } -static DecodeStatus decodeOperand_VS_32(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); } -static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); } -static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); } -static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); } -static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); } -static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); } -static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); } -static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); } -static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); } -static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); } -static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); } static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { const auto *DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); } static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) { + uint64_t Addr, + const MCDisassembler *Decoder) { const auto *DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); } -static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { const auto *DAsm = static_cast(Decoder); return addOperand( Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); } -static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { const auto *DAsm = static_cast(Decoder); return addOperand( Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); @@ -312,10 +299,9 @@ return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; } -static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); if (!DAsm->isGFX90A()) { Imm &= 511; @@ -347,42 +333,37 @@ return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); } -static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, - unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW32, Decoder); } -static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, - unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW64, Decoder); } -static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, - unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW96, Decoder); } -static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, - unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus +DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, + const MCDisassembler *Decoder) { return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW128, Decoder); } -static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, - unsigned Imm, +static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) { + const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); } diff --git a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp --- a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -83,41 +83,43 @@ } template -static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, - uint64_t Address = 0, - const void *Decoder = nullptr); +static DecodeStatus +DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address = 0, + const MCDisassembler *Decoder = nullptr); template -static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, - uint64_t Address = 0, - const void *Decoder = nullptr); +static DecodeStatus +DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address = 0, + const MCDisassembler *Decoder = nullptr); template static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *); +static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, + const MCDisassembler *); static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t, - const void *); + const MCDisassembler *); static const uint16_t GPR32DecoderTable[] = { ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6, @@ -128,7 +130,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) { LLVM_DEBUG(dbgs() << "Not a GPR32 register."); return MCDisassembler::Fail; @@ -140,8 +142,8 @@ } static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // Enumerates registers from ranges [r0-r3],[r12-r15]. if (RegNo > 3) RegNo += 8; // 4 for r12, etc... @@ -165,7 +167,7 @@ } static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Dec) { + const MCDisassembler *Dec) { // We have the 9-bit immediate in the low bits, 6-bit register in high bits. unsigned S9 = Insn & 0x1ff; unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9; @@ -175,17 +177,16 @@ } static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, - uint64_t Value, const void *Decoder) { + uint64_t Value, + const MCDisassembler *Decoder) { static const uint64_t AtLeast = 2; - // TODO: Try to force emitter to use MCDisassembler* instead of void*. - auto Disassembler = static_cast(Decoder); - return (nullptr != Disassembler && - Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0, - AtLeast)); + return (nullptr != Decoder && Decoder->tryAddingSymbolicOperand( + Inst, Value, Address, true, 0, AtLeast)); } static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address, - uint64_t Offset, const void *Decoder) { + uint64_t Offset, + const MCDisassembler *Decoder) { uint64_t NextAddress = Address + Offset; if (!DecodeSymbolicOperand(Inst, Address, NextAddress, Decoder)) @@ -194,7 +195,8 @@ template static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { static_assert(B > 0, "field is empty"); DecodeSymbolicOperandOff(Inst, Address, SignExtend32(InsnS), Decoder); @@ -204,7 +206,7 @@ template static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { static_assert(B > 0, "field is empty"); Inst.addOperand(MCOperand::createImm( @@ -215,7 +217,7 @@ template static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { static_assert(B > 0, "field is empty"); const unsigned max = (1u << B) - 1; @@ -226,7 +228,7 @@ static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned SrcC, DstB, LImm; DstB = decodeBField(Insn); if (DstB != 62) { @@ -243,7 +245,7 @@ static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned DstA, SrcB, LImm; LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n"); SrcB = decodeBField(Insn); @@ -261,7 +263,7 @@ static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned DstA, SrcB; LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n"); DstA = decodeAField(Insn); @@ -278,7 +280,7 @@ static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n"); using Field = decltype(Insn); Field H = fieldFromInstruction(Insn, 5, 3) | @@ -304,7 +306,7 @@ static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned DstB; LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n"); DstB = decodeBField(Insn); @@ -318,7 +320,8 @@ } static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned DstB = decodeBField(Insn); DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); @@ -328,7 +331,8 @@ } static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned DstB = decodeBField(Insn); DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -175,410 +175,529 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGPRwithZRnospRegisterClass( - MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, - unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, - unsigned Insn, - uint64_t Adddress, - const void *Decoder); +static DecodeStatus +DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, + uint64_t Adddress, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template -static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +template +static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); template static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); -template + const MCDisassembler *Decoder); +template static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template + uint64_t Address, + const MCDisassembler *Decoder); +template static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder); -template -static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +template +static DecodeStatus +DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -template -static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +template +static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); #include "ARMGenDisassemblerTables.inc" @@ -712,11 +831,11 @@ /// operand to the MCInst and false otherwise. static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, - MCInst &MI, const void *Decoder) { - const MCDisassembler *Dis = static_cast(Decoder); + MCInst &MI, + const MCDisassembler *Decoder) { // FIXME: Does it make sense for value to be negative? - return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, - /* Offset */ 0, InstSize); + return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, + isBranch, /* Offset */ 0, InstSize); } /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being @@ -729,7 +848,7 @@ /// a literal 'C' string if the referenced address of the literal pool's entry /// is an address into a section with 'C' string literals. static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, - const void *Decoder) { + const MCDisassembler *Decoder) { const MCDisassembler *Dis = static_cast(Decoder); Dis->tryAddingPcLoadReferenceComment(Value, Address); } @@ -1144,7 +1263,8 @@ }; static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -1155,7 +1275,7 @@ static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -1167,9 +1287,9 @@ return MCDisassembler::Success; } -static DecodeStatus -DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) @@ -1182,7 +1302,7 @@ static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 13) @@ -1194,8 +1314,8 @@ } static DecodeStatus -DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) @@ -1209,8 +1329,8 @@ } static DecodeStatus -DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 15) @@ -1227,8 +1347,8 @@ } static DecodeStatus -DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo == 13) return MCDisassembler::Fail; @@ -1237,7 +1357,8 @@ } static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); @@ -1249,7 +1370,8 @@ }; static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; // According to the Arm ARM RegNo = 14 is undefined, but we return fail @@ -1265,8 +1387,9 @@ return S; } -static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 13) return MCDisassembler::Fail; @@ -1280,7 +1403,7 @@ static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo != 13) return MCDisassembler::Fail; @@ -1290,7 +1413,8 @@ } static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: @@ -1320,7 +1444,8 @@ } static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; const FeatureBitset &featureBits = @@ -1345,7 +1470,8 @@ }; static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1355,7 +1481,8 @@ } static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); } @@ -1371,7 +1498,8 @@ }; static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { const FeatureBitset &featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); @@ -1386,22 +1514,24 @@ } static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus -DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); @@ -1415,7 +1545,8 @@ }; static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler::Fail; RegNo >>= 1; @@ -1435,7 +1566,8 @@ }; static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 30) return MCDisassembler::Fail; @@ -1455,10 +1587,9 @@ ARM::D28_D30, ARM::D29_D31 }; -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 29) return MCDisassembler::Fail; @@ -1468,7 +1599,8 @@ } static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Val == 0xF) return MCDisassembler::Fail; // AL predicate is not allowed on Thumb1 branches. @@ -1485,7 +1617,8 @@ } static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (Val) Inst.addOperand(MCOperand::createReg(ARM::CPSR)); else @@ -1494,7 +1627,8 @@ } static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction(Val, 0, 4); @@ -1531,7 +1665,8 @@ } static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction(Val, 0, 4); @@ -1566,7 +1701,8 @@ } static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; bool NeedDisjointWriteback = false; @@ -1613,7 +1749,8 @@ } static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Vd = fieldFromInstruction(Val, 8, 5); @@ -1637,7 +1774,8 @@ } static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Vd = fieldFromInstruction(Val, 8, 5); @@ -1662,7 +1800,8 @@ } static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // This operand encodes a mask of contiguous zeros between a specified MSB // and LSB. To decode it, we create the mask of all bits MSB-and-lower, // the mask of all bits LSB-and-lower, and then xor them to create @@ -1689,7 +1828,8 @@ } static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned pred = fieldFromInstruction(Insn, 28, 4); @@ -1867,8 +2007,8 @@ } static DecodeStatus -DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -1973,7 +2113,8 @@ } static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 13, 4); @@ -2017,7 +2158,7 @@ static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) return MCDisassembler::Fail; @@ -2028,9 +2169,9 @@ return MCDisassembler::Success; } -static DecodeStatus -DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -2221,7 +2362,8 @@ } static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -2250,7 +2392,8 @@ } static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -2272,9 +2415,10 @@ return S; } -static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, - unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -2365,7 +2509,8 @@ // Check for UNPREDICTABLE predicated ESB instruction static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned imm8 = fieldFromInstruction(Insn, 0, 8); const MCDisassembler *Dis = static_cast(Decoder); @@ -2387,7 +2532,8 @@ } static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned imod = fieldFromInstruction(Insn, 18, 2); unsigned M = fieldFromInstruction(Insn, 17, 1); unsigned iflags = fieldFromInstruction(Insn, 6, 3); @@ -2434,7 +2580,8 @@ } static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned imod = fieldFromInstruction(Insn, 9, 2); unsigned M = fieldFromInstruction(Insn, 8, 1); unsigned iflags = fieldFromInstruction(Insn, 5, 3); @@ -2475,9 +2622,9 @@ return S; } -static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { unsigned imm = fieldFromInstruction(Insn, 0, 8); unsigned Opcode = ARM::t2HINT; @@ -2501,7 +2648,8 @@ } static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 8, 4); @@ -2525,7 +2673,8 @@ } static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -2552,7 +2701,8 @@ } static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 16, 4); @@ -2580,7 +2730,8 @@ } static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Pred = fieldFromInstruction(Insn, 28, 4); @@ -2601,7 +2752,8 @@ } static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Imm = fieldFromInstruction(Insn, 9, 1); @@ -2629,7 +2781,8 @@ } static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned add = fieldFromInstruction(Val, 12, 1); @@ -2649,7 +2802,8 @@ } static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 9, 4); @@ -2669,7 +2823,8 @@ } static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 9, 4); @@ -2689,13 +2844,14 @@ } static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); } -static DecodeStatus -DecodeT2BInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus Status = MCDisassembler::Success; // Note the J1 and J2 values are from the encoded instruction. So here @@ -2720,9 +2876,9 @@ return Status; } -static DecodeStatus -DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned pred = fieldFromInstruction(Insn, 28, 4); @@ -2751,7 +2907,8 @@ } static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction(Val, 0, 4); @@ -2768,7 +2925,8 @@ } static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3044,7 +3202,8 @@ } static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned type = fieldFromInstruction(Insn, 8, 4); unsigned align = fieldFromInstruction(Insn, 4, 2); if (type == 6 && (align & 2)) return MCDisassembler::Fail; @@ -3057,7 +3216,8 @@ } static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned size = fieldFromInstruction(Insn, 6, 2); if (size == 3) return MCDisassembler::Fail; @@ -3072,7 +3232,8 @@ } static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned size = fieldFromInstruction(Insn, 6, 2); if (size == 3) return MCDisassembler::Fail; @@ -3085,7 +3246,8 @@ } static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned size = fieldFromInstruction(Insn, 6, 2); if (size == 3) return MCDisassembler::Fail; @@ -3095,7 +3257,8 @@ } static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3365,7 +3528,8 @@ } static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3412,7 +3576,8 @@ } static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3460,7 +3625,8 @@ } static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3495,7 +3661,8 @@ } static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3546,9 +3713,9 @@ return S; } -static DecodeStatus -DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3592,9 +3759,9 @@ return S; } -static DecodeStatus -DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | @@ -3622,7 +3789,8 @@ } static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Qd = fieldFromInstruction(Insn, 13, 3); @@ -3647,7 +3815,8 @@ } static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3666,31 +3835,36 @@ } static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(8 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(16 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(32 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(64 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -3726,7 +3900,8 @@ } static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned dst = fieldFromInstruction(Insn, 8, 3); @@ -3750,7 +3925,8 @@ } static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, true, 2, Inst, Decoder)) Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); @@ -3758,7 +3934,8 @@ } static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, true, 4, Inst, Decoder)) Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); @@ -3766,7 +3943,8 @@ } static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, true, 2, Inst, Decoder)) Inst.addOperand(MCOperand::createImm(Val << 1)); @@ -3774,7 +3952,8 @@ } static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 0, 3); @@ -3789,7 +3968,8 @@ } static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 0, 3); @@ -3803,7 +3983,8 @@ } static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned imm = Val << 2; Inst.addOperand(MCOperand::createImm(imm)); @@ -3813,7 +3994,8 @@ } static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createReg(ARM::SP)); Inst.addOperand(MCOperand::createImm(Val)); @@ -3821,7 +4003,8 @@ } static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 6, 4); @@ -3850,7 +4033,8 @@ } static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -3933,7 +4117,8 @@ } static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4017,7 +4202,8 @@ } static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4096,8 +4282,8 @@ return S; } -static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder) { +static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4136,7 +4322,8 @@ } static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, - uint64_t Address, const void* Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -4188,8 +4375,8 @@ return S; } -static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { if (Val == 0) Inst.addOperand(MCOperand::createImm(INT32_MIN)); else { @@ -4203,7 +4390,7 @@ } static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Val == 0) Inst.addOperand(MCOperand::createImm(INT32_MIN)); else { @@ -4218,7 +4405,8 @@ } static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 9, 4); @@ -4234,7 +4422,7 @@ static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 8, 4); @@ -4248,8 +4436,9 @@ return S; } -static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 8, 4); @@ -4263,8 +4452,8 @@ return S; } -static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { int imm = Val & 0xFF; if (Val == 0) imm = INT32_MIN; @@ -4275,9 +4464,9 @@ return MCDisassembler::Success; } -template -static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +template +static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { int imm = Val & 0x7F; if (Val == 0) imm = INT32_MIN; @@ -4291,7 +4480,8 @@ } static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 9, 4); @@ -4336,10 +4526,10 @@ return S; } -template +template static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 8, 3); @@ -4353,10 +4543,10 @@ return S; } -template +template static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 8, 4); @@ -4373,7 +4563,8 @@ } static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -4434,7 +4625,8 @@ } static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 13, 4); @@ -4460,7 +4652,8 @@ } static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned imm = fieldFromInstruction(Insn, 0, 7); Inst.addOperand(MCOperand::createReg(ARM::SP)); @@ -4471,7 +4664,8 @@ } static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Inst.getOpcode() == ARM::tADDrSP) { @@ -4496,7 +4690,8 @@ } static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; unsigned flags = fieldFromInstruction(Insn, 0, 3); @@ -4507,7 +4702,8 @@ } static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned add = fieldFromInstruction(Insn, 4, 1); @@ -4520,7 +4716,8 @@ } static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 3, 4); unsigned Qm = fieldFromInstruction(Insn, 0, 3); @@ -4533,9 +4730,10 @@ return S; } -template +template static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Qm = fieldFromInstruction(Insn, 8, 3); int imm = fieldFromInstruction(Insn, 0, 7); @@ -4557,7 +4755,8 @@ } static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // Val is passed in as S:J1:J2:imm10H:imm10L:'0' // Note only one trailing zero not two. Also the J1 and J2 values are from // the encoded instruction. So here change to I1 and I2 values via: @@ -4581,7 +4780,8 @@ } static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (Val == 0xA || Val == 0xB) return MCDisassembler::Fail; @@ -4595,9 +4795,9 @@ return MCDisassembler::Success; } -static DecodeStatus -DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { const FeatureBitset &FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); DecodeStatus S = MCDisassembler::Success; @@ -4613,9 +4813,9 @@ return S; } -static DecodeStatus -DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned pred = fieldFromInstruction(Insn, 22, 4); @@ -4656,8 +4856,8 @@ // Decode a shifted immediate operand. These basically consist // of an 8-bit value, and a 4-bit directive that specifies either // a splat operation or a rotation. -static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { unsigned ctrl = fieldFromInstruction(Val, 10, 2); if (ctrl == 0) { unsigned byte = fieldFromInstruction(Val, 8, 2); @@ -4687,9 +4887,9 @@ return MCDisassembler::Success; } -static DecodeStatus -DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, true, 2, Inst, Decoder)) Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); @@ -4698,7 +4898,7 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Val is passed in as S:J1:J2:imm10:imm11 // Note no trailing zero after imm11. Also the J1 and J2 values are from // the encoded instruction. So here change to I1 and I2 values via: @@ -4721,7 +4921,8 @@ } static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (Val & ~0xf) return MCDisassembler::Fail; @@ -4730,7 +4931,8 @@ } static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (Val & ~0xf) return MCDisassembler::Fail; @@ -4738,8 +4940,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; const FeatureBitset &FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); @@ -4840,7 +5042,8 @@ } static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned R = fieldFromInstruction(Val, 5, 1); unsigned SysM = fieldFromInstruction(Val, 0, 5); @@ -4855,7 +5058,8 @@ } static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -4877,7 +5081,7 @@ static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rd = fieldFromInstruction(Insn, 12, 4); @@ -4902,7 +5106,8 @@ } static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4927,7 +5132,8 @@ } static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4954,7 +5160,8 @@ } static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -4979,7 +5186,8 @@ } static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5003,8 +5211,8 @@ return S; } -static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5070,8 +5278,8 @@ return S; } -static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5135,8 +5343,8 @@ return S; } -static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5202,8 +5410,8 @@ return S; } -static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5265,8 +5473,8 @@ return S; } -static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5335,8 +5543,8 @@ return S; } -static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5398,8 +5606,8 @@ return S; } -static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5479,8 +5687,8 @@ return S; } -static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5551,8 +5759,8 @@ return S; } -static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); @@ -5577,8 +5785,8 @@ return S; } -static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); @@ -5603,8 +5811,8 @@ return S; } -static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned pred = fieldFromInstruction(Insn, 4, 4); unsigned mask = fieldFromInstruction(Insn, 0, 4); @@ -5632,9 +5840,9 @@ return S; } -static DecodeStatus -DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -5669,9 +5877,9 @@ return S; } -static DecodeStatus -DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 12, 4); @@ -5704,8 +5912,8 @@ return S; } -static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, + const MCDisassembler *Decoder) { unsigned sign1 = fieldFromInstruction(Insn, 21, 1); unsigned sign2 = fieldFromInstruction(Insn, 23, 1); if (sign1 != sign2) return MCDisassembler::Fail; @@ -5732,7 +5940,7 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; // Shift of "asr #32" is not allowed in Thumb2 mode. @@ -5741,8 +5949,8 @@ return S; } -static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -5768,8 +5976,8 @@ return S; } -static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { const FeatureBitset &featureBits = ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; @@ -5827,8 +6035,8 @@ return S; } -static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { const FeatureBitset &featureBits = ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; @@ -5886,10 +6094,10 @@ return S; } -static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); @@ -5919,8 +6127,8 @@ return S; } -static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rn = fieldFromInstruction(Val, 16, 4); @@ -5947,7 +6155,8 @@ } static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned CRm = fieldFromInstruction(Val, 0, 4); @@ -5993,7 +6202,7 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { const FeatureBitset &featureBits = ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); DecodeStatus S = MCDisassembler::Success; @@ -6045,7 +6254,7 @@ template static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Val == 0 && !zeroPermitted) S = MCDisassembler::Fail; @@ -6064,7 +6273,7 @@ static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { uint64_t LocImm = Inst.getOperand(0).getImm(); Val = LocImm + (2 << Val); @@ -6076,7 +6285,7 @@ static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Val >= ARMCC::AL) // also exclude the non-condition NV return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(Val)); @@ -6084,7 +6293,7 @@ } static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Inst.getOpcode() == ARM::MVE_LCTP) @@ -6147,7 +6356,7 @@ static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Val == 0) @@ -6159,7 +6368,8 @@ } static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if ((RegNo) + 1 > 11) return MCDisassembler::Fail; @@ -6169,7 +6379,8 @@ } static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if ((RegNo) > 14) return MCDisassembler::Fail; @@ -6180,7 +6391,8 @@ static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo == 15) { Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); return MCDisassembler::Success; @@ -6196,7 +6408,7 @@ } static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createImm(ARMCC::AL)); @@ -6222,8 +6434,8 @@ } static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; @@ -6239,7 +6451,7 @@ static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 6) return MCDisassembler::Fail; @@ -6255,7 +6467,7 @@ static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 4) return MCDisassembler::Fail; @@ -6266,7 +6478,7 @@ static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; // Parse VPT mask and encode it in the MCInst as an immediate with the same @@ -6296,7 +6508,8 @@ } static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // The vpred_r operand type includes an MQPR register field derived // from the encoding. But we don't actually want to add an operand // to the MCInst at this stage, because AddThumbPredicate will do it @@ -6307,18 +6520,16 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); return MCDisassembler::Success; } -static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { unsigned Code; switch (Val & 0x3) { case 0: @@ -6338,17 +6549,16 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); return MCDisassembler::Success; } -static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { unsigned Code; switch (Val) { default: @@ -6378,7 +6588,8 @@ } static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned DecodedVal = 64 - Val; @@ -6419,10 +6630,10 @@ } } -template +template static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { switch (Inst.getOpcode()) { case ARM::VSTR_FPSCR_pre: case ARM::VSTR_FPSCR_NZCVQC_pre: @@ -6463,9 +6674,10 @@ return S; } -static inline DecodeStatus DecodeMVE_MEM_pre( - MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, - unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { +static inline DecodeStatus +DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder, unsigned Rn, + OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { DecodeStatus S = MCDisassembler::Success; unsigned Qd = fieldFromInstruction(Val, 13, 3); @@ -6484,7 +6696,8 @@ template static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, fieldFromInstruction(Val, 16, 3), DecodetGPRRegisterClass, @@ -6493,7 +6706,8 @@ template static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, fieldFromInstruction(Val, 16, 4), DecoderGPRRegisterClass, @@ -6502,17 +6716,18 @@ template static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, fieldFromInstruction(Val, 17, 3), DecodeMQPRRegisterClass, DecodeMveAddrModeQ); } -template +template static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (Val < MinLog || Val > MaxLog) @@ -6522,10 +6737,10 @@ return S; } -template -static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder) { +template +static DecodeStatus +DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createImm(start + Val)); @@ -6534,7 +6749,8 @@ } static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 0, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); @@ -6557,7 +6773,8 @@ } static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction(Insn, 0, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); @@ -6581,8 +6798,9 @@ return S; } -static DecodeStatus DecodeMVEOverlappingLongShift( - MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; @@ -6660,8 +6878,9 @@ return S; } -static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | fieldFromInstruction(Insn, 13, 3)); @@ -6679,9 +6898,9 @@ return S; } -template +template static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createReg(ARM::VPR)); unsigned Qn = fieldFromInstruction(Insn, 17, 3); @@ -6718,7 +6937,7 @@ } static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createReg(ARM::VPR)); unsigned Rn = fieldFromInstruction(Insn, 16, 4); @@ -6727,8 +6946,9 @@ return S; } -static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; Inst.addOperand(MCOperand::createReg(ARM::VPR)); Inst.addOperand(MCOperand::createReg(ARM::VPR)); @@ -6736,7 +6956,8 @@ } static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { const unsigned Rd = fieldFromInstruction(Insn, 8, 4); const unsigned Rn = fieldFromInstruction(Insn, 16, 4); const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp --- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp +++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp @@ -66,7 +66,7 @@ static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -77,7 +77,7 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -88,46 +88,50 @@ static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Note: this function must be defined but does not seem to be called. assert(false && "unimplemented: PTRREGS register class"); return MCDisassembler::Success; } static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); #include "AVRGenDisassemblerTables.inc" static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = 0; addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 9, 2) << 4; @@ -140,7 +144,7 @@ } static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = 0; addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 9, 2) << 4; @@ -153,7 +157,7 @@ } static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = fieldFromInstruction(Insn, 3, 5); unsigned b = fieldFromInstruction(Insn, 0, 3); Inst.addOperand(MCOperand::createImm(addr)); @@ -162,7 +166,8 @@ } static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // Call targets need to be shifted left by one so this needs a custom // decoder. Inst.addOperand(MCOperand::createImm(Field << 1)); @@ -170,7 +175,7 @@ } static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 5); if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) @@ -179,7 +184,7 @@ } static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(AVR::R31R30)); @@ -187,7 +192,8 @@ } static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == @@ -200,7 +206,8 @@ } static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned r = fieldFromInstruction(Insn, 4, 4) * 2; unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == @@ -213,7 +220,7 @@ } static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25 unsigned k = 0; k |= fieldFromInstruction(Insn, 0, 4); @@ -229,7 +236,8 @@ } static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16; unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16; if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == @@ -323,4 +331,4 @@ } typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp --- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp +++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp @@ -100,7 +100,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { if (RegNo > 11) return MCDisassembler::Fail; @@ -113,9 +113,9 @@ BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W10, BPF::W11}; -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void * /*Decoder*/) { +static DecodeStatus +DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler * /*Decoder*/) { if (RegNo > 11) return MCDisassembler::Fail; @@ -125,7 +125,8 @@ } static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Register = (Insn >> 16) & 0xf; if (Register > 11) return MCDisassembler::Fail; @@ -221,4 +222,4 @@ } typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); diff --git a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp --- a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp +++ b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp @@ -108,7 +108,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -118,7 +118,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -128,7 +128,7 @@ static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 16) return MCDisassembler::Fail; @@ -138,7 +138,7 @@ static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 16) return MCDisassembler::Fail; @@ -148,7 +148,7 @@ static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 16) return MCDisassembler::Fail; @@ -158,7 +158,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -168,7 +168,7 @@ static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 16) return MCDisassembler::Fail; @@ -178,7 +178,7 @@ static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 16) return MCDisassembler::Fail; @@ -188,7 +188,7 @@ static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 8) return MCDisassembler::Fail; @@ -198,7 +198,7 @@ static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo != 14) return MCDisassembler::Fail; @@ -208,11 +208,9 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { const FeatureBitset &FeatureBits = - static_cast(Decoder) - ->getSubtargetInfo() - .getFeatureBits(); + Decoder->getSubtargetInfo().getFeatureBits(); bool hasHighReg = FeatureBits[CSKY::FeatureHighreg]; if (RegNo >= 32 || (!hasHighReg && RegNo >= 16)) @@ -224,7 +222,8 @@ template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(Imm << S)); return MCDisassembler::Success; @@ -232,14 +231,15 @@ template static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(Imm + 1)); return MCDisassembler::Success; } static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<8>(Imm) && "Invalid immediate"); if ((Imm >> 7) & 0x1) { Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2)); @@ -253,7 +253,7 @@ static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<2>(Imm) && "Invalid immediate"); if (Imm == 0) @@ -271,7 +271,8 @@ } static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt<10>(Imm) && "Invalid immediate"); auto Imm5 = Imm & 0x1f; @@ -288,7 +289,7 @@ static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<10>(Imm) && "Invalid immediate"); auto Imm5 = Imm & 0x1f; @@ -305,7 +306,7 @@ static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<10>(Imm) && "Invalid immediate"); auto Imm5 = Imm & 0x1f; @@ -322,7 +323,7 @@ static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<10>(Imm) && "Invalid immediate"); auto Imm5 = Imm & 0x1f; @@ -339,7 +340,7 @@ static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<10>(Imm) && "Invalid immediate"); auto Imm5 = Imm & 0x1f; @@ -356,14 +357,15 @@ static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(Log2(Imm))); return MCDisassembler::Success; } template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); // Sign-extend the number in the bottom N bits of Imm Inst.addOperand(MCOperand::createImm(SignExtend64(Imm) << S)); @@ -488,7 +490,7 @@ } static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address, - const void *DisAsm, + const MCDisassembler *DisAsm, const MCSubtargetInfo &STI) { LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n"); if (!STI.getFeatureBits()[CSKY::FeatureFPUV3_HF] && diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -78,11 +78,12 @@ uint64_t Operand = Upper26 | Lower6; return Operand; } -static HexagonDisassembler const &disassembler(void const *Decoder) { +static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) { return *static_cast(Decoder); } template -static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { +static void signedDecoder(MCInst &MI, unsigned tmp, + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); int64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp)); int64_t Extended = SignExtend64<32>(FullValue); @@ -95,65 +96,66 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, + const MCDisassembler *Decoder); +static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); - + const MCDisassembler *Decoder); static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder); + uint64_t /*Address*/, + const MCDisassembler *Decoder); static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "HexagonDepDecoders.inc" #include "HexagonGenDisassemblerTables.inc" @@ -542,15 +544,15 @@ return MCDisassembler::Fail; } -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg IntRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, @@ -563,10 +565,10 @@ return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); } -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { static const MCPhysReg GeneralSubRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, @@ -579,7 +581,7 @@ static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxVRDecoderTable[] = { Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, @@ -592,9 +594,10 @@ return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); } -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg DoubleRegDecoderTable[] = { Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, @@ -604,8 +607,10 @@ return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); } -static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( - MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { +static DecodeStatus +DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; @@ -615,7 +620,7 @@ static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxWRDecoderTable[] = { Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, @@ -629,11 +634,11 @@ return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); } -LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. + static DecodeStatus + DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg HvxVQRDecoderTable[] = { Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; @@ -643,7 +648,7 @@ static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3}; @@ -652,7 +657,7 @@ static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3}; @@ -661,7 +666,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg CtrlRegDecoderTable[] = { @@ -687,9 +692,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg CtrlReg64DecoderTable[] = { @@ -717,7 +722,7 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: @@ -735,7 +740,7 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); int64_t FullValue = fullValue(Disassembler, MI, tmp); assert(FullValue >= 0 && "Negative in unsigned decoder"); @@ -744,7 +749,8 @@ } static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { + uint64_t /*Address*/, + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); tmp = SignExtend64(tmp, Bits); @@ -754,7 +760,7 @@ // custom decoder for various jump/call immediates static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); // r13_2 is not extendable, so if there are no extent bits, it's r13_2 @@ -799,7 +805,7 @@ static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) return MCDisassembler::Fail; @@ -824,9 +830,9 @@ Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, }; -static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { RegNo = RegNo >> 1; if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0])) return MCDisassembler::Fail; @@ -839,9 +845,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg GuestRegDecoderTable[] = { @@ -865,9 +871,10 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg GuestReg64DecoderTable[] = { diff --git a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc --- a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc +++ b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc @@ -14,58 +14,58 @@ #pragma clang diagnostic ignored "-Wunused-function" #endif -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<12>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<13>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<14>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<3>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<4>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<5>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<7>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<9>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<8>(MI, tmp, Decoder); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp --- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -45,26 +45,30 @@ // Definition is further down. static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); #include "LanaiGenDisassemblerTables.inc" @@ -158,7 +162,7 @@ DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { if (RegNo > 31) return MCDisassembler::Fail; @@ -168,7 +172,8 @@ } static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // RI memory values encoded using 23 bits: // 5 bit register, 16 bit constant unsigned Register = (Insn >> 18) & 0x1f; @@ -180,7 +185,8 @@ } static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // RR memory values encoded using 20 bits: // 5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ unsigned Register = (Insn >> 15) & 0x1f; @@ -192,7 +198,8 @@ } static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // RI memory values encoded using 17 bits: // 5 bit register, 10 bit constant unsigned Register = (Insn >> 12) & 0x1f; @@ -206,14 +213,13 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, - const void *Decoder) { - const MCDisassembler *Dis = static_cast(Decoder); - return Dis->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset, - Width); + const MCDisassembler *Decoder) { + return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset, + Width); } static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI, Decoder)) MI.addOperand(MCOperand::createImm(Insn)); @@ -221,7 +227,8 @@ } static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Offset = (Insn & 0xffff); Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); @@ -230,7 +237,7 @@ static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Val >= LPCC::UNKNOWN) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(Val)); diff --git a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp --- a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp +++ b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp @@ -57,7 +57,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); @@ -66,7 +66,8 @@ template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(Imm + P)); return MCDisassembler::Success; @@ -74,7 +75,8 @@ template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); // Sign-extend the number in the bottom bits of Imm, then shift left // bits. diff --git a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp --- a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp +++ b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp @@ -72,7 +72,7 @@ static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -90,7 +90,7 @@ static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -100,16 +100,16 @@ } static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "MSP430GenDisassemblerTables.inc" static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int64_t Imm; switch (Bits) { default: @@ -127,7 +127,7 @@ static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Reg = Bits & 15; unsigned Imm = Bits >> 4; diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -79,338 +79,279 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); +static DecodeStatus +DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); +static DecodeStatus +DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeBranchTarget(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeJumpTarget(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeBranchTarget21(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeBranchTarget26(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is // shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is // shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeBranchTargetMM - Decode microMIPS branch offset, which is // shifted left by 1 bit. -static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is // shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeJumpTargetMM - Decode microMIPS jump target, which is // shifted left by 1 bit. -static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, // which is shifted left by 2 bit. -static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMem(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemEVA(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeLoadByte15(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeCacheOpMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodePrefeOpMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeSyncI(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeSyncI_MM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeSynciR6(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMImm4(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMImm9(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMImm12(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeMemMMImm16(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeLi16Imm(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeUImmWithOffsetAndScale(Inst, Value, Address, Decoder); } @@ -418,128 +359,132 @@ template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeInsSize(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// handle. template static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); template static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template -static DecodeStatus -DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder); +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const MCDisassembler *Decoder); template static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static MCDisassembler *createMipsDisassembler( const Target &T, @@ -569,16 +514,16 @@ #include "MipsGenDisassemblerTables.inc" -static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { - const MipsDisassembler *Dis = static_cast(D); - const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); +static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { + const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo(); return *(RegInfo->getRegClass(RC).begin() + RegNo); } template static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { - using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); + const MCDisassembler *Decoder) { + using DecodeFN = + DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *); // The size of the n field depends on the element size // The register class also depends on this. @@ -624,7 +569,8 @@ template static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { InsnType Rs = fieldFromInstruction(insn, 16, 5); InsnType Imm = fieldFromInstruction(insn, 0, 16); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, @@ -638,7 +584,7 @@ template static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Imm = fieldFromInstruction(insn, 0, 16); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, @@ -653,7 +599,7 @@ template static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier // ISA's instead). @@ -692,7 +638,7 @@ template static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); int64_t Imm = 0; @@ -726,7 +672,7 @@ template static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier // ISA's instead). @@ -765,7 +711,7 @@ template static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); int64_t Imm = 0; @@ -799,7 +745,7 @@ template static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // We have: // 0b110101 ttttt sssss iiiiiiiiiiiiiiii // Invalid if rt == 0 @@ -838,7 +784,7 @@ template static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // We have: // 0b111101 ttttt sssss iiiiiiiiiiiiiiii // Invalid if rt == 0 @@ -877,7 +823,7 @@ template static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier // ISA's instead). @@ -920,7 +866,7 @@ template static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZL instruction from the earlier // ISA's instead). @@ -964,7 +910,7 @@ template static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZ instruction from the earlier // ISA's instead). @@ -1012,8 +958,8 @@ template static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier // ISA's instead). @@ -1056,7 +1002,7 @@ // for feature / behaviour parity with binutils. template static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Msbd = fieldFromInstruction(Insn, 11, 5); unsigned Lsb = fieldFromInstruction(Insn, 6, 5); unsigned Size = 0; @@ -1098,7 +1044,7 @@ // for feature / behaviour parity with binutils. template static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Msbd = fieldFromInstruction(Insn, 11, 5); unsigned Lsb = fieldFromInstruction(Insn, 6, 5); unsigned Size = 0; @@ -1140,7 +1086,7 @@ // Auto-generated decoder wouldn't add the third operand for CRC32*. template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { InsnType Rs = fieldFromInstruction(Insn, 21, 5); InsnType Rt = fieldFromInstruction(Insn, 16, 5); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, @@ -1384,17 +1330,15 @@ return MCDisassembler::Fail; } -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return MCDisassembler::Fail; } -static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1403,10 +1347,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); @@ -1414,10 +1357,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); @@ -1425,10 +1367,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); @@ -1436,10 +1377,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); @@ -1447,27 +1387,24 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (static_cast(Decoder)->isGP64()) return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1476,10 +1413,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1488,10 +1424,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); @@ -1499,10 +1434,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); @@ -1512,7 +1446,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -1521,10 +1455,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMem(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1543,10 +1475,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemEVA(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn >> 7); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1564,10 +1494,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeLoadByte15(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Reg = fieldFromInstruction(Insn, 21, 5); @@ -1582,10 +1511,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCacheOp(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Hint = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1599,10 +1526,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCacheOpMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<12>(Insn & 0xfff); unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Hint = fieldFromInstruction(Insn, 21, 5); @@ -1616,10 +1542,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePrefeOpMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn & 0x1ff); unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Hint = fieldFromInstruction(Insn, 21, 5); @@ -1633,10 +1558,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn >> 7); unsigned Hint = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1650,10 +1574,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeSyncI(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1666,7 +1588,8 @@ } static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -1678,10 +1601,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeSynciR6(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Immediate = SignExtend32<16>(Insn & 0xffff); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -1694,7 +1615,8 @@ } static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); unsigned Reg = fieldFromInstruction(Insn, 6, 5); unsigned Base = fieldFromInstruction(Insn, 11, 5); @@ -1739,10 +1661,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMImm4(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Offset = Insn & 0xf; unsigned Reg = fieldFromInstruction(Insn, 7, 3); unsigned Base = fieldFromInstruction(Insn, 4, 3); @@ -1797,10 +1718,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Offset = Insn & 0x1F; unsigned Reg = fieldFromInstruction(Insn, 5, 5); @@ -1813,10 +1733,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Offset = Insn & 0x7F; unsigned Reg = fieldFromInstruction(Insn, 7, 3); @@ -1829,10 +1748,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset; switch (Inst.getOpcode()) { case Mips::LWM16_MMR6: @@ -1854,10 +1772,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMImm9(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn & 0x1ff); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -1875,10 +1792,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMImm12(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<12>(Insn & 0x0fff); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -1910,10 +1826,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMemMMImm16(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -1928,10 +1843,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFMem(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1947,7 +1860,8 @@ } static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // This function is the same as DecodeFMem but with the Reg and Base fields // swapped according to microMIPS spec. int Offset = SignExtend32<16>(Insn & 0xffff); @@ -1964,10 +1878,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFMem2(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -1982,10 +1894,8 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFMem3(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -2000,10 +1910,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<11>(Insn & 0x07ff); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 11, 5); @@ -2019,7 +1928,8 @@ } static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { int Offset = SignExtend32<11>(Insn & 0x07ff); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); @@ -2034,10 +1944,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); unsigned Rt = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); @@ -2056,10 +1965,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Currently only hardware register 29 is supported. if (RegNo != 29) return MCDisassembler::Fail; @@ -2067,10 +1975,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 30 || RegNo %2) return MCDisassembler::Fail; @@ -2079,10 +1986,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 4) return MCDisassembler::Fail; @@ -2091,10 +1997,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 4) return MCDisassembler::Fail; @@ -2103,10 +2008,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 4) return MCDisassembler::Fail; @@ -2115,10 +2019,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2127,10 +2030,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2139,10 +2041,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2151,10 +2052,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2163,10 +2063,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; @@ -2175,10 +2074,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2187,10 +2085,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -2199,122 +2096,109 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeJumpTarget(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; Inst.addOperand(MCOperand::createImm(JumpOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget21(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget26(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<8>(Offset << 1); Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<11>(Offset << 1); Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, - unsigned Offset, +static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, - unsigned Offset, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, + uint64_t Address, + const MCDisassembler *Decoder) { int32_t BranchOffset = SignExtend32<27>(Offset << 1); Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; Inst.addOperand(MCOperand::createImm(JumpOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; Inst.addOperand(MCOperand::createImm(JumpOffset)); return MCDisassembler::Success; } -static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Value == 0) Inst.addOperand(MCOperand::createImm(1)); else if (Value == 0x7) @@ -2324,10 +2208,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeLi16Imm(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Value == 0x7F) Inst.addOperand(MCOperand::createImm(-1)); else @@ -2335,18 +2218,17 @@ return MCDisassembler::Success; } -static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, - unsigned Value, +static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); return MCDisassembler::Success; } template -static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, + const MCDisassembler *Decoder) { Value &= ((1 << Bits) - 1); Value *= Scale; Inst.addOperand(MCOperand::createImm(Value + Offset)); @@ -2354,18 +2236,16 @@ } template -static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, + const MCDisassembler *Decoder) { int32_t Imm = SignExtend32(Value) * ScaleBy; Inst.addOperand(MCOperand::createImm(Imm + Offset)); return MCDisassembler::Success; } -static DecodeStatus DecodeInsSize(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { // First we need to grab the pos(lsb) from MCInst. // This function only handles the 32 bit variants of ins, as dins // variants are handled differently. @@ -2376,19 +2256,21 @@ } static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); return MCDisassembler::Success; } static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); return MCDisassembler::Success; } -static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { int32_t DecodedValue; switch (Insn) { case 0: DecodedValue = 256; break; @@ -2402,7 +2284,8 @@ } static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // Insn must be >= 0, since it is unsigned that condition is always true. assert(Insn < 16); int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, @@ -2411,10 +2294,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeRegListOperand(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::FP}; unsigned RegNum; @@ -2442,7 +2324,7 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; unsigned RegLst; switch(Inst.getOpcode()) { @@ -2465,8 +2347,8 @@ } static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned RegPair = fieldFromInstruction(Insn, 7, 3); if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == MCDisassembler::Fail) @@ -2491,7 +2373,8 @@ } static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { switch (RegPair) { default: return MCDisassembler::Fail; @@ -2533,15 +2416,16 @@ } static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); return MCDisassembler::Success; } template static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // We have: // 0b000111 ttttt sssss iiiiiiiiiiiiiiii // Invalid if rt == 0 @@ -2589,8 +2473,8 @@ template static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // We have: // 0b000110 ttttt sssss iiiiiiiiiiiiiiii // Invalid if rt == 0 diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -64,14 +64,14 @@ static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); return MCDisassembler::Success; } static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t /*Address*/, - const void * /*Decoder*/) { + const MCDisassembler * /*Decoder*/) { int32_t Offset = SignExtend32<24>(Imm); Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; @@ -90,85 +90,85 @@ static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, CRRegs); } static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, CRBITRegs); } static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs); } static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs); } static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VFRegs); } static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VRegs); } static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VSRegs); } static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VSFRegs); } static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VSSRegs); } static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, RRegs); } -static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, RRegsNoR0); } static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegs); } static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegs); } -static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, XRegsNoX0); } @@ -176,44 +176,47 @@ #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SPERegs); } static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, ACCRegs); } static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, VSRpRegs); } #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass -template +template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } -template +template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); return MCDisassembler::Success; } static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { if (Imm != 0) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(Imm)); @@ -222,7 +225,7 @@ static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo & 1) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); @@ -230,7 +233,8 @@ } static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the memri field (imm, reg), which has the low 16-bits as the // displacement and the next 5 bits as the register #. @@ -265,7 +269,8 @@ } static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the memrix field (imm, reg), which has the low 14-bits as the // displacement and the next 5 bits as the register #. @@ -287,7 +292,7 @@ static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Decode the memrix field for a hash store or hash check operation. // The field is composed of a register and an immediate value that is 6 bits // and covers the range -8 to -512. The immediate is always negative and 2s @@ -303,7 +308,8 @@ } static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the memrix16 field (imm, reg), which has the low 12-bits as the // displacement with 16-byte aligned, and the next 5 bits as the register #. @@ -319,7 +325,7 @@ static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the // displacement, and the next 5 bits as an immediate 0. uint64_t Base = Imm >> 34; @@ -333,7 +339,7 @@ static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Decode the memri34 field (imm, reg), which has the low 34-bits as the // displacement, and the next 5 bits as the register #. uint64_t Base = Imm >> 34; @@ -347,7 +353,8 @@ } static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the spe8disp field (imm, reg), which has the low 5-bits as the // displacement with 8-byte aligned, and the next 5 bits as the register #. @@ -362,7 +369,8 @@ } static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the spe4disp field (imm, reg), which has the low 5-bits as the // displacement with 4-byte aligned, and the next 5 bits as the register #. @@ -377,7 +385,8 @@ } static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // Decode the spe2disp field (imm, reg), which has the low 5-bits as the // displacement with 2-byte aligned, and the next 5 bits as the register #. @@ -392,7 +401,8 @@ } static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { // The cr bit encoding is 0x80 >> cr_reg_num. unsigned Zeros = countTrailingZeros(Imm); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -60,11 +60,9 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { const FeatureBitset &FeatureBits = - static_cast(Decoder) - ->getSubtargetInfo() - .getFeatureBits(); + Decoder->getSubtargetInfo().getFeatureBits(); bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) @@ -77,7 +75,7 @@ static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -88,7 +86,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -99,7 +97,7 @@ static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 8) { return MCDisassembler::Fail; } @@ -110,7 +108,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -121,7 +119,7 @@ static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 8) { return MCDisassembler::Fail; } @@ -132,7 +130,7 @@ static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo == 0) { return MCDisassembler::Fail; } @@ -140,9 +138,9 @@ return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo == 2) { return MCDisassembler::Fail; } @@ -152,7 +150,7 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 8) return MCDisassembler::Fail; @@ -163,7 +161,7 @@ static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32 || RegNo & 1) return MCDisassembler::Fail; @@ -174,7 +172,7 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -185,7 +183,7 @@ static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -205,7 +203,7 @@ static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -225,7 +223,7 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= 32) return MCDisassembler::Fail; @@ -244,7 +242,8 @@ } static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { MCRegister Reg = RISCV::NoRegister; switch (RegNo) { default: @@ -261,7 +260,8 @@ // Add implied SP operand for instructions *SP compressed instructions. The SP // operand isn't explicitly encoded in the instruction. -static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { +static void addImplySP(MCInst &Inst, int64_t Address, + const MCDisassembler *Decoder) { if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || Inst.getOpcode() == RISCV::C_FLWSP || @@ -279,7 +279,8 @@ template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); Inst.addOperand(MCOperand::createImm(Imm)); @@ -289,7 +290,7 @@ template static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Imm == 0) return MCDisassembler::Fail; return decodeUImmOperand(Inst, Imm, Address, Decoder); @@ -297,7 +298,8 @@ template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, - int64_t Address, const void *Decoder) { + int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); // Sign-extend the number in the bottom N bits of Imm @@ -308,7 +310,7 @@ template static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (Imm == 0) return MCDisassembler::Fail; return decodeSImmOperand(Inst, Imm, Address, Decoder); @@ -317,7 +319,7 @@ template static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid immediate"); // Sign-extend the number in the bottom N bits of Imm after accounting for // the fact that the N bit immediate is stored in N-1 bits (the LSB is @@ -328,7 +330,7 @@ static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { assert(isUInt<6>(Imm) && "Invalid immediate"); if (Imm > 31) { Imm = (SignExtend64<6>(Imm) & 0xfffff); @@ -337,9 +339,8 @@ return MCDisassembler::Success; } -static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) { +static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, + const MCDisassembler *Decoder) { assert(isUInt<3>(Imm) && "Invalid immediate"); if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm)) return MCDisassembler::Fail; @@ -349,26 +350,30 @@ } static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "RISCVGenDisassemblerTables.inc" static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); @@ -379,7 +384,7 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeGPRRegisterClass(Inst, 0, Address, Decoder); uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); @@ -391,7 +396,7 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { DecodeGPRRegisterClass(Inst, 0, Address, Decoder); Inst.addOperand(Inst.getOperand(0)); uint64_t UImm6 = @@ -403,7 +408,8 @@ } static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); @@ -413,7 +419,7 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -142,10 +142,9 @@ SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 }; -static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = IntRegDecoderTable[RegNo]; @@ -153,10 +152,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = IntRegDecoderTable[RegNo]; @@ -164,11 +162,9 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = FPRegDecoderTable[RegNo]; @@ -176,11 +172,9 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = DFPRegDecoderTable[RegNo]; @@ -188,11 +182,9 @@ return MCDisassembler::Success; } - -static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -203,10 +195,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = CPRegDecoderTable[RegNo]; @@ -216,7 +207,7 @@ static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 3) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); @@ -225,7 +216,7 @@ static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); @@ -233,8 +224,8 @@ } static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo >= array_lengthof(PRRegDecoderTable)) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); @@ -242,7 +233,8 @@ } static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { DecodeStatus S = MCDisassembler::Success; if (RegNo > 31) @@ -257,7 +249,8 @@ } static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -267,45 +260,52 @@ } static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -363,13 +363,12 @@ return MCDisassembler::Fail; } - typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder, - bool isLoad, DecodeFunc DecodeRD) { + const MCDisassembler *Decoder, bool isLoad, + DecodeFunc DecodeRD) { unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5); bool isImm = fieldFromInstruction(insn, 13, 1); @@ -415,100 +414,106 @@ } static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeIntRegsRegisterClass); } -static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeIntPairRegisterClass); } static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeFPRegsRegisterClass); } static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeDFPRegsRegisterClass); } static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeQFPRegsRegisterClass); } static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeCPRegsRegisterClass); } -static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeCPPairRegisterClass); } static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeIntRegsRegisterClass); } static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeIntPairRegisterClass); } static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeFPRegsRegisterClass); } static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeDFPRegsRegisterClass); } static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeQFPRegsRegisterClass); } -static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeCPRegsRegisterClass); } static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeCPPairRegisterClass); } -static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, +static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, - const void *Decoder) { - const MCDisassembler *Dis = static_cast(Decoder); - return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, - Offset, Width); + const MCDisassembler *Decoder) { + return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset, + Width); } -static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder) { unsigned tgt = fieldFromInstruction(insn, 0, 30); tgt <<= 2; if (!tryAddingSymbolicOperand(tgt+Address, false, Address, @@ -517,15 +522,15 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, + const MCDisassembler *Decoder) { unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); MI.addOperand(MCOperand::createImm(tgt)); return MCDisassembler::Success; } static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5); @@ -559,7 +564,7 @@ } static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned isImm = fieldFromInstruction(insn, 13, 1); @@ -587,7 +592,7 @@ } static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5); @@ -627,7 +632,7 @@ } static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned isImm = fieldFromInstruction(insn, 13, 1); diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -73,10 +73,9 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, - const void *Decoder) { - const MCDisassembler *Dis = static_cast(Decoder); - return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, - Offset, Width); + const MCDisassembler *Decoder) { + return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset, + Width); } static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, @@ -91,79 +90,79 @@ static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); } static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); } static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); } -static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16); } static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16); } static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16); } static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32); } static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32); } static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32); } static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16); } static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16); } @@ -184,70 +183,81 @@ } static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<1>(Inst, Imm); } static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<2>(Inst, Imm); } static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<3>(Inst, Imm); } static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<4>(Inst, Imm); } static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<6>(Inst, Imm); } static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<8>(Inst, Imm); } static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<12>(Inst, Imm); } static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<16>(Inst, Imm); } static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeUImmOperand<32>(Inst, Imm); } static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeSImmOperand<8>(Inst, Imm); } static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeSImmOperand<16>(Inst, Imm); } static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return decodeSImmOperand<32>(Inst, Imm); } -template +template static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, - bool isBranch, - const void *Decoder) { + uint64_t Address, bool isBranch, + const MCDisassembler *Decoder) { assert(isUInt(Imm) && "Invalid PC-relative offset"); uint64_t Value = SignExtend64(Imm) * 2 + Address; @@ -260,31 +270,31 @@ static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder); } static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder); } static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder); } static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder); } static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder); } @@ -382,64 +392,61 @@ static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs); } static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs); } static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs); } static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, - uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, - uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, - uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs); } -static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, + const MCDisassembler *Decoder) { return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs); } diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp --- a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp +++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp @@ -126,7 +126,7 @@ static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 63) return MCDisassembler::Fail; unsigned Reg = I32RegDecoderTable[RegNo]; @@ -136,7 +136,7 @@ static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 63) return MCDisassembler::Fail; unsigned Reg = I64RegDecoderTable[RegNo]; @@ -146,7 +146,7 @@ static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 63) return MCDisassembler::Fail; unsigned Reg = F32RegDecoderTable[RegNo]; @@ -156,7 +156,7 @@ static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo % 2 || RegNo > 63) return MCDisassembler::Fail; unsigned Reg = F128RegDecoderTable[RegNo / 2]; @@ -166,7 +166,7 @@ static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Reg = VE::NoRegister; if (RegNo == 255) Reg = VE::VIX; @@ -180,7 +180,7 @@ static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; unsigned Reg = VMRegDecoderTable[RegNo]; @@ -190,7 +190,7 @@ static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo % 2 || RegNo > 15) return MCDisassembler::Fail; unsigned Reg = VM512RegDecoderTable[RegNo / 2]; @@ -200,7 +200,7 @@ static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 30) return MCDisassembler::Fail; unsigned Reg = MiscRegDecoderTable[RegNo]; @@ -211,47 +211,56 @@ } static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "VEGenDisassemblerTables.inc" @@ -302,10 +311,10 @@ } typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned sy = fieldFromInstruction(insn, 40, 7); bool cy = fieldFromInstruction(insn, 47, 1); unsigned sz = fieldFromInstruction(insn, 32, 7); @@ -338,7 +347,7 @@ } static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned sz = fieldFromInstruction(insn, 32, 7); bool cz = fieldFromInstruction(insn, 39, 1); uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); @@ -360,7 +369,7 @@ } static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder, bool isLoad, + const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX) { unsigned sx = fieldFromInstruction(insn, 48, 7); @@ -384,7 +393,7 @@ } static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder, bool isLoad, + const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeSX) { unsigned sx = fieldFromInstruction(insn, 48, 7); @@ -408,50 +417,55 @@ } static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); } static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); } static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); } static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); } static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); } static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); } static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMemAS(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); } static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { return DecodeMemAS(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); } static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder, bool isImmOnly, bool isUImm, - DecodeFunc DecodeSX) { + const MCDisassembler *Decoder, bool isImmOnly, + bool isUImm, DecodeFunc DecodeSX) { unsigned sx = fieldFromInstruction(insn, 48, 7); bool cy = fieldFromInstruction(insn, 47, 1); unsigned sy = fieldFromInstruction(insn, 40, 7); @@ -488,43 +502,43 @@ } static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, true, DecodeI64RegisterClass); } static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, true, DecodeI32RegisterClass); } static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, false, DecodeI64RegisterClass); } static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeCAS(MI, insn, Address, Decoder, false, false, DecodeI32RegisterClass); } static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); } static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { uint64_t tgt = SignExtend64<7>(insn); MI.addOperand(MCOperand::createImm(tgt)); return MCDisassembler::Success; } static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { uint64_t tgt = SignExtend64<32>(insn); MI.addOperand(MCOperand::createImm(tgt)); return MCDisassembler::Success; @@ -568,14 +582,14 @@ // Decode CC Operand field. static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); return MCDisassembler::Success; } // Decode RD Operand field. static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { MI.addOperand(MCOperand::createImm(VEValToRD(cf))); return MCDisassembler::Success; } @@ -583,7 +597,7 @@ // Decode branch condition instruction and CCOperand field in it. static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned cf = fieldFromInstruction(insn, 48, 4); bool cy = fieldFromInstruction(insn, 47, 1); unsigned sy = fieldFromInstruction(insn, 40, 7); @@ -607,7 +621,7 @@ static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { // Decode MEMri. return DecodeAS(MI, insn, Address, Decoder); } diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -66,140 +66,116 @@ return true; } -static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { - const XCoreDisassembler *Dis = static_cast(D); - const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); +static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { + const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo(); return *(RegInfo->getRegClass(RC).begin() + RegNo); } -static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus Decode2RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode2RImmInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeR2RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeRUSInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus +DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); -static DecodeStatus DecodeL2RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode3RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode3RImmInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode2RUSInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL3RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL6RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL5RInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, - unsigned Insn, +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); -static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); +static DecodeStatus +DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); #include "XCoreGenDisassemblerTables.inc" -static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) -{ + const MCDisassembler *Decoder) { if (RegNo > 11) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); @@ -207,11 +183,9 @@ return MCDisassembler::Success; } -static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, - unsigned RegNo, +static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) -{ + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); @@ -220,7 +194,8 @@ } static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { if (Val > 11) return MCDisassembler::Fail; static const unsigned Values[] = { @@ -231,7 +206,8 @@ } static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createImm(-(int64_t)Val)); return MCDisassembler::Success; } @@ -270,9 +246,9 @@ return MCDisassembler::Success; } -static DecodeStatus -Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { // Try and decode as a 3R instruction. unsigned Opcode = fieldFromInstruction(Insn, 11, 5); switch (Opcode) { @@ -340,9 +316,9 @@ return MCDisassembler::Fail; } -static DecodeStatus -Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -353,9 +329,9 @@ return S; } -static DecodeStatus -Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -366,9 +342,9 @@ return S; } -static DecodeStatus -DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); if (S != MCDisassembler::Success) @@ -379,9 +355,9 @@ return S; } -static DecodeStatus -Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -393,9 +369,9 @@ return S; } -static DecodeStatus -DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -406,9 +382,9 @@ return S; } -static DecodeStatus -DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -421,7 +397,7 @@ static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); if (S != MCDisassembler::Success) @@ -433,9 +409,9 @@ return S; } -static DecodeStatus -DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { // Try and decode as a L3R / L2RUS instruction. unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | fieldFromInstruction(Insn, 27, 5) << 4; @@ -504,9 +480,9 @@ return MCDisassembler::Fail; } -static DecodeStatus -DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2); @@ -518,9 +494,9 @@ return S; } -static DecodeStatus -DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2); @@ -532,9 +508,9 @@ return S; } -static DecodeStatus -Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { @@ -545,9 +521,9 @@ return S; } -static DecodeStatus -Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { @@ -558,9 +534,9 @@ return S; } -static DecodeStatus -Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { @@ -571,9 +547,9 @@ return S; } -static DecodeStatus -Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); if (S == MCDisassembler::Success) { @@ -584,9 +560,9 @@ return S; } -static DecodeStatus -DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -598,9 +574,9 @@ return S; } -static DecodeStatus -DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -613,9 +589,9 @@ return S; } -static DecodeStatus -DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -627,9 +603,9 @@ return S; } -static DecodeStatus -DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -641,9 +617,9 @@ return S; } -static DecodeStatus -DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5, Op6; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -661,9 +637,9 @@ return S; } -static DecodeStatus -DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { // Try and decode as a L6R instruction. Inst.clear(); unsigned Opcode = fieldFromInstruction(Insn, 27, 5); @@ -675,9 +651,9 @@ return MCDisassembler::Fail; } -static DecodeStatus -DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); @@ -695,9 +671,9 @@ return S; } -static DecodeStatus -DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; unsigned Op4 = fieldFromInstruction(Insn, 16, 4); DecodeStatus S = @@ -716,7 +692,7 @@ static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Op1, Op2, Op3; unsigned Op4 = fieldFromInstruction(Insn, 16, 4); DecodeStatus S = diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp --- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -969,8 +969,9 @@ OS.indent(Indentation) << "template \n"; OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S," << " unsigned Idx, InsnType insn, MCInst &MI,\n"; - OS.indent(Indentation) << " uint64_t " - << "Address, const void *Decoder, bool &DecodeComplete) {\n"; + OS.indent(Indentation) + << " uint64_t " + << "Address, const MCDisassembler *Decoder, bool &DecodeComplete) {\n"; Indentation += 2; OS.indent(Indentation) << "DecodeComplete = true;\n"; // TODO: When InsnType is large, using uint64_t limits all fields to 64 bits @@ -2221,7 +2222,7 @@ "MCInst &MI,\n" << " InsnType insn, uint64_t " "Address,\n" - << " const void *DisAsm,\n" + << " const MCDisassembler *DisAsm,\n" << " const MCSubtargetInfo &STI) {\n" << " const FeatureBitset &Bits = STI.getFeatureBits();\n" << "\n"