diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -226,16 +226,16 @@
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
def FPR16 : RegisterClass<"RISCV", [f16], 16, (add
- (sequence "F%u_H", 0, 7),
(sequence "F%u_H", 10, 17),
+ (sequence "F%u_H", 0, 7),
(sequence "F%u_H", 28, 31),
(sequence "F%u_H", 8, 9),
(sequence "F%u_H", 18, 27)
)>;
def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
- (sequence "F%u_F", 0, 7),
(sequence "F%u_F", 10, 17),
+ (sequence "F%u_F", 0, 7),
(sequence "F%u_F", 28, 31),
(sequence "F%u_F", 8, 9),
(sequence "F%u_F", 18, 27)
@@ -249,8 +249,8 @@
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
- (sequence "F%u_D", 0, 7),
(sequence "F%u_D", 10, 17),
+ (sequence "F%u_D", 0, 7),
(sequence "F%u_D", 28, 31),
(sequence "F%u_D", 8, 9),
(sequence "F%u_D", 18, 27)
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
@@ -24,23 +24,23 @@
; ILP32-LABEL: callee:
; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var)
-; ILP32-NEXT: flw ft0, %lo(var)(a0)
-; ILP32-NEXT: flw ft1, %lo(var+4)(a0)
-; ILP32-NEXT: flw ft2, %lo(var+8)(a0)
-; ILP32-NEXT: flw ft3, %lo(var+12)(a0)
+; ILP32-NEXT: flw fa0, %lo(var)(a0)
+; ILP32-NEXT: flw fa1, %lo(var+4)(a0)
+; ILP32-NEXT: flw fa2, %lo(var+8)(a0)
+; ILP32-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32-NEXT: addi a1, a0, %lo(var)
-; ILP32-NEXT: flw ft4, 16(a1)
-; ILP32-NEXT: flw ft5, 20(a1)
-; ILP32-NEXT: flw ft6, 24(a1)
-; ILP32-NEXT: flw ft7, 28(a1)
-; ILP32-NEXT: flw fa0, 32(a1)
-; ILP32-NEXT: flw fa1, 36(a1)
-; ILP32-NEXT: flw fa2, 40(a1)
-; ILP32-NEXT: flw fa3, 44(a1)
-; ILP32-NEXT: flw fa4, 48(a1)
-; ILP32-NEXT: flw fa5, 52(a1)
-; ILP32-NEXT: flw fa6, 56(a1)
-; ILP32-NEXT: flw fa7, 60(a1)
+; ILP32-NEXT: flw fa4, 16(a1)
+; ILP32-NEXT: flw fa5, 20(a1)
+; ILP32-NEXT: flw fa6, 24(a1)
+; ILP32-NEXT: flw fa7, 28(a1)
+; ILP32-NEXT: flw ft0, 32(a1)
+; ILP32-NEXT: flw ft1, 36(a1)
+; ILP32-NEXT: flw ft2, 40(a1)
+; ILP32-NEXT: flw ft3, 44(a1)
+; ILP32-NEXT: flw ft4, 48(a1)
+; ILP32-NEXT: flw ft5, 52(a1)
+; ILP32-NEXT: flw ft6, 56(a1)
+; ILP32-NEXT: flw ft7, 60(a1)
; ILP32-NEXT: flw ft8, 64(a1)
; ILP32-NEXT: flw ft9, 68(a1)
; ILP32-NEXT: flw ft10, 72(a1)
@@ -73,44 +73,44 @@
; ILP32-NEXT: fsw ft10, 72(a1)
; ILP32-NEXT: fsw ft9, 68(a1)
; ILP32-NEXT: fsw ft8, 64(a1)
-; ILP32-NEXT: fsw fa7, 60(a1)
-; ILP32-NEXT: fsw fa6, 56(a1)
-; ILP32-NEXT: fsw fa5, 52(a1)
-; ILP32-NEXT: fsw fa4, 48(a1)
-; ILP32-NEXT: fsw fa3, 44(a1)
-; ILP32-NEXT: fsw fa2, 40(a1)
-; ILP32-NEXT: fsw fa1, 36(a1)
-; ILP32-NEXT: fsw fa0, 32(a1)
-; ILP32-NEXT: fsw ft7, 28(a1)
-; ILP32-NEXT: fsw ft6, 24(a1)
-; ILP32-NEXT: fsw ft5, 20(a1)
-; ILP32-NEXT: fsw ft4, 16(a1)
-; ILP32-NEXT: fsw ft3, %lo(var+12)(a0)
-; ILP32-NEXT: fsw ft2, %lo(var+8)(a0)
-; ILP32-NEXT: fsw ft1, %lo(var+4)(a0)
-; ILP32-NEXT: fsw ft0, %lo(var)(a0)
+; ILP32-NEXT: fsw ft7, 60(a1)
+; ILP32-NEXT: fsw ft6, 56(a1)
+; ILP32-NEXT: fsw ft5, 52(a1)
+; ILP32-NEXT: fsw ft4, 48(a1)
+; ILP32-NEXT: fsw ft3, 44(a1)
+; ILP32-NEXT: fsw ft2, 40(a1)
+; ILP32-NEXT: fsw ft1, 36(a1)
+; ILP32-NEXT: fsw ft0, 32(a1)
+; ILP32-NEXT: fsw fa7, 28(a1)
+; ILP32-NEXT: fsw fa6, 24(a1)
+; ILP32-NEXT: fsw fa5, 20(a1)
+; ILP32-NEXT: fsw fa4, 16(a1)
+; ILP32-NEXT: fsw fa3, %lo(var+12)(a0)
+; ILP32-NEXT: fsw fa2, %lo(var+8)(a0)
+; ILP32-NEXT: fsw fa1, %lo(var+4)(a0)
+; ILP32-NEXT: fsw fa0, %lo(var)(a0)
; ILP32-NEXT: ret
;
; LP64-LABEL: callee:
; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var)
-; LP64-NEXT: flw ft0, %lo(var)(a0)
-; LP64-NEXT: flw ft1, %lo(var+4)(a0)
-; LP64-NEXT: flw ft2, %lo(var+8)(a0)
-; LP64-NEXT: flw ft3, %lo(var+12)(a0)
+; LP64-NEXT: flw fa0, %lo(var)(a0)
+; LP64-NEXT: flw fa1, %lo(var+4)(a0)
+; LP64-NEXT: flw fa2, %lo(var+8)(a0)
+; LP64-NEXT: flw fa3, %lo(var+12)(a0)
; LP64-NEXT: addi a1, a0, %lo(var)
-; LP64-NEXT: flw ft4, 16(a1)
-; LP64-NEXT: flw ft5, 20(a1)
-; LP64-NEXT: flw ft6, 24(a1)
-; LP64-NEXT: flw ft7, 28(a1)
-; LP64-NEXT: flw fa0, 32(a1)
-; LP64-NEXT: flw fa1, 36(a1)
-; LP64-NEXT: flw fa2, 40(a1)
-; LP64-NEXT: flw fa3, 44(a1)
-; LP64-NEXT: flw fa4, 48(a1)
-; LP64-NEXT: flw fa5, 52(a1)
-; LP64-NEXT: flw fa6, 56(a1)
-; LP64-NEXT: flw fa7, 60(a1)
+; LP64-NEXT: flw fa4, 16(a1)
+; LP64-NEXT: flw fa5, 20(a1)
+; LP64-NEXT: flw fa6, 24(a1)
+; LP64-NEXT: flw fa7, 28(a1)
+; LP64-NEXT: flw ft0, 32(a1)
+; LP64-NEXT: flw ft1, 36(a1)
+; LP64-NEXT: flw ft2, 40(a1)
+; LP64-NEXT: flw ft3, 44(a1)
+; LP64-NEXT: flw ft4, 48(a1)
+; LP64-NEXT: flw ft5, 52(a1)
+; LP64-NEXT: flw ft6, 56(a1)
+; LP64-NEXT: flw ft7, 60(a1)
; LP64-NEXT: flw ft8, 64(a1)
; LP64-NEXT: flw ft9, 68(a1)
; LP64-NEXT: flw ft10, 72(a1)
@@ -143,22 +143,22 @@
; LP64-NEXT: fsw ft10, 72(a1)
; LP64-NEXT: fsw ft9, 68(a1)
; LP64-NEXT: fsw ft8, 64(a1)
-; LP64-NEXT: fsw fa7, 60(a1)
-; LP64-NEXT: fsw fa6, 56(a1)
-; LP64-NEXT: fsw fa5, 52(a1)
-; LP64-NEXT: fsw fa4, 48(a1)
-; LP64-NEXT: fsw fa3, 44(a1)
-; LP64-NEXT: fsw fa2, 40(a1)
-; LP64-NEXT: fsw fa1, 36(a1)
-; LP64-NEXT: fsw fa0, 32(a1)
-; LP64-NEXT: fsw ft7, 28(a1)
-; LP64-NEXT: fsw ft6, 24(a1)
-; LP64-NEXT: fsw ft5, 20(a1)
-; LP64-NEXT: fsw ft4, 16(a1)
-; LP64-NEXT: fsw ft3, %lo(var+12)(a0)
-; LP64-NEXT: fsw ft2, %lo(var+8)(a0)
-; LP64-NEXT: fsw ft1, %lo(var+4)(a0)
-; LP64-NEXT: fsw ft0, %lo(var)(a0)
+; LP64-NEXT: fsw ft7, 60(a1)
+; LP64-NEXT: fsw ft6, 56(a1)
+; LP64-NEXT: fsw ft5, 52(a1)
+; LP64-NEXT: fsw ft4, 48(a1)
+; LP64-NEXT: fsw ft3, 44(a1)
+; LP64-NEXT: fsw ft2, 40(a1)
+; LP64-NEXT: fsw ft1, 36(a1)
+; LP64-NEXT: fsw ft0, 32(a1)
+; LP64-NEXT: fsw fa7, 28(a1)
+; LP64-NEXT: fsw fa6, 24(a1)
+; LP64-NEXT: fsw fa5, 20(a1)
+; LP64-NEXT: fsw fa4, 16(a1)
+; LP64-NEXT: fsw fa3, %lo(var+12)(a0)
+; LP64-NEXT: fsw fa2, %lo(var+8)(a0)
+; LP64-NEXT: fsw fa1, %lo(var+4)(a0)
+; LP64-NEXT: fsw fa0, %lo(var)(a0)
; LP64-NEXT: ret
;
; ILP32F-LABEL: callee:
@@ -177,23 +177,23 @@
; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui a0, %hi(var)
-; ILP32F-NEXT: flw ft0, %lo(var)(a0)
-; ILP32F-NEXT: flw ft1, %lo(var+4)(a0)
-; ILP32F-NEXT: flw ft2, %lo(var+8)(a0)
-; ILP32F-NEXT: flw ft3, %lo(var+12)(a0)
+; ILP32F-NEXT: flw fa0, %lo(var)(a0)
+; ILP32F-NEXT: flw fa1, %lo(var+4)(a0)
+; ILP32F-NEXT: flw fa2, %lo(var+8)(a0)
+; ILP32F-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32F-NEXT: addi a1, a0, %lo(var)
-; ILP32F-NEXT: flw ft4, 16(a1)
-; ILP32F-NEXT: flw ft5, 20(a1)
-; ILP32F-NEXT: flw ft6, 24(a1)
-; ILP32F-NEXT: flw ft7, 28(a1)
-; ILP32F-NEXT: flw fa0, 32(a1)
-; ILP32F-NEXT: flw fa1, 36(a1)
-; ILP32F-NEXT: flw fa2, 40(a1)
-; ILP32F-NEXT: flw fa3, 44(a1)
-; ILP32F-NEXT: flw fa4, 48(a1)
-; ILP32F-NEXT: flw fa5, 52(a1)
-; ILP32F-NEXT: flw fa6, 56(a1)
-; ILP32F-NEXT: flw fa7, 60(a1)
+; ILP32F-NEXT: flw fa4, 16(a1)
+; ILP32F-NEXT: flw fa5, 20(a1)
+; ILP32F-NEXT: flw fa6, 24(a1)
+; ILP32F-NEXT: flw fa7, 28(a1)
+; ILP32F-NEXT: flw ft0, 32(a1)
+; ILP32F-NEXT: flw ft1, 36(a1)
+; ILP32F-NEXT: flw ft2, 40(a1)
+; ILP32F-NEXT: flw ft3, 44(a1)
+; ILP32F-NEXT: flw ft4, 48(a1)
+; ILP32F-NEXT: flw ft5, 52(a1)
+; ILP32F-NEXT: flw ft6, 56(a1)
+; ILP32F-NEXT: flw ft7, 60(a1)
; ILP32F-NEXT: flw ft8, 64(a1)
; ILP32F-NEXT: flw ft9, 68(a1)
; ILP32F-NEXT: flw ft10, 72(a1)
@@ -226,22 +226,22 @@
; ILP32F-NEXT: fsw ft10, 72(a1)
; ILP32F-NEXT: fsw ft9, 68(a1)
; ILP32F-NEXT: fsw ft8, 64(a1)
-; ILP32F-NEXT: fsw fa7, 60(a1)
-; ILP32F-NEXT: fsw fa6, 56(a1)
-; ILP32F-NEXT: fsw fa5, 52(a1)
-; ILP32F-NEXT: fsw fa4, 48(a1)
-; ILP32F-NEXT: fsw fa3, 44(a1)
-; ILP32F-NEXT: fsw fa2, 40(a1)
-; ILP32F-NEXT: fsw fa1, 36(a1)
-; ILP32F-NEXT: fsw fa0, 32(a1)
-; ILP32F-NEXT: fsw ft7, 28(a1)
-; ILP32F-NEXT: fsw ft6, 24(a1)
-; ILP32F-NEXT: fsw ft5, 20(a1)
-; ILP32F-NEXT: fsw ft4, 16(a1)
-; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0)
-; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0)
-; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0)
-; ILP32F-NEXT: fsw ft0, %lo(var)(a0)
+; ILP32F-NEXT: fsw ft7, 60(a1)
+; ILP32F-NEXT: fsw ft6, 56(a1)
+; ILP32F-NEXT: fsw ft5, 52(a1)
+; ILP32F-NEXT: fsw ft4, 48(a1)
+; ILP32F-NEXT: fsw ft3, 44(a1)
+; ILP32F-NEXT: fsw ft2, 40(a1)
+; ILP32F-NEXT: fsw ft1, 36(a1)
+; ILP32F-NEXT: fsw ft0, 32(a1)
+; ILP32F-NEXT: fsw fa7, 28(a1)
+; ILP32F-NEXT: fsw fa6, 24(a1)
+; ILP32F-NEXT: fsw fa5, 20(a1)
+; ILP32F-NEXT: fsw fa4, 16(a1)
+; ILP32F-NEXT: fsw fa3, %lo(var+12)(a0)
+; ILP32F-NEXT: fsw fa2, %lo(var+8)(a0)
+; ILP32F-NEXT: fsw fa1, %lo(var+4)(a0)
+; ILP32F-NEXT: fsw fa0, %lo(var)(a0)
; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
@@ -273,23 +273,23 @@
; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui a0, %hi(var)
-; LP64F-NEXT: flw ft0, %lo(var)(a0)
-; LP64F-NEXT: flw ft1, %lo(var+4)(a0)
-; LP64F-NEXT: flw ft2, %lo(var+8)(a0)
-; LP64F-NEXT: flw ft3, %lo(var+12)(a0)
+; LP64F-NEXT: flw fa0, %lo(var)(a0)
+; LP64F-NEXT: flw fa1, %lo(var+4)(a0)
+; LP64F-NEXT: flw fa2, %lo(var+8)(a0)
+; LP64F-NEXT: flw fa3, %lo(var+12)(a0)
; LP64F-NEXT: addi a1, a0, %lo(var)
-; LP64F-NEXT: flw ft4, 16(a1)
-; LP64F-NEXT: flw ft5, 20(a1)
-; LP64F-NEXT: flw ft6, 24(a1)
-; LP64F-NEXT: flw ft7, 28(a1)
-; LP64F-NEXT: flw fa0, 32(a1)
-; LP64F-NEXT: flw fa1, 36(a1)
-; LP64F-NEXT: flw fa2, 40(a1)
-; LP64F-NEXT: flw fa3, 44(a1)
-; LP64F-NEXT: flw fa4, 48(a1)
-; LP64F-NEXT: flw fa5, 52(a1)
-; LP64F-NEXT: flw fa6, 56(a1)
-; LP64F-NEXT: flw fa7, 60(a1)
+; LP64F-NEXT: flw fa4, 16(a1)
+; LP64F-NEXT: flw fa5, 20(a1)
+; LP64F-NEXT: flw fa6, 24(a1)
+; LP64F-NEXT: flw fa7, 28(a1)
+; LP64F-NEXT: flw ft0, 32(a1)
+; LP64F-NEXT: flw ft1, 36(a1)
+; LP64F-NEXT: flw ft2, 40(a1)
+; LP64F-NEXT: flw ft3, 44(a1)
+; LP64F-NEXT: flw ft4, 48(a1)
+; LP64F-NEXT: flw ft5, 52(a1)
+; LP64F-NEXT: flw ft6, 56(a1)
+; LP64F-NEXT: flw ft7, 60(a1)
; LP64F-NEXT: flw ft8, 64(a1)
; LP64F-NEXT: flw ft9, 68(a1)
; LP64F-NEXT: flw ft10, 72(a1)
@@ -322,22 +322,22 @@
; LP64F-NEXT: fsw ft10, 72(a1)
; LP64F-NEXT: fsw ft9, 68(a1)
; LP64F-NEXT: fsw ft8, 64(a1)
-; LP64F-NEXT: fsw fa7, 60(a1)
-; LP64F-NEXT: fsw fa6, 56(a1)
-; LP64F-NEXT: fsw fa5, 52(a1)
-; LP64F-NEXT: fsw fa4, 48(a1)
-; LP64F-NEXT: fsw fa3, 44(a1)
-; LP64F-NEXT: fsw fa2, 40(a1)
-; LP64F-NEXT: fsw fa1, 36(a1)
-; LP64F-NEXT: fsw fa0, 32(a1)
-; LP64F-NEXT: fsw ft7, 28(a1)
-; LP64F-NEXT: fsw ft6, 24(a1)
-; LP64F-NEXT: fsw ft5, 20(a1)
-; LP64F-NEXT: fsw ft4, 16(a1)
-; LP64F-NEXT: fsw ft3, %lo(var+12)(a0)
-; LP64F-NEXT: fsw ft2, %lo(var+8)(a0)
-; LP64F-NEXT: fsw ft1, %lo(var+4)(a0)
-; LP64F-NEXT: fsw ft0, %lo(var)(a0)
+; LP64F-NEXT: fsw ft7, 60(a1)
+; LP64F-NEXT: fsw ft6, 56(a1)
+; LP64F-NEXT: fsw ft5, 52(a1)
+; LP64F-NEXT: fsw ft4, 48(a1)
+; LP64F-NEXT: fsw ft3, 44(a1)
+; LP64F-NEXT: fsw ft2, 40(a1)
+; LP64F-NEXT: fsw ft1, 36(a1)
+; LP64F-NEXT: fsw ft0, 32(a1)
+; LP64F-NEXT: fsw fa7, 28(a1)
+; LP64F-NEXT: fsw fa6, 24(a1)
+; LP64F-NEXT: fsw fa5, 20(a1)
+; LP64F-NEXT: fsw fa4, 16(a1)
+; LP64F-NEXT: fsw fa3, %lo(var+12)(a0)
+; LP64F-NEXT: fsw fa2, %lo(var+8)(a0)
+; LP64F-NEXT: fsw fa1, %lo(var+4)(a0)
+; LP64F-NEXT: fsw fa0, %lo(var)(a0)
; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
@@ -369,23 +369,23 @@
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var)
-; ILP32D-NEXT: flw ft0, %lo(var)(a0)
-; ILP32D-NEXT: flw ft1, %lo(var+4)(a0)
-; ILP32D-NEXT: flw ft2, %lo(var+8)(a0)
-; ILP32D-NEXT: flw ft3, %lo(var+12)(a0)
+; ILP32D-NEXT: flw fa0, %lo(var)(a0)
+; ILP32D-NEXT: flw fa1, %lo(var+4)(a0)
+; ILP32D-NEXT: flw fa2, %lo(var+8)(a0)
+; ILP32D-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var)
-; ILP32D-NEXT: flw ft4, 16(a1)
-; ILP32D-NEXT: flw ft5, 20(a1)
-; ILP32D-NEXT: flw ft6, 24(a1)
-; ILP32D-NEXT: flw ft7, 28(a1)
-; ILP32D-NEXT: flw fa0, 32(a1)
-; ILP32D-NEXT: flw fa1, 36(a1)
-; ILP32D-NEXT: flw fa2, 40(a1)
-; ILP32D-NEXT: flw fa3, 44(a1)
-; ILP32D-NEXT: flw fa4, 48(a1)
-; ILP32D-NEXT: flw fa5, 52(a1)
-; ILP32D-NEXT: flw fa6, 56(a1)
-; ILP32D-NEXT: flw fa7, 60(a1)
+; ILP32D-NEXT: flw fa4, 16(a1)
+; ILP32D-NEXT: flw fa5, 20(a1)
+; ILP32D-NEXT: flw fa6, 24(a1)
+; ILP32D-NEXT: flw fa7, 28(a1)
+; ILP32D-NEXT: flw ft0, 32(a1)
+; ILP32D-NEXT: flw ft1, 36(a1)
+; ILP32D-NEXT: flw ft2, 40(a1)
+; ILP32D-NEXT: flw ft3, 44(a1)
+; ILP32D-NEXT: flw ft4, 48(a1)
+; ILP32D-NEXT: flw ft5, 52(a1)
+; ILP32D-NEXT: flw ft6, 56(a1)
+; ILP32D-NEXT: flw ft7, 60(a1)
; ILP32D-NEXT: flw ft8, 64(a1)
; ILP32D-NEXT: flw ft9, 68(a1)
; ILP32D-NEXT: flw ft10, 72(a1)
@@ -418,22 +418,22 @@
; ILP32D-NEXT: fsw ft10, 72(a1)
; ILP32D-NEXT: fsw ft9, 68(a1)
; ILP32D-NEXT: fsw ft8, 64(a1)
-; ILP32D-NEXT: fsw fa7, 60(a1)
-; ILP32D-NEXT: fsw fa6, 56(a1)
-; ILP32D-NEXT: fsw fa5, 52(a1)
-; ILP32D-NEXT: fsw fa4, 48(a1)
-; ILP32D-NEXT: fsw fa3, 44(a1)
-; ILP32D-NEXT: fsw fa2, 40(a1)
-; ILP32D-NEXT: fsw fa1, 36(a1)
-; ILP32D-NEXT: fsw fa0, 32(a1)
-; ILP32D-NEXT: fsw ft7, 28(a1)
-; ILP32D-NEXT: fsw ft6, 24(a1)
-; ILP32D-NEXT: fsw ft5, 20(a1)
-; ILP32D-NEXT: fsw ft4, 16(a1)
-; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0)
-; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0)
-; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0)
-; ILP32D-NEXT: fsw ft0, %lo(var)(a0)
+; ILP32D-NEXT: fsw ft7, 60(a1)
+; ILP32D-NEXT: fsw ft6, 56(a1)
+; ILP32D-NEXT: fsw ft5, 52(a1)
+; ILP32D-NEXT: fsw ft4, 48(a1)
+; ILP32D-NEXT: fsw ft3, 44(a1)
+; ILP32D-NEXT: fsw ft2, 40(a1)
+; ILP32D-NEXT: fsw ft1, 36(a1)
+; ILP32D-NEXT: fsw ft0, 32(a1)
+; ILP32D-NEXT: fsw fa7, 28(a1)
+; ILP32D-NEXT: fsw fa6, 24(a1)
+; ILP32D-NEXT: fsw fa5, 20(a1)
+; ILP32D-NEXT: fsw fa4, 16(a1)
+; ILP32D-NEXT: fsw fa3, %lo(var+12)(a0)
+; ILP32D-NEXT: fsw fa2, %lo(var+8)(a0)
+; ILP32D-NEXT: fsw fa1, %lo(var+4)(a0)
+; ILP32D-NEXT: fsw fa0, %lo(var)(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -465,23 +465,23 @@
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var)
-; LP64D-NEXT: flw ft0, %lo(var)(a0)
-; LP64D-NEXT: flw ft1, %lo(var+4)(a0)
-; LP64D-NEXT: flw ft2, %lo(var+8)(a0)
-; LP64D-NEXT: flw ft3, %lo(var+12)(a0)
+; LP64D-NEXT: flw fa0, %lo(var)(a0)
+; LP64D-NEXT: flw fa1, %lo(var+4)(a0)
+; LP64D-NEXT: flw fa2, %lo(var+8)(a0)
+; LP64D-NEXT: flw fa3, %lo(var+12)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var)
-; LP64D-NEXT: flw ft4, 16(a1)
-; LP64D-NEXT: flw ft5, 20(a1)
-; LP64D-NEXT: flw ft6, 24(a1)
-; LP64D-NEXT: flw ft7, 28(a1)
-; LP64D-NEXT: flw fa0, 32(a1)
-; LP64D-NEXT: flw fa1, 36(a1)
-; LP64D-NEXT: flw fa2, 40(a1)
-; LP64D-NEXT: flw fa3, 44(a1)
-; LP64D-NEXT: flw fa4, 48(a1)
-; LP64D-NEXT: flw fa5, 52(a1)
-; LP64D-NEXT: flw fa6, 56(a1)
-; LP64D-NEXT: flw fa7, 60(a1)
+; LP64D-NEXT: flw fa4, 16(a1)
+; LP64D-NEXT: flw fa5, 20(a1)
+; LP64D-NEXT: flw fa6, 24(a1)
+; LP64D-NEXT: flw fa7, 28(a1)
+; LP64D-NEXT: flw ft0, 32(a1)
+; LP64D-NEXT: flw ft1, 36(a1)
+; LP64D-NEXT: flw ft2, 40(a1)
+; LP64D-NEXT: flw ft3, 44(a1)
+; LP64D-NEXT: flw ft4, 48(a1)
+; LP64D-NEXT: flw ft5, 52(a1)
+; LP64D-NEXT: flw ft6, 56(a1)
+; LP64D-NEXT: flw ft7, 60(a1)
; LP64D-NEXT: flw ft8, 64(a1)
; LP64D-NEXT: flw ft9, 68(a1)
; LP64D-NEXT: flw ft10, 72(a1)
@@ -514,22 +514,22 @@
; LP64D-NEXT: fsw ft10, 72(a1)
; LP64D-NEXT: fsw ft9, 68(a1)
; LP64D-NEXT: fsw ft8, 64(a1)
-; LP64D-NEXT: fsw fa7, 60(a1)
-; LP64D-NEXT: fsw fa6, 56(a1)
-; LP64D-NEXT: fsw fa5, 52(a1)
-; LP64D-NEXT: fsw fa4, 48(a1)
-; LP64D-NEXT: fsw fa3, 44(a1)
-; LP64D-NEXT: fsw fa2, 40(a1)
-; LP64D-NEXT: fsw fa1, 36(a1)
-; LP64D-NEXT: fsw fa0, 32(a1)
-; LP64D-NEXT: fsw ft7, 28(a1)
-; LP64D-NEXT: fsw ft6, 24(a1)
-; LP64D-NEXT: fsw ft5, 20(a1)
-; LP64D-NEXT: fsw ft4, 16(a1)
-; LP64D-NEXT: fsw ft3, %lo(var+12)(a0)
-; LP64D-NEXT: fsw ft2, %lo(var+8)(a0)
-; LP64D-NEXT: fsw ft1, %lo(var+4)(a0)
-; LP64D-NEXT: fsw ft0, %lo(var)(a0)
+; LP64D-NEXT: fsw ft7, 60(a1)
+; LP64D-NEXT: fsw ft6, 56(a1)
+; LP64D-NEXT: fsw ft5, 52(a1)
+; LP64D-NEXT: fsw ft4, 48(a1)
+; LP64D-NEXT: fsw ft3, 44(a1)
+; LP64D-NEXT: fsw ft2, 40(a1)
+; LP64D-NEXT: fsw ft1, 36(a1)
+; LP64D-NEXT: fsw ft0, 32(a1)
+; LP64D-NEXT: fsw fa7, 28(a1)
+; LP64D-NEXT: fsw fa6, 24(a1)
+; LP64D-NEXT: fsw fa5, 20(a1)
+; LP64D-NEXT: fsw fa4, 16(a1)
+; LP64D-NEXT: fsw fa3, %lo(var+12)(a0)
+; LP64D-NEXT: fsw fa2, %lo(var+8)(a0)
+; LP64D-NEXT: fsw fa1, %lo(var+4)(a0)
+; LP64D-NEXT: fsw fa0, %lo(var)(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -564,136 +564,136 @@
; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var)
-; ILP32-NEXT: flw ft0, %lo(var)(s0)
-; ILP32-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, %lo(var+4)(s0)
-; ILP32-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, %lo(var+8)(s0)
-; ILP32-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, %lo(var+12)(s0)
-; ILP32-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, %lo(var)(s0)
+; ILP32-NEXT: fsw fa0, 128(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, %lo(var+4)(s0)
+; ILP32-NEXT: fsw fa0, 124(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, %lo(var+8)(s0)
+; ILP32-NEXT: fsw fa0, 120(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, %lo(var+12)(s0)
+; ILP32-NEXT: fsw fa0, 116(sp) # 4-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var)
-; ILP32-NEXT: flw ft0, 16(s1)
-; ILP32-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 20(s1)
-; ILP32-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 24(s1)
-; ILP32-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 28(s1)
-; ILP32-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 32(s1)
-; ILP32-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 36(s1)
-; ILP32-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 40(s1)
-; ILP32-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 44(s1)
-; ILP32-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 48(s1)
-; ILP32-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 52(s1)
-; ILP32-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 56(s1)
-; ILP32-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 60(s1)
-; ILP32-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 64(s1)
-; ILP32-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 68(s1)
-; ILP32-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 72(s1)
-; ILP32-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 76(s1)
-; ILP32-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 80(s1)
-; ILP32-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 84(s1)
-; ILP32-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 88(s1)
-; ILP32-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 92(s1)
-; ILP32-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 96(s1)
-; ILP32-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 100(s1)
-; ILP32-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 104(s1)
-; ILP32-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 108(s1)
-; ILP32-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 112(s1)
-; ILP32-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 116(s1)
-; ILP32-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 120(s1)
-; ILP32-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw ft0, 124(s1)
-; ILP32-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 16(s1)
+; ILP32-NEXT: fsw fa0, 112(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 20(s1)
+; ILP32-NEXT: fsw fa0, 108(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 24(s1)
+; ILP32-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 28(s1)
+; ILP32-NEXT: fsw fa0, 100(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 32(s1)
+; ILP32-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 36(s1)
+; ILP32-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 40(s1)
+; ILP32-NEXT: fsw fa0, 88(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 44(s1)
+; ILP32-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 48(s1)
+; ILP32-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 52(s1)
+; ILP32-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 56(s1)
+; ILP32-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 60(s1)
+; ILP32-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 64(s1)
+; ILP32-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 68(s1)
+; ILP32-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 72(s1)
+; ILP32-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 76(s1)
+; ILP32-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 80(s1)
+; ILP32-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 84(s1)
+; ILP32-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 88(s1)
+; ILP32-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 92(s1)
+; ILP32-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 96(s1)
+; ILP32-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 100(s1)
+; ILP32-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 104(s1)
+; ILP32-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 108(s1)
+; ILP32-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 112(s1)
+; ILP32-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 116(s1)
+; ILP32-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 120(s1)
+; ILP32-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa0, 124(s1)
+; ILP32-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
; ILP32-NEXT: call callee@plt
-; ILP32-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 124(s1)
-; ILP32-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 120(s1)
-; ILP32-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 116(s1)
-; ILP32-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 112(s1)
-; ILP32-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 108(s1)
-; ILP32-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 104(s1)
-; ILP32-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 100(s1)
-; ILP32-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 96(s1)
-; ILP32-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 92(s1)
-; ILP32-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 88(s1)
-; ILP32-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 84(s1)
-; ILP32-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 80(s1)
-; ILP32-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 76(s1)
-; ILP32-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 72(s1)
-; ILP32-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 68(s1)
-; ILP32-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 64(s1)
-; ILP32-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 60(s1)
-; ILP32-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 56(s1)
-; ILP32-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 52(s1)
-; ILP32-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 48(s1)
-; ILP32-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 44(s1)
-; ILP32-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 40(s1)
-; ILP32-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 36(s1)
-; ILP32-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 32(s1)
-; ILP32-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 28(s1)
-; ILP32-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 24(s1)
-; ILP32-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 20(s1)
-; ILP32-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, 16(s1)
-; ILP32-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, %lo(var+12)(s0)
-; ILP32-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, %lo(var+8)(s0)
-; ILP32-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, %lo(var+4)(s0)
-; ILP32-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw ft0, %lo(var)(s0)
+; ILP32-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 124(s1)
+; ILP32-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 120(s1)
+; ILP32-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 116(s1)
+; ILP32-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 112(s1)
+; ILP32-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 108(s1)
+; ILP32-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 104(s1)
+; ILP32-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 100(s1)
+; ILP32-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 96(s1)
+; ILP32-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 92(s1)
+; ILP32-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 88(s1)
+; ILP32-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 84(s1)
+; ILP32-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 80(s1)
+; ILP32-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 76(s1)
+; ILP32-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 72(s1)
+; ILP32-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 68(s1)
+; ILP32-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 64(s1)
+; ILP32-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 60(s1)
+; ILP32-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 56(s1)
+; ILP32-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 52(s1)
+; ILP32-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 48(s1)
+; ILP32-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 44(s1)
+; ILP32-NEXT: flw fa0, 88(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 40(s1)
+; ILP32-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 36(s1)
+; ILP32-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 32(s1)
+; ILP32-NEXT: flw fa0, 100(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 28(s1)
+; ILP32-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 24(s1)
+; ILP32-NEXT: flw fa0, 108(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 20(s1)
+; ILP32-NEXT: flw fa0, 112(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, 16(s1)
+; ILP32-NEXT: flw fa0, 116(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, %lo(var+12)(s0)
+; ILP32-NEXT: flw fa0, 120(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, %lo(var+8)(s0)
+; ILP32-NEXT: flw fa0, 124(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, %lo(var+4)(s0)
+; ILP32-NEXT: flw fa0, 128(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa0, %lo(var)(s0)
; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
@@ -707,136 +707,136 @@
; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var)
-; LP64-NEXT: flw ft0, %lo(var)(s0)
-; LP64-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, %lo(var+4)(s0)
-; LP64-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, %lo(var+8)(s0)
-; LP64-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, %lo(var+12)(s0)
-; LP64-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, %lo(var)(s0)
+; LP64-NEXT: fsw fa0, 132(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, %lo(var+4)(s0)
+; LP64-NEXT: fsw fa0, 128(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, %lo(var+8)(s0)
+; LP64-NEXT: fsw fa0, 124(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, %lo(var+12)(s0)
+; LP64-NEXT: fsw fa0, 120(sp) # 4-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var)
-; LP64-NEXT: flw ft0, 16(s1)
-; LP64-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 20(s1)
-; LP64-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 24(s1)
-; LP64-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 28(s1)
-; LP64-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 32(s1)
-; LP64-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 36(s1)
-; LP64-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 40(s1)
-; LP64-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 44(s1)
-; LP64-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 48(s1)
-; LP64-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 52(s1)
-; LP64-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 56(s1)
-; LP64-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 60(s1)
-; LP64-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 64(s1)
-; LP64-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 68(s1)
-; LP64-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 72(s1)
-; LP64-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 76(s1)
-; LP64-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 80(s1)
-; LP64-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 84(s1)
-; LP64-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 88(s1)
-; LP64-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 92(s1)
-; LP64-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 96(s1)
-; LP64-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 100(s1)
-; LP64-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 104(s1)
-; LP64-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 108(s1)
-; LP64-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 112(s1)
-; LP64-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 116(s1)
-; LP64-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 120(s1)
-; LP64-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw ft0, 124(s1)
-; LP64-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 16(s1)
+; LP64-NEXT: fsw fa0, 116(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 20(s1)
+; LP64-NEXT: fsw fa0, 112(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 24(s1)
+; LP64-NEXT: fsw fa0, 108(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 28(s1)
+; LP64-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 32(s1)
+; LP64-NEXT: fsw fa0, 100(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 36(s1)
+; LP64-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 40(s1)
+; LP64-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 44(s1)
+; LP64-NEXT: fsw fa0, 88(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 48(s1)
+; LP64-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 52(s1)
+; LP64-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 56(s1)
+; LP64-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 60(s1)
+; LP64-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 64(s1)
+; LP64-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 68(s1)
+; LP64-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 72(s1)
+; LP64-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 76(s1)
+; LP64-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 80(s1)
+; LP64-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 84(s1)
+; LP64-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 88(s1)
+; LP64-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 92(s1)
+; LP64-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 96(s1)
+; LP64-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 100(s1)
+; LP64-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 104(s1)
+; LP64-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 108(s1)
+; LP64-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 112(s1)
+; LP64-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 116(s1)
+; LP64-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 120(s1)
+; LP64-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa0, 124(s1)
+; LP64-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64-NEXT: call callee@plt
-; LP64-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 124(s1)
-; LP64-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 120(s1)
-; LP64-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 116(s1)
-; LP64-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 112(s1)
-; LP64-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 108(s1)
-; LP64-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 104(s1)
-; LP64-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 100(s1)
-; LP64-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 96(s1)
-; LP64-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 92(s1)
-; LP64-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 88(s1)
-; LP64-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 84(s1)
-; LP64-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 80(s1)
-; LP64-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 76(s1)
-; LP64-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 72(s1)
-; LP64-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 68(s1)
-; LP64-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 64(s1)
-; LP64-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 60(s1)
-; LP64-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 56(s1)
-; LP64-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 52(s1)
-; LP64-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 48(s1)
-; LP64-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 44(s1)
-; LP64-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 40(s1)
-; LP64-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 36(s1)
-; LP64-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 32(s1)
-; LP64-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 28(s1)
-; LP64-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 24(s1)
-; LP64-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 20(s1)
-; LP64-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, 16(s1)
-; LP64-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, %lo(var+12)(s0)
-; LP64-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, %lo(var+8)(s0)
-; LP64-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, %lo(var+4)(s0)
-; LP64-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw ft0, %lo(var)(s0)
+; LP64-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 124(s1)
+; LP64-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 120(s1)
+; LP64-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 116(s1)
+; LP64-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 112(s1)
+; LP64-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 108(s1)
+; LP64-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 104(s1)
+; LP64-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 100(s1)
+; LP64-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 96(s1)
+; LP64-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 92(s1)
+; LP64-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 88(s1)
+; LP64-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 84(s1)
+; LP64-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 80(s1)
+; LP64-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 76(s1)
+; LP64-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 72(s1)
+; LP64-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 68(s1)
+; LP64-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 64(s1)
+; LP64-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 60(s1)
+; LP64-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 56(s1)
+; LP64-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 52(s1)
+; LP64-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 48(s1)
+; LP64-NEXT: flw fa0, 88(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 44(s1)
+; LP64-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 40(s1)
+; LP64-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 36(s1)
+; LP64-NEXT: flw fa0, 100(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 32(s1)
+; LP64-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 28(s1)
+; LP64-NEXT: flw fa0, 108(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 24(s1)
+; LP64-NEXT: flw fa0, 112(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 20(s1)
+; LP64-NEXT: flw fa0, 116(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, 16(s1)
+; LP64-NEXT: flw fa0, 120(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, %lo(var+12)(s0)
+; LP64-NEXT: flw fa0, 124(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, %lo(var+8)(s0)
+; LP64-NEXT: flw fa0, 128(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, %lo(var+4)(s0)
+; LP64-NEXT: flw fa0, 132(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa0, %lo(var)(s0)
; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
@@ -862,47 +862,47 @@
; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui s0, %hi(var)
-; ILP32F-NEXT: flw ft0, %lo(var)(s0)
-; ILP32F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, %lo(var+4)(s0)
-; ILP32F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, %lo(var+8)(s0)
-; ILP32F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, %lo(var+12)(s0)
-; ILP32F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, %lo(var)(s0)
+; ILP32F-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, %lo(var+4)(s0)
+; ILP32F-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, %lo(var+8)(s0)
+; ILP32F-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, %lo(var+12)(s0)
+; ILP32F-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; ILP32F-NEXT: addi s1, s0, %lo(var)
-; ILP32F-NEXT: flw ft0, 16(s1)
-; ILP32F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 20(s1)
-; ILP32F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 24(s1)
-; ILP32F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 28(s1)
-; ILP32F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 32(s1)
-; ILP32F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 36(s1)
-; ILP32F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 40(s1)
-; ILP32F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 44(s1)
-; ILP32F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 48(s1)
-; ILP32F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 52(s1)
-; ILP32F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 56(s1)
-; ILP32F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 60(s1)
-; ILP32F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 64(s1)
-; ILP32F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 68(s1)
-; ILP32F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 72(s1)
-; ILP32F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw ft0, 76(s1)
-; ILP32F-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 16(s1)
+; ILP32F-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 20(s1)
+; ILP32F-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 24(s1)
+; ILP32F-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 28(s1)
+; ILP32F-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 32(s1)
+; ILP32F-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 36(s1)
+; ILP32F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 40(s1)
+; ILP32F-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 44(s1)
+; ILP32F-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 48(s1)
+; ILP32F-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 52(s1)
+; ILP32F-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 56(s1)
+; ILP32F-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 60(s1)
+; ILP32F-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 64(s1)
+; ILP32F-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 68(s1)
+; ILP32F-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 72(s1)
+; ILP32F-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa0, 76(s1)
+; ILP32F-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw fs8, 80(s1)
; ILP32F-NEXT: flw fs9, 84(s1)
; ILP32F-NEXT: flw fs10, 88(s1)
@@ -928,46 +928,46 @@
; ILP32F-NEXT: fsw fs10, 88(s1)
; ILP32F-NEXT: fsw fs9, 84(s1)
; ILP32F-NEXT: fsw fs8, 80(s1)
-; ILP32F-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 76(s1)
-; ILP32F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 72(s1)
-; ILP32F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 68(s1)
-; ILP32F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 64(s1)
-; ILP32F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 60(s1)
-; ILP32F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 56(s1)
-; ILP32F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 52(s1)
-; ILP32F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 48(s1)
-; ILP32F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 44(s1)
-; ILP32F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 40(s1)
-; ILP32F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 36(s1)
-; ILP32F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 32(s1)
-; ILP32F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 28(s1)
-; ILP32F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 24(s1)
-; ILP32F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 20(s1)
-; ILP32F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, 16(s1)
-; ILP32F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, %lo(var+12)(s0)
-; ILP32F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, %lo(var+8)(s0)
-; ILP32F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0)
-; ILP32F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw ft0, %lo(var)(s0)
+; ILP32F-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 76(s1)
+; ILP32F-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 72(s1)
+; ILP32F-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 68(s1)
+; ILP32F-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 64(s1)
+; ILP32F-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 60(s1)
+; ILP32F-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 56(s1)
+; ILP32F-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 52(s1)
+; ILP32F-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 48(s1)
+; ILP32F-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 44(s1)
+; ILP32F-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 40(s1)
+; ILP32F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 36(s1)
+; ILP32F-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 32(s1)
+; ILP32F-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 28(s1)
+; ILP32F-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 24(s1)
+; ILP32F-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 20(s1)
+; ILP32F-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, 16(s1)
+; ILP32F-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, %lo(var+12)(s0)
+; ILP32F-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, %lo(var+8)(s0)
+; ILP32F-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, %lo(var+4)(s0)
+; ILP32F-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa0, %lo(var)(s0)
; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
@@ -1005,47 +1005,47 @@
; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui s0, %hi(var)
-; LP64F-NEXT: flw ft0, %lo(var)(s0)
-; LP64F-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, %lo(var+4)(s0)
-; LP64F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, %lo(var+8)(s0)
-; LP64F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, %lo(var+12)(s0)
-; LP64F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, %lo(var)(s0)
+; LP64F-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, %lo(var+4)(s0)
+; LP64F-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, %lo(var+8)(s0)
+; LP64F-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, %lo(var+12)(s0)
+; LP64F-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; LP64F-NEXT: addi s1, s0, %lo(var)
-; LP64F-NEXT: flw ft0, 16(s1)
-; LP64F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 20(s1)
-; LP64F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 24(s1)
-; LP64F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 28(s1)
-; LP64F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 32(s1)
-; LP64F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 36(s1)
-; LP64F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 40(s1)
-; LP64F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 44(s1)
-; LP64F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 48(s1)
-; LP64F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 52(s1)
-; LP64F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 56(s1)
-; LP64F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 60(s1)
-; LP64F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 64(s1)
-; LP64F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 68(s1)
-; LP64F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 72(s1)
-; LP64F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw ft0, 76(s1)
-; LP64F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 16(s1)
+; LP64F-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 20(s1)
+; LP64F-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 24(s1)
+; LP64F-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 28(s1)
+; LP64F-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 32(s1)
+; LP64F-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 36(s1)
+; LP64F-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 40(s1)
+; LP64F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 44(s1)
+; LP64F-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 48(s1)
+; LP64F-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 52(s1)
+; LP64F-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 56(s1)
+; LP64F-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 60(s1)
+; LP64F-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 64(s1)
+; LP64F-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 68(s1)
+; LP64F-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 72(s1)
+; LP64F-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa0, 76(s1)
+; LP64F-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw fs8, 80(s1)
; LP64F-NEXT: flw fs9, 84(s1)
; LP64F-NEXT: flw fs10, 88(s1)
@@ -1071,46 +1071,46 @@
; LP64F-NEXT: fsw fs10, 88(s1)
; LP64F-NEXT: fsw fs9, 84(s1)
; LP64F-NEXT: fsw fs8, 80(s1)
-; LP64F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 76(s1)
-; LP64F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 72(s1)
-; LP64F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 68(s1)
-; LP64F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 64(s1)
-; LP64F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 60(s1)
-; LP64F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 56(s1)
-; LP64F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 52(s1)
-; LP64F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 48(s1)
-; LP64F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 44(s1)
-; LP64F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 40(s1)
-; LP64F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 36(s1)
-; LP64F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 32(s1)
-; LP64F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 28(s1)
-; LP64F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 24(s1)
-; LP64F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 20(s1)
-; LP64F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, 16(s1)
-; LP64F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, %lo(var+12)(s0)
-; LP64F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, %lo(var+8)(s0)
-; LP64F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, %lo(var+4)(s0)
-; LP64F-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw ft0, %lo(var)(s0)
+; LP64F-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 76(s1)
+; LP64F-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 72(s1)
+; LP64F-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 68(s1)
+; LP64F-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 64(s1)
+; LP64F-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 60(s1)
+; LP64F-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 56(s1)
+; LP64F-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 52(s1)
+; LP64F-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 48(s1)
+; LP64F-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 44(s1)
+; LP64F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 40(s1)
+; LP64F-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 36(s1)
+; LP64F-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 32(s1)
+; LP64F-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 28(s1)
+; LP64F-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 24(s1)
+; LP64F-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 20(s1)
+; LP64F-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, 16(s1)
+; LP64F-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, %lo(var+12)(s0)
+; LP64F-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, %lo(var+8)(s0)
+; LP64F-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, %lo(var+4)(s0)
+; LP64F-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa0, %lo(var)(s0)
; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
@@ -1148,47 +1148,47 @@
; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var)
-; ILP32D-NEXT: flw ft0, %lo(var)(s0)
-; ILP32D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, %lo(var+4)(s0)
-; ILP32D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, %lo(var+8)(s0)
-; ILP32D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, %lo(var+12)(s0)
-; ILP32D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, %lo(var)(s0)
+; ILP32D-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, %lo(var+4)(s0)
+; ILP32D-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, %lo(var+8)(s0)
+; ILP32D-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, %lo(var+12)(s0)
+; ILP32D-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var)
-; ILP32D-NEXT: flw ft0, 16(s1)
-; ILP32D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 20(s1)
-; ILP32D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 24(s1)
-; ILP32D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 28(s1)
-; ILP32D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 32(s1)
-; ILP32D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 36(s1)
-; ILP32D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 40(s1)
-; ILP32D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 44(s1)
-; ILP32D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 48(s1)
-; ILP32D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 52(s1)
-; ILP32D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 56(s1)
-; ILP32D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 60(s1)
-; ILP32D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 64(s1)
-; ILP32D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 68(s1)
-; ILP32D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 72(s1)
-; ILP32D-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw ft0, 76(s1)
-; ILP32D-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 16(s1)
+; ILP32D-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 20(s1)
+; ILP32D-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 24(s1)
+; ILP32D-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 28(s1)
+; ILP32D-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 32(s1)
+; ILP32D-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 36(s1)
+; ILP32D-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 40(s1)
+; ILP32D-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 44(s1)
+; ILP32D-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 48(s1)
+; ILP32D-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 52(s1)
+; ILP32D-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 56(s1)
+; ILP32D-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 60(s1)
+; ILP32D-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 64(s1)
+; ILP32D-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 68(s1)
+; ILP32D-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 72(s1)
+; ILP32D-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa0, 76(s1)
+; ILP32D-NEXT: fsw fa0, 0(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw fs8, 80(s1)
; ILP32D-NEXT: flw fs9, 84(s1)
; ILP32D-NEXT: flw fs10, 88(s1)
@@ -1214,46 +1214,46 @@
; ILP32D-NEXT: fsw fs10, 88(s1)
; ILP32D-NEXT: fsw fs9, 84(s1)
; ILP32D-NEXT: fsw fs8, 80(s1)
-; ILP32D-NEXT: flw ft0, 0(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 76(s1)
-; ILP32D-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 72(s1)
-; ILP32D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 68(s1)
-; ILP32D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 64(s1)
-; ILP32D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 60(s1)
-; ILP32D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 56(s1)
-; ILP32D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 52(s1)
-; ILP32D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 48(s1)
-; ILP32D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 44(s1)
-; ILP32D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 40(s1)
-; ILP32D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 36(s1)
-; ILP32D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 32(s1)
-; ILP32D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 28(s1)
-; ILP32D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 24(s1)
-; ILP32D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 20(s1)
-; ILP32D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, 16(s1)
-; ILP32D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, %lo(var+12)(s0)
-; ILP32D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, %lo(var+8)(s0)
-; ILP32D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0)
-; ILP32D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw ft0, %lo(var)(s0)
+; ILP32D-NEXT: flw fa0, 0(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 76(s1)
+; ILP32D-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 72(s1)
+; ILP32D-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 68(s1)
+; ILP32D-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 64(s1)
+; ILP32D-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 60(s1)
+; ILP32D-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 56(s1)
+; ILP32D-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 52(s1)
+; ILP32D-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 48(s1)
+; ILP32D-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 44(s1)
+; ILP32D-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 40(s1)
+; ILP32D-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 36(s1)
+; ILP32D-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 32(s1)
+; ILP32D-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 28(s1)
+; ILP32D-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 24(s1)
+; ILP32D-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 20(s1)
+; ILP32D-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, 16(s1)
+; ILP32D-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, %lo(var+12)(s0)
+; ILP32D-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, %lo(var+8)(s0)
+; ILP32D-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, %lo(var+4)(s0)
+; ILP32D-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa0, %lo(var)(s0)
; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
@@ -1291,47 +1291,47 @@
; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var)
-; LP64D-NEXT: flw ft0, %lo(var)(s0)
-; LP64D-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, %lo(var+4)(s0)
-; LP64D-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, %lo(var+8)(s0)
-; LP64D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, %lo(var+12)(s0)
-; LP64D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, %lo(var)(s0)
+; LP64D-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, %lo(var+4)(s0)
+; LP64D-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, %lo(var+8)(s0)
+; LP64D-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, %lo(var+12)(s0)
+; LP64D-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var)
-; LP64D-NEXT: flw ft0, 16(s1)
-; LP64D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 20(s1)
-; LP64D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 24(s1)
-; LP64D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 28(s1)
-; LP64D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 32(s1)
-; LP64D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 36(s1)
-; LP64D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 40(s1)
-; LP64D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 44(s1)
-; LP64D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 48(s1)
-; LP64D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 52(s1)
-; LP64D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 56(s1)
-; LP64D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 60(s1)
-; LP64D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 64(s1)
-; LP64D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 68(s1)
-; LP64D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 72(s1)
-; LP64D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw ft0, 76(s1)
-; LP64D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 16(s1)
+; LP64D-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 20(s1)
+; LP64D-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 24(s1)
+; LP64D-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 28(s1)
+; LP64D-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 32(s1)
+; LP64D-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 36(s1)
+; LP64D-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 40(s1)
+; LP64D-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 44(s1)
+; LP64D-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 48(s1)
+; LP64D-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 52(s1)
+; LP64D-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 56(s1)
+; LP64D-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 60(s1)
+; LP64D-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 64(s1)
+; LP64D-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 68(s1)
+; LP64D-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 72(s1)
+; LP64D-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa0, 76(s1)
+; LP64D-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw fs8, 80(s1)
; LP64D-NEXT: flw fs9, 84(s1)
; LP64D-NEXT: flw fs10, 88(s1)
@@ -1357,46 +1357,46 @@
; LP64D-NEXT: fsw fs10, 88(s1)
; LP64D-NEXT: fsw fs9, 84(s1)
; LP64D-NEXT: fsw fs8, 80(s1)
-; LP64D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 76(s1)
-; LP64D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 72(s1)
-; LP64D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 68(s1)
-; LP64D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 64(s1)
-; LP64D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 60(s1)
-; LP64D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 56(s1)
-; LP64D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 52(s1)
-; LP64D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 48(s1)
-; LP64D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 44(s1)
-; LP64D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 40(s1)
-; LP64D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 36(s1)
-; LP64D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 32(s1)
-; LP64D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 28(s1)
-; LP64D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 24(s1)
-; LP64D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 20(s1)
-; LP64D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, 16(s1)
-; LP64D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, %lo(var+12)(s0)
-; LP64D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, %lo(var+8)(s0)
-; LP64D-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, %lo(var+4)(s0)
-; LP64D-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw ft0, %lo(var)(s0)
+; LP64D-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 76(s1)
+; LP64D-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 72(s1)
+; LP64D-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 68(s1)
+; LP64D-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 64(s1)
+; LP64D-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 60(s1)
+; LP64D-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 56(s1)
+; LP64D-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 52(s1)
+; LP64D-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 48(s1)
+; LP64D-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 44(s1)
+; LP64D-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 40(s1)
+; LP64D-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 36(s1)
+; LP64D-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 32(s1)
+; LP64D-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 28(s1)
+; LP64D-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 24(s1)
+; LP64D-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 20(s1)
+; LP64D-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, 16(s1)
+; LP64D-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, %lo(var+12)(s0)
+; LP64D-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, %lo(var+8)(s0)
+; LP64D-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, %lo(var+4)(s0)
+; LP64D-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa0, %lo(var)(s0)
; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
@@ -20,23 +20,23 @@
; ILP32-LABEL: callee:
; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var)
-; ILP32-NEXT: fld ft0, %lo(var)(a0)
-; ILP32-NEXT: fld ft1, %lo(var+8)(a0)
+; ILP32-NEXT: fld fa0, %lo(var)(a0)
+; ILP32-NEXT: fld fa1, %lo(var+8)(a0)
; ILP32-NEXT: addi a1, a0, %lo(var)
-; ILP32-NEXT: fld ft2, 16(a1)
-; ILP32-NEXT: fld ft3, 24(a1)
-; ILP32-NEXT: fld ft4, 32(a1)
-; ILP32-NEXT: fld ft5, 40(a1)
-; ILP32-NEXT: fld ft6, 48(a1)
-; ILP32-NEXT: fld ft7, 56(a1)
-; ILP32-NEXT: fld fa0, 64(a1)
-; ILP32-NEXT: fld fa1, 72(a1)
-; ILP32-NEXT: fld fa2, 80(a1)
-; ILP32-NEXT: fld fa3, 88(a1)
-; ILP32-NEXT: fld fa4, 96(a1)
-; ILP32-NEXT: fld fa5, 104(a1)
-; ILP32-NEXT: fld fa6, 112(a1)
-; ILP32-NEXT: fld fa7, 120(a1)
+; ILP32-NEXT: fld fa2, 16(a1)
+; ILP32-NEXT: fld fa3, 24(a1)
+; ILP32-NEXT: fld fa4, 32(a1)
+; ILP32-NEXT: fld fa5, 40(a1)
+; ILP32-NEXT: fld fa6, 48(a1)
+; ILP32-NEXT: fld fa7, 56(a1)
+; ILP32-NEXT: fld ft0, 64(a1)
+; ILP32-NEXT: fld ft1, 72(a1)
+; ILP32-NEXT: fld ft2, 80(a1)
+; ILP32-NEXT: fld ft3, 88(a1)
+; ILP32-NEXT: fld ft4, 96(a1)
+; ILP32-NEXT: fld ft5, 104(a1)
+; ILP32-NEXT: fld ft6, 112(a1)
+; ILP32-NEXT: fld ft7, 120(a1)
; ILP32-NEXT: fld ft8, 128(a1)
; ILP32-NEXT: fld ft9, 136(a1)
; ILP32-NEXT: fld ft10, 144(a1)
@@ -69,44 +69,44 @@
; ILP32-NEXT: fsd ft10, 144(a1)
; ILP32-NEXT: fsd ft9, 136(a1)
; ILP32-NEXT: fsd ft8, 128(a1)
-; ILP32-NEXT: fsd fa7, 120(a1)
-; ILP32-NEXT: fsd fa6, 112(a1)
-; ILP32-NEXT: fsd fa5, 104(a1)
-; ILP32-NEXT: fsd fa4, 96(a1)
-; ILP32-NEXT: fsd fa3, 88(a1)
-; ILP32-NEXT: fsd fa2, 80(a1)
-; ILP32-NEXT: fsd fa1, 72(a1)
-; ILP32-NEXT: fsd fa0, 64(a1)
-; ILP32-NEXT: fsd ft7, 56(a1)
-; ILP32-NEXT: fsd ft6, 48(a1)
-; ILP32-NEXT: fsd ft5, 40(a1)
-; ILP32-NEXT: fsd ft4, 32(a1)
-; ILP32-NEXT: fsd ft3, 24(a1)
-; ILP32-NEXT: fsd ft2, 16(a1)
-; ILP32-NEXT: fsd ft1, %lo(var+8)(a0)
-; ILP32-NEXT: fsd ft0, %lo(var)(a0)
+; ILP32-NEXT: fsd ft7, 120(a1)
+; ILP32-NEXT: fsd ft6, 112(a1)
+; ILP32-NEXT: fsd ft5, 104(a1)
+; ILP32-NEXT: fsd ft4, 96(a1)
+; ILP32-NEXT: fsd ft3, 88(a1)
+; ILP32-NEXT: fsd ft2, 80(a1)
+; ILP32-NEXT: fsd ft1, 72(a1)
+; ILP32-NEXT: fsd ft0, 64(a1)
+; ILP32-NEXT: fsd fa7, 56(a1)
+; ILP32-NEXT: fsd fa6, 48(a1)
+; ILP32-NEXT: fsd fa5, 40(a1)
+; ILP32-NEXT: fsd fa4, 32(a1)
+; ILP32-NEXT: fsd fa3, 24(a1)
+; ILP32-NEXT: fsd fa2, 16(a1)
+; ILP32-NEXT: fsd fa1, %lo(var+8)(a0)
+; ILP32-NEXT: fsd fa0, %lo(var)(a0)
; ILP32-NEXT: ret
;
; LP64-LABEL: callee:
; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var)
-; LP64-NEXT: fld ft0, %lo(var)(a0)
-; LP64-NEXT: fld ft1, %lo(var+8)(a0)
+; LP64-NEXT: fld fa0, %lo(var)(a0)
+; LP64-NEXT: fld fa1, %lo(var+8)(a0)
; LP64-NEXT: addi a1, a0, %lo(var)
-; LP64-NEXT: fld ft2, 16(a1)
-; LP64-NEXT: fld ft3, 24(a1)
-; LP64-NEXT: fld ft4, 32(a1)
-; LP64-NEXT: fld ft5, 40(a1)
-; LP64-NEXT: fld ft6, 48(a1)
-; LP64-NEXT: fld ft7, 56(a1)
-; LP64-NEXT: fld fa0, 64(a1)
-; LP64-NEXT: fld fa1, 72(a1)
-; LP64-NEXT: fld fa2, 80(a1)
-; LP64-NEXT: fld fa3, 88(a1)
-; LP64-NEXT: fld fa4, 96(a1)
-; LP64-NEXT: fld fa5, 104(a1)
-; LP64-NEXT: fld fa6, 112(a1)
-; LP64-NEXT: fld fa7, 120(a1)
+; LP64-NEXT: fld fa2, 16(a1)
+; LP64-NEXT: fld fa3, 24(a1)
+; LP64-NEXT: fld fa4, 32(a1)
+; LP64-NEXT: fld fa5, 40(a1)
+; LP64-NEXT: fld fa6, 48(a1)
+; LP64-NEXT: fld fa7, 56(a1)
+; LP64-NEXT: fld ft0, 64(a1)
+; LP64-NEXT: fld ft1, 72(a1)
+; LP64-NEXT: fld ft2, 80(a1)
+; LP64-NEXT: fld ft3, 88(a1)
+; LP64-NEXT: fld ft4, 96(a1)
+; LP64-NEXT: fld ft5, 104(a1)
+; LP64-NEXT: fld ft6, 112(a1)
+; LP64-NEXT: fld ft7, 120(a1)
; LP64-NEXT: fld ft8, 128(a1)
; LP64-NEXT: fld ft9, 136(a1)
; LP64-NEXT: fld ft10, 144(a1)
@@ -139,22 +139,22 @@
; LP64-NEXT: fsd ft10, 144(a1)
; LP64-NEXT: fsd ft9, 136(a1)
; LP64-NEXT: fsd ft8, 128(a1)
-; LP64-NEXT: fsd fa7, 120(a1)
-; LP64-NEXT: fsd fa6, 112(a1)
-; LP64-NEXT: fsd fa5, 104(a1)
-; LP64-NEXT: fsd fa4, 96(a1)
-; LP64-NEXT: fsd fa3, 88(a1)
-; LP64-NEXT: fsd fa2, 80(a1)
-; LP64-NEXT: fsd fa1, 72(a1)
-; LP64-NEXT: fsd fa0, 64(a1)
-; LP64-NEXT: fsd ft7, 56(a1)
-; LP64-NEXT: fsd ft6, 48(a1)
-; LP64-NEXT: fsd ft5, 40(a1)
-; LP64-NEXT: fsd ft4, 32(a1)
-; LP64-NEXT: fsd ft3, 24(a1)
-; LP64-NEXT: fsd ft2, 16(a1)
-; LP64-NEXT: fsd ft1, %lo(var+8)(a0)
-; LP64-NEXT: fsd ft0, %lo(var)(a0)
+; LP64-NEXT: fsd ft7, 120(a1)
+; LP64-NEXT: fsd ft6, 112(a1)
+; LP64-NEXT: fsd ft5, 104(a1)
+; LP64-NEXT: fsd ft4, 96(a1)
+; LP64-NEXT: fsd ft3, 88(a1)
+; LP64-NEXT: fsd ft2, 80(a1)
+; LP64-NEXT: fsd ft1, 72(a1)
+; LP64-NEXT: fsd ft0, 64(a1)
+; LP64-NEXT: fsd fa7, 56(a1)
+; LP64-NEXT: fsd fa6, 48(a1)
+; LP64-NEXT: fsd fa5, 40(a1)
+; LP64-NEXT: fsd fa4, 32(a1)
+; LP64-NEXT: fsd fa3, 24(a1)
+; LP64-NEXT: fsd fa2, 16(a1)
+; LP64-NEXT: fsd fa1, %lo(var+8)(a0)
+; LP64-NEXT: fsd fa0, %lo(var)(a0)
; LP64-NEXT: ret
;
; ILP32D-LABEL: callee:
@@ -173,23 +173,23 @@
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var)
-; ILP32D-NEXT: fld ft0, %lo(var)(a0)
-; ILP32D-NEXT: fld ft1, %lo(var+8)(a0)
+; ILP32D-NEXT: fld fa0, %lo(var)(a0)
+; ILP32D-NEXT: fld fa1, %lo(var+8)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var)
-; ILP32D-NEXT: fld ft2, 16(a1)
-; ILP32D-NEXT: fld ft3, 24(a1)
-; ILP32D-NEXT: fld ft4, 32(a1)
-; ILP32D-NEXT: fld ft5, 40(a1)
-; ILP32D-NEXT: fld ft6, 48(a1)
-; ILP32D-NEXT: fld ft7, 56(a1)
-; ILP32D-NEXT: fld fa0, 64(a1)
-; ILP32D-NEXT: fld fa1, 72(a1)
-; ILP32D-NEXT: fld fa2, 80(a1)
-; ILP32D-NEXT: fld fa3, 88(a1)
-; ILP32D-NEXT: fld fa4, 96(a1)
-; ILP32D-NEXT: fld fa5, 104(a1)
-; ILP32D-NEXT: fld fa6, 112(a1)
-; ILP32D-NEXT: fld fa7, 120(a1)
+; ILP32D-NEXT: fld fa2, 16(a1)
+; ILP32D-NEXT: fld fa3, 24(a1)
+; ILP32D-NEXT: fld fa4, 32(a1)
+; ILP32D-NEXT: fld fa5, 40(a1)
+; ILP32D-NEXT: fld fa6, 48(a1)
+; ILP32D-NEXT: fld fa7, 56(a1)
+; ILP32D-NEXT: fld ft0, 64(a1)
+; ILP32D-NEXT: fld ft1, 72(a1)
+; ILP32D-NEXT: fld ft2, 80(a1)
+; ILP32D-NEXT: fld ft3, 88(a1)
+; ILP32D-NEXT: fld ft4, 96(a1)
+; ILP32D-NEXT: fld ft5, 104(a1)
+; ILP32D-NEXT: fld ft6, 112(a1)
+; ILP32D-NEXT: fld ft7, 120(a1)
; ILP32D-NEXT: fld ft8, 128(a1)
; ILP32D-NEXT: fld ft9, 136(a1)
; ILP32D-NEXT: fld ft10, 144(a1)
@@ -222,22 +222,22 @@
; ILP32D-NEXT: fsd ft10, 144(a1)
; ILP32D-NEXT: fsd ft9, 136(a1)
; ILP32D-NEXT: fsd ft8, 128(a1)
-; ILP32D-NEXT: fsd fa7, 120(a1)
-; ILP32D-NEXT: fsd fa6, 112(a1)
-; ILP32D-NEXT: fsd fa5, 104(a1)
-; ILP32D-NEXT: fsd fa4, 96(a1)
-; ILP32D-NEXT: fsd fa3, 88(a1)
-; ILP32D-NEXT: fsd fa2, 80(a1)
-; ILP32D-NEXT: fsd fa1, 72(a1)
-; ILP32D-NEXT: fsd fa0, 64(a1)
-; ILP32D-NEXT: fsd ft7, 56(a1)
-; ILP32D-NEXT: fsd ft6, 48(a1)
-; ILP32D-NEXT: fsd ft5, 40(a1)
-; ILP32D-NEXT: fsd ft4, 32(a1)
-; ILP32D-NEXT: fsd ft3, 24(a1)
-; ILP32D-NEXT: fsd ft2, 16(a1)
-; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0)
-; ILP32D-NEXT: fsd ft0, %lo(var)(a0)
+; ILP32D-NEXT: fsd ft7, 120(a1)
+; ILP32D-NEXT: fsd ft6, 112(a1)
+; ILP32D-NEXT: fsd ft5, 104(a1)
+; ILP32D-NEXT: fsd ft4, 96(a1)
+; ILP32D-NEXT: fsd ft3, 88(a1)
+; ILP32D-NEXT: fsd ft2, 80(a1)
+; ILP32D-NEXT: fsd ft1, 72(a1)
+; ILP32D-NEXT: fsd ft0, 64(a1)
+; ILP32D-NEXT: fsd fa7, 56(a1)
+; ILP32D-NEXT: fsd fa6, 48(a1)
+; ILP32D-NEXT: fsd fa5, 40(a1)
+; ILP32D-NEXT: fsd fa4, 32(a1)
+; ILP32D-NEXT: fsd fa3, 24(a1)
+; ILP32D-NEXT: fsd fa2, 16(a1)
+; ILP32D-NEXT: fsd fa1, %lo(var+8)(a0)
+; ILP32D-NEXT: fsd fa0, %lo(var)(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -269,23 +269,23 @@
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var)
-; LP64D-NEXT: fld ft0, %lo(var)(a0)
-; LP64D-NEXT: fld ft1, %lo(var+8)(a0)
+; LP64D-NEXT: fld fa0, %lo(var)(a0)
+; LP64D-NEXT: fld fa1, %lo(var+8)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var)
-; LP64D-NEXT: fld ft2, 16(a1)
-; LP64D-NEXT: fld ft3, 24(a1)
-; LP64D-NEXT: fld ft4, 32(a1)
-; LP64D-NEXT: fld ft5, 40(a1)
-; LP64D-NEXT: fld ft6, 48(a1)
-; LP64D-NEXT: fld ft7, 56(a1)
-; LP64D-NEXT: fld fa0, 64(a1)
-; LP64D-NEXT: fld fa1, 72(a1)
-; LP64D-NEXT: fld fa2, 80(a1)
-; LP64D-NEXT: fld fa3, 88(a1)
-; LP64D-NEXT: fld fa4, 96(a1)
-; LP64D-NEXT: fld fa5, 104(a1)
-; LP64D-NEXT: fld fa6, 112(a1)
-; LP64D-NEXT: fld fa7, 120(a1)
+; LP64D-NEXT: fld fa2, 16(a1)
+; LP64D-NEXT: fld fa3, 24(a1)
+; LP64D-NEXT: fld fa4, 32(a1)
+; LP64D-NEXT: fld fa5, 40(a1)
+; LP64D-NEXT: fld fa6, 48(a1)
+; LP64D-NEXT: fld fa7, 56(a1)
+; LP64D-NEXT: fld ft0, 64(a1)
+; LP64D-NEXT: fld ft1, 72(a1)
+; LP64D-NEXT: fld ft2, 80(a1)
+; LP64D-NEXT: fld ft3, 88(a1)
+; LP64D-NEXT: fld ft4, 96(a1)
+; LP64D-NEXT: fld ft5, 104(a1)
+; LP64D-NEXT: fld ft6, 112(a1)
+; LP64D-NEXT: fld ft7, 120(a1)
; LP64D-NEXT: fld ft8, 128(a1)
; LP64D-NEXT: fld ft9, 136(a1)
; LP64D-NEXT: fld ft10, 144(a1)
@@ -318,22 +318,22 @@
; LP64D-NEXT: fsd ft10, 144(a1)
; LP64D-NEXT: fsd ft9, 136(a1)
; LP64D-NEXT: fsd ft8, 128(a1)
-; LP64D-NEXT: fsd fa7, 120(a1)
-; LP64D-NEXT: fsd fa6, 112(a1)
-; LP64D-NEXT: fsd fa5, 104(a1)
-; LP64D-NEXT: fsd fa4, 96(a1)
-; LP64D-NEXT: fsd fa3, 88(a1)
-; LP64D-NEXT: fsd fa2, 80(a1)
-; LP64D-NEXT: fsd fa1, 72(a1)
-; LP64D-NEXT: fsd fa0, 64(a1)
-; LP64D-NEXT: fsd ft7, 56(a1)
-; LP64D-NEXT: fsd ft6, 48(a1)
-; LP64D-NEXT: fsd ft5, 40(a1)
-; LP64D-NEXT: fsd ft4, 32(a1)
-; LP64D-NEXT: fsd ft3, 24(a1)
-; LP64D-NEXT: fsd ft2, 16(a1)
-; LP64D-NEXT: fsd ft1, %lo(var+8)(a0)
-; LP64D-NEXT: fsd ft0, %lo(var)(a0)
+; LP64D-NEXT: fsd ft7, 120(a1)
+; LP64D-NEXT: fsd ft6, 112(a1)
+; LP64D-NEXT: fsd ft5, 104(a1)
+; LP64D-NEXT: fsd ft4, 96(a1)
+; LP64D-NEXT: fsd ft3, 88(a1)
+; LP64D-NEXT: fsd ft2, 80(a1)
+; LP64D-NEXT: fsd ft1, 72(a1)
+; LP64D-NEXT: fsd ft0, 64(a1)
+; LP64D-NEXT: fsd fa7, 56(a1)
+; LP64D-NEXT: fsd fa6, 48(a1)
+; LP64D-NEXT: fsd fa5, 40(a1)
+; LP64D-NEXT: fsd fa4, 32(a1)
+; LP64D-NEXT: fsd fa3, 24(a1)
+; LP64D-NEXT: fsd fa2, 16(a1)
+; LP64D-NEXT: fsd fa1, %lo(var+8)(a0)
+; LP64D-NEXT: fsd fa0, %lo(var)(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -368,136 +368,136 @@
; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var)
-; ILP32-NEXT: fld ft0, %lo(var)(s0)
-; ILP32-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, %lo(var+8)(s0)
-; ILP32-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, %lo(var)(s0)
+; ILP32-NEXT: fsd fa0, 248(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, %lo(var+8)(s0)
+; ILP32-NEXT: fsd fa0, 240(sp) # 8-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var)
-; ILP32-NEXT: fld ft0, 16(s1)
-; ILP32-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 24(s1)
-; ILP32-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 32(s1)
-; ILP32-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 40(s1)
-; ILP32-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 48(s1)
-; ILP32-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 56(s1)
-; ILP32-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 64(s1)
-; ILP32-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 72(s1)
-; ILP32-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 80(s1)
-; ILP32-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 88(s1)
-; ILP32-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 96(s1)
-; ILP32-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 104(s1)
-; ILP32-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 112(s1)
-; ILP32-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 120(s1)
-; ILP32-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 128(s1)
-; ILP32-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 136(s1)
-; ILP32-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 144(s1)
-; ILP32-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 152(s1)
-; ILP32-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 160(s1)
-; ILP32-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 168(s1)
-; ILP32-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 176(s1)
-; ILP32-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 184(s1)
-; ILP32-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 192(s1)
-; ILP32-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 200(s1)
-; ILP32-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 208(s1)
-; ILP32-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 216(s1)
-; ILP32-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 224(s1)
-; ILP32-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 232(s1)
-; ILP32-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 240(s1)
-; ILP32-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld ft0, 248(s1)
-; ILP32-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 16(s1)
+; ILP32-NEXT: fsd fa0, 232(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 24(s1)
+; ILP32-NEXT: fsd fa0, 224(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 32(s1)
+; ILP32-NEXT: fsd fa0, 216(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 40(s1)
+; ILP32-NEXT: fsd fa0, 208(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 48(s1)
+; ILP32-NEXT: fsd fa0, 200(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 56(s1)
+; ILP32-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 64(s1)
+; ILP32-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 72(s1)
+; ILP32-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 80(s1)
+; ILP32-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 88(s1)
+; ILP32-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 96(s1)
+; ILP32-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 104(s1)
+; ILP32-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 112(s1)
+; ILP32-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 120(s1)
+; ILP32-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 128(s1)
+; ILP32-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 136(s1)
+; ILP32-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 144(s1)
+; ILP32-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 152(s1)
+; ILP32-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 160(s1)
+; ILP32-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 168(s1)
+; ILP32-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 176(s1)
+; ILP32-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 184(s1)
+; ILP32-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 192(s1)
+; ILP32-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 200(s1)
+; ILP32-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 208(s1)
+; ILP32-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 216(s1)
+; ILP32-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 224(s1)
+; ILP32-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 232(s1)
+; ILP32-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 240(s1)
+; ILP32-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa0, 248(s1)
+; ILP32-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; ILP32-NEXT: call callee@plt
-; ILP32-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 248(s1)
-; ILP32-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 240(s1)
-; ILP32-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 232(s1)
-; ILP32-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 224(s1)
-; ILP32-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 216(s1)
-; ILP32-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 208(s1)
-; ILP32-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 200(s1)
-; ILP32-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 192(s1)
-; ILP32-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 184(s1)
-; ILP32-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 176(s1)
-; ILP32-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 168(s1)
-; ILP32-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 160(s1)
-; ILP32-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 152(s1)
-; ILP32-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 144(s1)
-; ILP32-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 136(s1)
-; ILP32-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 128(s1)
-; ILP32-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 120(s1)
-; ILP32-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 112(s1)
-; ILP32-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 104(s1)
-; ILP32-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 96(s1)
-; ILP32-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 88(s1)
-; ILP32-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 80(s1)
-; ILP32-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 72(s1)
-; ILP32-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 64(s1)
-; ILP32-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 56(s1)
-; ILP32-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 48(s1)
-; ILP32-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 40(s1)
-; ILP32-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 32(s1)
-; ILP32-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 24(s1)
-; ILP32-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, 16(s1)
-; ILP32-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, %lo(var+8)(s0)
-; ILP32-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd ft0, %lo(var)(s0)
+; ILP32-NEXT: fld fa0, 0(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 248(s1)
+; ILP32-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 240(s1)
+; ILP32-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 232(s1)
+; ILP32-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 224(s1)
+; ILP32-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 216(s1)
+; ILP32-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 208(s1)
+; ILP32-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 200(s1)
+; ILP32-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 192(s1)
+; ILP32-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 184(s1)
+; ILP32-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 176(s1)
+; ILP32-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 168(s1)
+; ILP32-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 160(s1)
+; ILP32-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 152(s1)
+; ILP32-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 144(s1)
+; ILP32-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 136(s1)
+; ILP32-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 128(s1)
+; ILP32-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 120(s1)
+; ILP32-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 112(s1)
+; ILP32-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 104(s1)
+; ILP32-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 96(s1)
+; ILP32-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 88(s1)
+; ILP32-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 80(s1)
+; ILP32-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 72(s1)
+; ILP32-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 64(s1)
+; ILP32-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 56(s1)
+; ILP32-NEXT: fld fa0, 200(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 48(s1)
+; ILP32-NEXT: fld fa0, 208(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 40(s1)
+; ILP32-NEXT: fld fa0, 216(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 32(s1)
+; ILP32-NEXT: fld fa0, 224(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 24(s1)
+; ILP32-NEXT: fld fa0, 232(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, 16(s1)
+; ILP32-NEXT: fld fa0, 240(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, %lo(var+8)(s0)
+; ILP32-NEXT: fld fa0, 248(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa0, %lo(var)(s0)
; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
@@ -511,136 +511,136 @@
; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var)
-; LP64-NEXT: fld ft0, %lo(var)(s0)
-; LP64-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, %lo(var+8)(s0)
-; LP64-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, %lo(var)(s0)
+; LP64-NEXT: fsd fa0, 256(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, %lo(var+8)(s0)
+; LP64-NEXT: fsd fa0, 248(sp) # 8-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var)
-; LP64-NEXT: fld ft0, 16(s1)
-; LP64-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 24(s1)
-; LP64-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 32(s1)
-; LP64-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 40(s1)
-; LP64-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 48(s1)
-; LP64-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 56(s1)
-; LP64-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 64(s1)
-; LP64-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 72(s1)
-; LP64-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 80(s1)
-; LP64-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 88(s1)
-; LP64-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 96(s1)
-; LP64-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 104(s1)
-; LP64-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 112(s1)
-; LP64-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 120(s1)
-; LP64-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 128(s1)
-; LP64-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 136(s1)
-; LP64-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 144(s1)
-; LP64-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 152(s1)
-; LP64-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 160(s1)
-; LP64-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 168(s1)
-; LP64-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 176(s1)
-; LP64-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 184(s1)
-; LP64-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 192(s1)
-; LP64-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 200(s1)
-; LP64-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 208(s1)
-; LP64-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 216(s1)
-; LP64-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 224(s1)
-; LP64-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 232(s1)
-; LP64-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 240(s1)
-; LP64-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld ft0, 248(s1)
-; LP64-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 16(s1)
+; LP64-NEXT: fsd fa0, 240(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 24(s1)
+; LP64-NEXT: fsd fa0, 232(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 32(s1)
+; LP64-NEXT: fsd fa0, 224(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 40(s1)
+; LP64-NEXT: fsd fa0, 216(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 48(s1)
+; LP64-NEXT: fsd fa0, 208(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 56(s1)
+; LP64-NEXT: fsd fa0, 200(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 64(s1)
+; LP64-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 72(s1)
+; LP64-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 80(s1)
+; LP64-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 88(s1)
+; LP64-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 96(s1)
+; LP64-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 104(s1)
+; LP64-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 112(s1)
+; LP64-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 120(s1)
+; LP64-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 128(s1)
+; LP64-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 136(s1)
+; LP64-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 144(s1)
+; LP64-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 152(s1)
+; LP64-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 160(s1)
+; LP64-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 168(s1)
+; LP64-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 176(s1)
+; LP64-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 184(s1)
+; LP64-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 192(s1)
+; LP64-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 200(s1)
+; LP64-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 208(s1)
+; LP64-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 216(s1)
+; LP64-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 224(s1)
+; LP64-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 232(s1)
+; LP64-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 240(s1)
+; LP64-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa0, 248(s1)
+; LP64-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; LP64-NEXT: call callee@plt
-; LP64-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 248(s1)
-; LP64-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 240(s1)
-; LP64-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 232(s1)
-; LP64-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 224(s1)
-; LP64-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 216(s1)
-; LP64-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 208(s1)
-; LP64-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 200(s1)
-; LP64-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 192(s1)
-; LP64-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 184(s1)
-; LP64-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 176(s1)
-; LP64-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 168(s1)
-; LP64-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 160(s1)
-; LP64-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 152(s1)
-; LP64-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 144(s1)
-; LP64-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 136(s1)
-; LP64-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 128(s1)
-; LP64-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 120(s1)
-; LP64-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 112(s1)
-; LP64-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 104(s1)
-; LP64-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 96(s1)
-; LP64-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 88(s1)
-; LP64-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 80(s1)
-; LP64-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 72(s1)
-; LP64-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 64(s1)
-; LP64-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 56(s1)
-; LP64-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 48(s1)
-; LP64-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 40(s1)
-; LP64-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 32(s1)
-; LP64-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 24(s1)
-; LP64-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, 16(s1)
-; LP64-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, %lo(var+8)(s0)
-; LP64-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd ft0, %lo(var)(s0)
+; LP64-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 248(s1)
+; LP64-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 240(s1)
+; LP64-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 232(s1)
+; LP64-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 224(s1)
+; LP64-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 216(s1)
+; LP64-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 208(s1)
+; LP64-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 200(s1)
+; LP64-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 192(s1)
+; LP64-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 184(s1)
+; LP64-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 176(s1)
+; LP64-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 168(s1)
+; LP64-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 160(s1)
+; LP64-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 152(s1)
+; LP64-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 144(s1)
+; LP64-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 136(s1)
+; LP64-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 128(s1)
+; LP64-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 120(s1)
+; LP64-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 112(s1)
+; LP64-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 104(s1)
+; LP64-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 96(s1)
+; LP64-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 88(s1)
+; LP64-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 80(s1)
+; LP64-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 72(s1)
+; LP64-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 64(s1)
+; LP64-NEXT: fld fa0, 200(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 56(s1)
+; LP64-NEXT: fld fa0, 208(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 48(s1)
+; LP64-NEXT: fld fa0, 216(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 40(s1)
+; LP64-NEXT: fld fa0, 224(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 32(s1)
+; LP64-NEXT: fld fa0, 232(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 24(s1)
+; LP64-NEXT: fld fa0, 240(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, 16(s1)
+; LP64-NEXT: fld fa0, 248(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, %lo(var+8)(s0)
+; LP64-NEXT: fld fa0, 256(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa0, %lo(var)(s0)
; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
@@ -666,47 +666,47 @@
; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var)
-; ILP32D-NEXT: fld ft0, %lo(var)(s0)
-; ILP32D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, %lo(var+8)(s0)
-; ILP32D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, %lo(var)(s0)
+; ILP32D-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, %lo(var+8)(s0)
+; ILP32D-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var)
-; ILP32D-NEXT: fld ft0, 16(s1)
-; ILP32D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 24(s1)
-; ILP32D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 32(s1)
-; ILP32D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 40(s1)
-; ILP32D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 48(s1)
-; ILP32D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 56(s1)
-; ILP32D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 64(s1)
-; ILP32D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 72(s1)
-; ILP32D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 80(s1)
-; ILP32D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 88(s1)
-; ILP32D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 96(s1)
-; ILP32D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 104(s1)
-; ILP32D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 112(s1)
-; ILP32D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 120(s1)
-; ILP32D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 128(s1)
-; ILP32D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 136(s1)
-; ILP32D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 144(s1)
-; ILP32D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld ft0, 152(s1)
-; ILP32D-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 16(s1)
+; ILP32D-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 24(s1)
+; ILP32D-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 32(s1)
+; ILP32D-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 40(s1)
+; ILP32D-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 48(s1)
+; ILP32D-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 56(s1)
+; ILP32D-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 64(s1)
+; ILP32D-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 72(s1)
+; ILP32D-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 80(s1)
+; ILP32D-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 88(s1)
+; ILP32D-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 96(s1)
+; ILP32D-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 104(s1)
+; ILP32D-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 112(s1)
+; ILP32D-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 120(s1)
+; ILP32D-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 128(s1)
+; ILP32D-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 136(s1)
+; ILP32D-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 144(s1)
+; ILP32D-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa0, 152(s1)
+; ILP32D-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld fs8, 160(s1)
; ILP32D-NEXT: fld fs9, 168(s1)
; ILP32D-NEXT: fld fs10, 176(s1)
@@ -732,46 +732,46 @@
; ILP32D-NEXT: fsd fs10, 176(s1)
; ILP32D-NEXT: fsd fs9, 168(s1)
; ILP32D-NEXT: fsd fs8, 160(s1)
-; ILP32D-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 152(s1)
-; ILP32D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 144(s1)
-; ILP32D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 136(s1)
-; ILP32D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 128(s1)
-; ILP32D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 120(s1)
-; ILP32D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 112(s1)
-; ILP32D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 104(s1)
-; ILP32D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 96(s1)
-; ILP32D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 88(s1)
-; ILP32D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 80(s1)
-; ILP32D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 72(s1)
-; ILP32D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 64(s1)
-; ILP32D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 56(s1)
-; ILP32D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 48(s1)
-; ILP32D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 40(s1)
-; ILP32D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 32(s1)
-; ILP32D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 24(s1)
-; ILP32D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, 16(s1)
-; ILP32D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0)
-; ILP32D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd ft0, %lo(var)(s0)
+; ILP32D-NEXT: fld fa0, 0(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 152(s1)
+; ILP32D-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 144(s1)
+; ILP32D-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 136(s1)
+; ILP32D-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 128(s1)
+; ILP32D-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 120(s1)
+; ILP32D-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 112(s1)
+; ILP32D-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 104(s1)
+; ILP32D-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 96(s1)
+; ILP32D-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 88(s1)
+; ILP32D-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 80(s1)
+; ILP32D-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 72(s1)
+; ILP32D-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 64(s1)
+; ILP32D-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 56(s1)
+; ILP32D-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 48(s1)
+; ILP32D-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 40(s1)
+; ILP32D-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 32(s1)
+; ILP32D-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 24(s1)
+; ILP32D-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, 16(s1)
+; ILP32D-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, %lo(var+8)(s0)
+; ILP32D-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa0, %lo(var)(s0)
; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
@@ -809,47 +809,47 @@
; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var)
-; LP64D-NEXT: fld ft0, %lo(var)(s0)
-; LP64D-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, %lo(var+8)(s0)
-; LP64D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, %lo(var)(s0)
+; LP64D-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, %lo(var+8)(s0)
+; LP64D-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var)
-; LP64D-NEXT: fld ft0, 16(s1)
-; LP64D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 24(s1)
-; LP64D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 32(s1)
-; LP64D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 40(s1)
-; LP64D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 48(s1)
-; LP64D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 56(s1)
-; LP64D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 64(s1)
-; LP64D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 72(s1)
-; LP64D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 80(s1)
-; LP64D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 88(s1)
-; LP64D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 96(s1)
-; LP64D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 104(s1)
-; LP64D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 112(s1)
-; LP64D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 120(s1)
-; LP64D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 128(s1)
-; LP64D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 136(s1)
-; LP64D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 144(s1)
-; LP64D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld ft0, 152(s1)
-; LP64D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 16(s1)
+; LP64D-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 24(s1)
+; LP64D-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 32(s1)
+; LP64D-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 40(s1)
+; LP64D-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 48(s1)
+; LP64D-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 56(s1)
+; LP64D-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 64(s1)
+; LP64D-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 72(s1)
+; LP64D-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 80(s1)
+; LP64D-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 88(s1)
+; LP64D-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 96(s1)
+; LP64D-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 104(s1)
+; LP64D-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 112(s1)
+; LP64D-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 120(s1)
+; LP64D-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 128(s1)
+; LP64D-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 136(s1)
+; LP64D-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 144(s1)
+; LP64D-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fa0, 152(s1)
+; LP64D-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld fs8, 160(s1)
; LP64D-NEXT: fld fs9, 168(s1)
; LP64D-NEXT: fld fs10, 176(s1)
@@ -875,46 +875,46 @@
; LP64D-NEXT: fsd fs10, 176(s1)
; LP64D-NEXT: fsd fs9, 168(s1)
; LP64D-NEXT: fsd fs8, 160(s1)
-; LP64D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 152(s1)
-; LP64D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 144(s1)
-; LP64D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 136(s1)
-; LP64D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 128(s1)
-; LP64D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 120(s1)
-; LP64D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 112(s1)
-; LP64D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 104(s1)
-; LP64D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 96(s1)
-; LP64D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 88(s1)
-; LP64D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 80(s1)
-; LP64D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 72(s1)
-; LP64D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 64(s1)
-; LP64D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 56(s1)
-; LP64D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 48(s1)
-; LP64D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 40(s1)
-; LP64D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 32(s1)
-; LP64D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 24(s1)
-; LP64D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, 16(s1)
-; LP64D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, %lo(var+8)(s0)
-; LP64D-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd ft0, %lo(var)(s0)
+; LP64D-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 152(s1)
+; LP64D-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 144(s1)
+; LP64D-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 136(s1)
+; LP64D-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 128(s1)
+; LP64D-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 120(s1)
+; LP64D-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 112(s1)
+; LP64D-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 104(s1)
+; LP64D-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 96(s1)
+; LP64D-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 88(s1)
+; LP64D-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 80(s1)
+; LP64D-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 72(s1)
+; LP64D-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 64(s1)
+; LP64D-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 56(s1)
+; LP64D-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 48(s1)
+; LP64D-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 40(s1)
+; LP64D-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 32(s1)
+; LP64D-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 24(s1)
+; LP64D-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, 16(s1)
+; LP64D-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, %lo(var+8)(s0)
+; LP64D-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa0, %lo(var)(s0)
; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
@@ -53,8 +53,8 @@
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: call __extendhfsf2@plt
-; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: fmv.w.x fa0, a0
+; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: add a0, s0, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -69,8 +69,8 @@
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: mv a0, a1
; RV64IF-NEXT: call __extendhfsf2@plt
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: addw a0, s0, a0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
@@ -180,8 +180,8 @@
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV64IF-NEXT: fmv.x.w a1, ft0
+; RV64IF-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
+; RV64IF-NEXT: fmv.x.w a1, fa0
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: call callee_half_in_regs@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -278,8 +278,8 @@
; RV32IF-NEXT: lhu a0, 16(sp)
; RV32IF-NEXT: mv s0, a7
; RV32IF-NEXT: call __extendhfsf2@plt
-; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: fmv.w.x fa0, a0
+; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: add a0, s0, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -294,8 +294,8 @@
; RV64IF-NEXT: lhu a0, 16(sp)
; RV64IF-NEXT: mv s0, a7
; RV64IF-NEXT: call __extendhfsf2@plt
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: addw a0, s0, a0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
@@ -548,8 +548,8 @@
; RV64IF-LABEL: callee_half_ret:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI4_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
;
; RV32-ILP32F-LABEL: callee_half_ret:
@@ -611,8 +611,8 @@
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call callee_half_ret@plt
; RV32IF-NEXT: call __extendhfsf2@plt
-; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: fmv.w.x fa0, a0
+; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@@ -623,8 +623,8 @@
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call callee_half_ret@plt
; RV64IF-NEXT: call __extendhfsf2@plt
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
@@ -79,9 +79,9 @@
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw a0, 8(sp)
; RV32-ILP32D-NEXT: sw a1, 12(sp)
-; RV32-ILP32D-NEXT: fld ft0, 8(sp)
+; RV32-ILP32D-NEXT: fld fa0, 8(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
-; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz
+; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -132,8 +132,8 @@
; RV32-ILP32D-NEXT: lw a0, 16(sp)
; RV32-ILP32D-NEXT: sw a7, 8(sp)
; RV32-ILP32D-NEXT: sw a0, 12(sp)
-; RV32-ILP32D-NEXT: fld ft0, 8(sp)
-; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32-ILP32D-NEXT: fld fa0, 8(sp)
+; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a6, a0
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -188,8 +188,8 @@
define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
; RV32-ILP32D-LABEL: callee_double_on_stack_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0:
-; RV32-ILP32D-NEXT: fld ft0, 0(sp)
-; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32-ILP32D-NEXT: fld fa0, 0(sp)
+; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a6, a0
; RV32-ILP32D-NEXT: ret
%g_trunc = trunc i64 %g to i32
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
@@ -79,9 +79,9 @@
define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0:
-; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0
+; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
-; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz
+; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret
%h_fptosi = fptosi float %h to i32
@@ -126,8 +126,8 @@
define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind {
; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs:
; RV32-ILP32FD: # %bb.0:
-; RV32-ILP32FD-NEXT: flw ft0, 0(sp)
-; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32-ILP32FD-NEXT: flw fa0, 0(sp)
+; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a6, a0
; RV32-ILP32FD-NEXT: ret
%g_trunc = trunc i64 %g to i32
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
@@ -18,10 +18,10 @@
define float @onstack_f32_fadd(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
; RV32IF-LABEL: onstack_f32_fadd:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: flw ft0, 4(sp)
-; RV32IF-NEXT: flw ft1, 0(sp)
-; RV32IF-NEXT: fadd.s ft0, ft1, ft0
-; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: flw fa0, 4(sp)
+; RV32IF-NEXT: flw fa1, 0(sp)
+; RV32IF-NEXT: fadd.s fa0, fa1, fa0
+; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret
%1 = fadd float %e, %f
ret float %1
@@ -56,16 +56,16 @@
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT: fmv.w.x ft0, a1
-; RV32IF-NEXT: fmv.w.x ft1, a0
-; RV32IF-NEXT: fadd.s ft2, ft1, ft0
-; RV32IF-NEXT: fsub.s ft0, ft0, ft1
-; RV32IF-NEXT: fsw ft0, 4(sp)
+; RV32IF-NEXT: fmv.w.x fa0, a1
+; RV32IF-NEXT: fmv.w.x fa1, a0
+; RV32IF-NEXT: fadd.s fa2, fa1, fa0
+; RV32IF-NEXT: fsub.s fa0, fa0, fa1
+; RV32IF-NEXT: fsw fa0, 4(sp)
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: li a2, 2
; RV32IF-NEXT: li a4, 3
; RV32IF-NEXT: li a6, 4
-; RV32IF-NEXT: fsw ft2, 0(sp)
+; RV32IF-NEXT: fsw fa2, 0(sp)
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a5, 0
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
@@ -7,14 +7,14 @@
define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
; RV64-LABEL: callee_v2f32:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.w.x ft0, a2
-; RV64-NEXT: fmv.w.x ft1, a0
-; RV64-NEXT: fmv.w.x ft2, a3
-; RV64-NEXT: fmv.w.x ft3, a1
-; RV64-NEXT: fadd.s ft2, ft3, ft2
-; RV64-NEXT: fadd.s ft0, ft1, ft0
-; RV64-NEXT: fmv.x.w a0, ft0
-; RV64-NEXT: fmv.x.w a1, ft2
+; RV64-NEXT: fmv.w.x fa0, a2
+; RV64-NEXT: fmv.w.x fa1, a0
+; RV64-NEXT: fmv.w.x fa2, a3
+; RV64-NEXT: fmv.w.x fa3, a1
+; RV64-NEXT: fadd.s fa2, fa3, fa2
+; RV64-NEXT: fadd.s fa0, fa1, fa0
+; RV64-NEXT: fmv.x.w a0, fa0
+; RV64-NEXT: fmv.x.w a1, fa2
; RV64-NEXT: ret
;
; RV64LP64F-LABEL: callee_v2f32:
@@ -29,34 +29,34 @@
define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
; RV64-LABEL: callee_v4f32:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.w.x ft0, a4
-; RV64-NEXT: fmv.w.x ft1, a7
-; RV64-NEXT: fmv.w.x ft2, a3
-; RV64-NEXT: fmv.w.x ft3, a6
-; RV64-NEXT: fmv.w.x ft4, a2
-; RV64-NEXT: fmv.w.x ft5, a5
-; RV64-NEXT: fmv.w.x ft6, a1
-; RV64-NEXT: flw ft7, 0(sp)
-; RV64-NEXT: fadd.s ft5, ft6, ft5
-; RV64-NEXT: fadd.s ft3, ft4, ft3
-; RV64-NEXT: fadd.s ft1, ft2, ft1
-; RV64-NEXT: fadd.s ft0, ft0, ft7
-; RV64-NEXT: fsw ft0, 12(a0)
-; RV64-NEXT: fsw ft1, 8(a0)
-; RV64-NEXT: fsw ft3, 4(a0)
-; RV64-NEXT: fsw ft5, 0(a0)
+; RV64-NEXT: fmv.w.x fa0, a4
+; RV64-NEXT: fmv.w.x fa1, a7
+; RV64-NEXT: fmv.w.x fa2, a3
+; RV64-NEXT: fmv.w.x fa3, a6
+; RV64-NEXT: fmv.w.x fa4, a2
+; RV64-NEXT: fmv.w.x fa5, a5
+; RV64-NEXT: fmv.w.x fa6, a1
+; RV64-NEXT: flw fa7, 0(sp)
+; RV64-NEXT: fadd.s fa5, fa6, fa5
+; RV64-NEXT: fadd.s fa3, fa4, fa3
+; RV64-NEXT: fadd.s fa1, fa2, fa1
+; RV64-NEXT: fadd.s fa0, fa0, fa7
+; RV64-NEXT: fsw fa0, 12(a0)
+; RV64-NEXT: fsw fa1, 8(a0)
+; RV64-NEXT: fsw fa3, 4(a0)
+; RV64-NEXT: fsw fa5, 0(a0)
; RV64-NEXT: ret
;
; RV64LP64F-LABEL: callee_v4f32:
; RV64LP64F: # %bb.0:
-; RV64LP64F-NEXT: fadd.s ft0, fa0, fa4
-; RV64LP64F-NEXT: fadd.s ft1, fa1, fa5
-; RV64LP64F-NEXT: fadd.s ft2, fa2, fa6
-; RV64LP64F-NEXT: fadd.s ft3, fa3, fa7
-; RV64LP64F-NEXT: fsw ft3, 12(a0)
-; RV64LP64F-NEXT: fsw ft2, 8(a0)
-; RV64LP64F-NEXT: fsw ft1, 4(a0)
-; RV64LP64F-NEXT: fsw ft0, 0(a0)
+; RV64LP64F-NEXT: fadd.s fa0, fa0, fa4
+; RV64LP64F-NEXT: fadd.s fa1, fa1, fa5
+; RV64LP64F-NEXT: fadd.s fa2, fa2, fa6
+; RV64LP64F-NEXT: fadd.s fa3, fa3, fa7
+; RV64LP64F-NEXT: fsw fa3, 12(a0)
+; RV64LP64F-NEXT: fsw fa2, 8(a0)
+; RV64LP64F-NEXT: fsw fa1, 4(a0)
+; RV64LP64F-NEXT: fsw fa0, 0(a0)
; RV64LP64F-NEXT: ret
%z = fadd <4 x float> %x, %y
ret <4 x float> %z
diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
--- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
@@ -128,10 +128,10 @@
; RV32I-SMALL-LABEL: lower_constantpool:
; RV32I-SMALL: # %bb.0:
; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a1)
-; RV32I-SMALL-NEXT: fmv.w.x ft1, a0
-; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0
-; RV32I-SMALL-NEXT: fmv.x.w a0, ft0
+; RV32I-SMALL-NEXT: flw fa0, %lo(.LCPI3_0)(a1)
+; RV32I-SMALL-NEXT: fmv.w.x fa1, a0
+; RV32I-SMALL-NEXT: fadd.s fa0, fa1, fa0
+; RV32I-SMALL-NEXT: fmv.x.w a0, fa0
; RV32I-SMALL-NEXT: ret
;
; RV32I-MEDIUM-LABEL: lower_constantpool:
@@ -139,10 +139,10 @@
; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
-; RV32I-MEDIUM-NEXT: flw ft0, 0(a1)
-; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0
-; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0
-; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0
+; RV32I-MEDIUM-NEXT: flw fa0, 0(a1)
+; RV32I-MEDIUM-NEXT: fmv.w.x fa1, a0
+; RV32I-MEDIUM-NEXT: fadd.s fa0, fa1, fa0
+; RV32I-MEDIUM-NEXT: fmv.x.w a0, fa0
; RV32I-MEDIUM-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll
--- a/llvm/test/CodeGen/RISCV/copysign-casts.ll
+++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll
@@ -58,14 +58,14 @@
;
; RV32IFD-LABEL: fold_promote_d_s:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.s ft0, fa1
-; RV32IFD-NEXT: fsgnj.d fa0, fa0, ft0
+; RV32IFD-NEXT: fcvt.d.s fa1, fa1
+; RV32IFD-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fold_promote_d_s:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.s ft0, fa1
-; RV64IFD-NEXT: fsgnj.d fa0, fa0, ft0
+; RV64IFD-NEXT: fcvt.d.s fa1, fa1
+; RV64IFD-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFD-NEXT: ret
;
; RV32IFZFH-LABEL: fold_promote_d_s:
@@ -80,14 +80,14 @@
;
; RV32IFDZFH-LABEL: fold_promote_d_s:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.d.s ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.d.s fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_promote_d_s:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.d.s ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.d.s fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fpext float %b to double
%t = call double @llvm.copysign.f64(double %a, double %c)
@@ -134,8 +134,8 @@
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fmv.x.w a0, fa1
; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: fcvt.d.s ft0, fa0
-; RV32IFD-NEXT: fsgnj.d fa0, fs0, ft0
+; RV32IFD-NEXT: fcvt.d.s fa0, fa0
+; RV32IFD-NEXT: fsgnj.d fa0, fs0, fa0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
@@ -149,8 +149,8 @@
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: fmv.x.w a0, fa1
; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: fcvt.d.s ft0, fa0
-; RV64IFD-NEXT: fsgnj.d fa0, fs0, ft0
+; RV64IFD-NEXT: fcvt.d.s fa0, fa0
+; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
@@ -169,14 +169,14 @@
;
; RV32IFDZFH-LABEL: fold_promote_d_h:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.d.h ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.d.h fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_promote_d_h:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.d.h ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.d.h fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fpext half %b to double
%t = call double @llvm.copysign.f64(double %a, double %c)
@@ -248,20 +248,20 @@
;
; RV32IFZFH-LABEL: fold_promote_f_h:
; RV32IFZFH: # %bb.0:
-; RV32IFZFH-NEXT: fcvt.s.h ft0, fa1
-; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IFZFH-NEXT: fcvt.s.h fa1, fa1
+; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFZFH-NEXT: ret
;
; RV32IFDZFH-LABEL: fold_promote_f_h:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.s.h ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.s.h fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_promote_f_h:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.s.h ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.s.h fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fpext half %b to float
%t = call float @llvm.copysign.f32(float %a, float %c)
@@ -290,38 +290,38 @@
;
; RV32IF-LABEL: fold_demote_s_d:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, a1
-; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IF-NEXT: fmv.w.x fa1, a1
+; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV32IFD-LABEL: fold_demote_s_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.s.d ft0, fa1
-; RV32IFD-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IFD-NEXT: fcvt.s.d fa1, fa1
+; RV32IFD-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fold_demote_s_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.s.d ft0, fa1
-; RV64IFD-NEXT: fsgnj.s fa0, fa0, ft0
+; RV64IFD-NEXT: fcvt.s.d fa1, fa1
+; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFD-NEXT: ret
;
; RV32IFZFH-LABEL: fold_demote_s_d:
; RV32IFZFH: # %bb.0:
-; RV32IFZFH-NEXT: fmv.w.x ft0, a1
-; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IFZFH-NEXT: fmv.w.x fa1, a1
+; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFZFH-NEXT: ret
;
; RV32IFDZFH-LABEL: fold_demote_s_d:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.s.d ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.s.d fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_demote_s_d:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.s.d ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.s.d fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fptrunc double %b to float
%t = call float @llvm.copysign.f32(float %a, float %c)
@@ -397,20 +397,20 @@
;
; RV32IFZFH-LABEL: fold_demote_h_s:
; RV32IFZFH: # %bb.0:
-; RV32IFZFH-NEXT: fcvt.h.s ft0, fa1
-; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV32IFZFH-NEXT: fcvt.h.s fa1, fa1
+; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFZFH-NEXT: ret
;
; RV32IFDZFH-LABEL: fold_demote_h_s:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.h.s ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.h.s fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_demote_h_s:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.h.s ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.h.s fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fptrunc float %b to half
%t = call half @llvm.copysign.f16(half %a, half %c)
@@ -488,20 +488,20 @@
; RV32IFZFH-LABEL: fold_demote_h_d:
; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: srli a0, a1, 16
-; RV32IFZFH-NEXT: fmv.h.x ft0, a0
-; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV32IFZFH-NEXT: fmv.h.x fa1, a0
+; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFZFH-NEXT: ret
;
; RV32IFDZFH-LABEL: fold_demote_h_d:
; RV32IFDZFH: # %bb.0:
-; RV32IFDZFH-NEXT: fcvt.h.d ft0, fa1
-; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV32IFDZFH-NEXT: fcvt.h.d fa1, fa1
+; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret
;
; RV64IFDZFH-LABEL: fold_demote_h_d:
; RV64IFDZFH: # %bb.0:
-; RV64IFDZFH-NEXT: fcvt.h.d ft0, fa1
-; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0
+; RV64IFDZFH-NEXT: fcvt.h.d fa1, fa1
+; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret
%c = fptrunc double %b to half
%t = call half @llvm.copysign.f16(half %a, half %c)
diff --git a/llvm/test/CodeGen/RISCV/double-arith-strict.ll b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
--- a/llvm/test/CodeGen/RISCV/double-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
@@ -293,16 +293,16 @@
define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fmsub_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fmsub_d:
@@ -369,18 +369,18 @@
define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmadd_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d:
@@ -465,18 +465,18 @@
define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmadd_d_2:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa1, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d_2:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa1, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d_2:
@@ -562,16 +562,16 @@
define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmsub_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa0, ft0
-; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa0, ft0
-; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmsub_d:
@@ -634,16 +634,16 @@
define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmsub_d_2:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d_2:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmsub_d_2:
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -214,16 +214,16 @@
define i32 @fneg_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fneg_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa0
-; RV32IFD-NEXT: fneg.d ft1, ft0
-; RV32IFD-NEXT: feq.d a0, ft0, ft1
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa0
+; RV32IFD-NEXT: fneg.d fa1, fa0
+; RV32IFD-NEXT: feq.d a0, fa0, fa1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fneg_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa0
-; RV64IFD-NEXT: fneg.d ft1, ft0
-; RV64IFD-NEXT: feq.d a0, ft0, ft1
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa0
+; RV64IFD-NEXT: fneg.d fa1, fa0
+; RV64IFD-NEXT: feq.d a0, fa0, fa1
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fneg_d:
@@ -308,16 +308,16 @@
define double @fabs_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fabs_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fabs.d ft1, ft0
-; RV32IFD-NEXT: fadd.d fa0, ft1, ft0
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV32IFD-NEXT: fabs.d fa1, fa0
+; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fabs_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fabs.d ft1, ft0
-; RV64IFD-NEXT: fadd.d fa0, ft1, ft0
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV64IFD-NEXT: fabs.d fa1, fa0
+; RV64IFD-NEXT: fadd.d fa0, fa1, fa0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fabs_d:
@@ -457,16 +457,16 @@
define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmsub_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fmsub_d:
@@ -533,18 +533,18 @@
define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d:
@@ -629,18 +629,18 @@
define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_2:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa1, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d_2:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa1, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d_2:
@@ -726,16 +726,16 @@
define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa0, ft0
-; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa0, ft0
-; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmsub_d:
@@ -798,16 +798,16 @@
define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d_2:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d_2:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmsub_d_2:
@@ -921,16 +921,16 @@
define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmsub_d_contract:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmsub_d_contract:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fmsub_d_contract:
@@ -1005,20 +1005,20 @@
define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_contract:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV32IFD-NEXT: fadd.d ft2, fa1, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV32IFD-NEXT: fnmadd.d fa0, ft1, ft2, ft0
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d_contract:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV64IFD-NEXT: fadd.d ft2, fa1, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa2, ft0
-; RV64IFD-NEXT: fnmadd.d fa0, ft1, ft2, ft0
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
+; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d_contract:
@@ -1120,18 +1120,18 @@
define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d_contract:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV32IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV32IFD-NEXT: fnmsub.d fa0, ft1, ft0, fa2
+; RV32IFD-NEXT: fcvt.d.w fa3, zero
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d_contract:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, zero
-; RV64IFD-NEXT: fadd.d ft1, fa0, ft0
-; RV64IFD-NEXT: fadd.d ft0, fa1, ft0
-; RV64IFD-NEXT: fnmsub.d fa0, ft1, ft0, fa2
+; RV64IFD-NEXT: fmv.d.x fa3, zero
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
+; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
+; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmsub_d_contract:
diff --git a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
@@ -99,12 +99,12 @@
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
-; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
-; RV32IFD-NEXT: fld ft1, 8(sp)
-; RV32IFD-NEXT: fsgnjn.d ft0, ft1, ft0
-; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: fld fa1, 8(sp)
+; RV32IFD-NEXT: fsgnjn.d fa0, fa1, fa0
+; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
@@ -125,10 +125,10 @@
; RV64IFD-NEXT: li a2, -1
; RV64IFD-NEXT: slli a2, a2, 63
; RV64IFD-NEXT: xor a1, a1, a2
-; RV64IFD-NEXT: fmv.d.x ft0, a1
-; RV64IFD-NEXT: fmv.d.x ft1, a0
-; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
-; RV64IFD-NEXT: fmv.x.d a0, ft0
+; RV64IFD-NEXT: fmv.d.x fa0, a1
+; RV64IFD-NEXT: fmv.d.x fa1, a0
+; RV64IFD-NEXT: fsgnj.d fa0, fa1, fa0
+; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ret
%1 = fneg double %b
%2 = call double @llvm.copysign.f64(double %a, double %1)
diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
--- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -13,12 +13,12 @@
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
-; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
-; RV32IFD-NEXT: fld ft1, 8(sp)
-; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
-; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: fld fa1, 8(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
+; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
@@ -56,12 +56,12 @@
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: sw a7, 8(sp)
; RV32IFD-NEXT: sw a0, 12(sp)
-; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a5, 8(sp)
; RV32IFD-NEXT: sw a6, 12(sp)
-; RV32IFD-NEXT: fld ft1, 8(sp)
-; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
-; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: fld fa1, 8(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
+; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
@@ -100,10 +100,10 @@
; RV32IFD-LABEL: callee_double_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: fld ft0, 24(sp)
-; RV32IFD-NEXT: fld ft1, 16(sp)
-; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
-; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: fld fa0, 24(sp)
+; RV32IFD-NEXT: fld fa1, 16(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
+; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/double-convert-strict.ll b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
@@ -633,15 +633,15 @@
; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
-; RV32IFD-NEXT: fcvt.d.w ft0, a0
-; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: fcvt.d.w fa0, a0
+; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.w ft0, a0
-; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: fcvt.d.w fa0, a0
+; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_demanded_bits:
@@ -691,15 +691,15 @@
; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
-; RV32IFD-NEXT: fcvt.d.wu ft0, a0
-; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: fcvt.d.wu fa0, a0
+; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.wu ft0, a0
-; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: fcvt.d.wu fa0, a0
+; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -615,9 +615,9 @@
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI12_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB12_2
@@ -625,8 +625,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB12_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI12_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB12_9
; RV32IFD-NEXT: # %bb.3: # %start
@@ -868,8 +868,9 @@
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB14_2
@@ -877,8 +878,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB14_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB14_7
@@ -1031,8 +1032,8 @@
; RV32IFD-LABEL: fmv_x_d:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
@@ -1040,8 +1041,8 @@
;
; RV64IFD-LABEL: fmv_x_d:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fmv.x.d a0, ft0
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fmv_x_d:
@@ -1147,17 +1148,17 @@
; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
-; RV32IFD-NEXT: fld ft0, 0(sp)
-; RV32IFD-NEXT: fld ft1, 8(sp)
-; RV32IFD-NEXT: fadd.d fa0, ft1, ft0
+; RV32IFD-NEXT: fld fa0, 0(sp)
+; RV32IFD-NEXT: fld fa1, 8(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmv_d_x:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, a0
-; RV64IFD-NEXT: fmv.d.x ft1, a1
-; RV64IFD-NEXT: fadd.d fa0, ft0, ft1
+; RV64IFD-NEXT: fmv.d.x fa0, a0
+; RV64IFD-NEXT: fmv.d.x fa1, a1
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fmv_d_x:
@@ -1316,15 +1317,15 @@
; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
-; RV32IFD-NEXT: fcvt.d.w ft0, a0
-; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: fcvt.d.w fa0, a0
+; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.w ft0, a0
-; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: fcvt.d.w fa0, a0
+; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_demanded_bits:
@@ -1374,15 +1375,15 @@
; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
-; RV32IFD-NEXT: fcvt.d.wu ft0, a0
-; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: fcvt.d.wu fa0, a0
+; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.wu ft0, a0
-; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: fcvt.d.wu fa0, a0
+; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_demanded_bits:
@@ -1466,12 +1467,12 @@
; RV32IFD-NEXT: beqz a0, .LBB26_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI26_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
-; RV32IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0)
-; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
-; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
-; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: fld fa2, %lo(.LCPI26_1)(a0)
+; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
+; RV32IFD-NEXT: fmin.d fa0, fa0, fa2
+; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB26_2: # %start
; RV32IFD-NEXT: ret
;
@@ -1481,12 +1482,12 @@
; RV64IFD-NEXT: beqz a0, .LBB26_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
+; RV64IFD-NEXT: fld fa1, %lo(.LCPI26_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
-; RV64IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0)
-; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
-; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
-; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: fld fa2, %lo(.LCPI26_1)(a0)
+; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
+; RV64IFD-NEXT: fmin.d fa0, fa0, fa2
+; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB26_2: # %start
; RV64IFD-NEXT: ret
;
@@ -1635,21 +1636,21 @@
; RV32IFD-LABEL: fcvt_wu_s_sat_i16:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI28_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI28_0)(a0)
-; RV32IFD-NEXT: fcvt.d.w ft1, zero
-; RV32IFD-NEXT: fmax.d ft1, fa0, ft1
-; RV32IFD-NEXT: fmin.d ft0, ft1, ft0
-; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI28_0)(a0)
+; RV32IFD-NEXT: fcvt.d.w fa2, zero
+; RV32IFD-NEXT: fmax.d fa0, fa0, fa2
+; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
+; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_s_sat_i16:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI28_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI28_0)(a0)
-; RV64IFD-NEXT: fmv.d.x ft1, zero
-; RV64IFD-NEXT: fmax.d ft1, fa0, ft1
-; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
-; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
+; RV64IFD-NEXT: fld fa1, %lo(.LCPI28_0)(a0)
+; RV64IFD-NEXT: fmv.d.x fa2, zero
+; RV64IFD-NEXT: fmax.d fa0, fa0, fa2
+; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
+; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i16:
@@ -1780,12 +1781,12 @@
; RV32IFD-NEXT: beqz a0, .LBB30_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI30_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
-; RV32IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0)
-; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
-; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
-; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: fld fa2, %lo(.LCPI30_1)(a0)
+; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
+; RV32IFD-NEXT: fmin.d fa0, fa0, fa2
+; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB30_2: # %start
; RV32IFD-NEXT: ret
;
@@ -1795,12 +1796,12 @@
; RV64IFD-NEXT: beqz a0, .LBB30_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
+; RV64IFD-NEXT: fld fa1, %lo(.LCPI30_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
-; RV64IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0)
-; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
-; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
-; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: fld fa2, %lo(.LCPI30_1)(a0)
+; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
+; RV64IFD-NEXT: fmin.d fa0, fa0, fa2
+; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB30_2: # %start
; RV64IFD-NEXT: ret
;
@@ -1951,21 +1952,21 @@
; RV32IFD-LABEL: fcvt_wu_s_sat_i8:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI32_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI32_0)(a0)
-; RV32IFD-NEXT: fcvt.d.w ft1, zero
-; RV32IFD-NEXT: fmax.d ft1, fa0, ft1
-; RV32IFD-NEXT: fmin.d ft0, ft1, ft0
-; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI32_0)(a0)
+; RV32IFD-NEXT: fcvt.d.w fa2, zero
+; RV32IFD-NEXT: fmax.d fa0, fa0, fa2
+; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
+; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_s_sat_i8:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI32_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI32_0)(a0)
-; RV64IFD-NEXT: fmv.d.x ft1, zero
-; RV64IFD-NEXT: fmax.d ft1, fa0, ft1
-; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
-; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
+; RV64IFD-NEXT: fld fa1, %lo(.LCPI32_0)(a0)
+; RV64IFD-NEXT: fmv.d.x fa2, zero
+; RV64IFD-NEXT: fmax.d fa0, fa0, fa2
+; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
+; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -23,15 +23,15 @@
; RV32IFD-LABEL: double_imm_op:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT: fadd.d fa0, fa0, ft0
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: double_imm_op:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
-; RV64IFD-NEXT: fadd.d fa0, fa0, ft0
+; RV64IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret
%1 = fadd double %a, 1.0
ret double %1
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -7,16 +7,16 @@
define dso_local double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fld ft1, 24(a0)
-; RV32IFD-NEXT: fadd.d fa0, ft0, ft1
+; RV32IFD-NEXT: fld fa0, 0(a0)
+; RV32IFD-NEXT: fld fa1, 24(a0)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fld ft0, 0(a0)
-; RV64IFD-NEXT: fld ft1, 24(a0)
-; RV64IFD-NEXT: fadd.d fa0, ft0, ft1
+; RV64IFD-NEXT: fld fa0, 0(a0)
+; RV64IFD-NEXT: fld fa1, 24(a0)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret
%1 = load double, double* %a
%2 = getelementptr double, double* %a, i32 3
@@ -30,16 +30,16 @@
define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fsd:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fsd ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 64(a0)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV32IFD-NEXT: fsd fa0, 0(a0)
+; RV32IFD-NEXT: fsd fa0, 64(a0)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fsd ft0, 0(a0)
-; RV64IFD-NEXT: fsd ft0, 64(a0)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV64IFD-NEXT: fsd fa0, 0(a0)
+; RV64IFD-NEXT: fsd fa0, 64(a0)
; RV64IFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
@@ -58,10 +58,10 @@
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: lui a0, %hi(G)
-; RV32IFD-NEXT: fld ft0, %lo(G)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(G)(a0)
; RV32IFD-NEXT: fsd fa0, %lo(G)(a0)
; RV32IFD-NEXT: addi a0, a0, %lo(G)
-; RV32IFD-NEXT: fld ft0, 72(a0)
+; RV32IFD-NEXT: fld fa1, 72(a0)
; RV32IFD-NEXT: fsd fa0, 72(a0)
; RV32IFD-NEXT: ret
;
@@ -69,10 +69,10 @@
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: lui a0, %hi(G)
-; RV64IFD-NEXT: fld ft0, %lo(G)(a0)
+; RV64IFD-NEXT: fld fa1, %lo(G)(a0)
; RV64IFD-NEXT: fsd fa0, %lo(G)(a0)
; RV64IFD-NEXT: addi a0, a0, %lo(G)
-; RV64IFD-NEXT: fld ft0, 72(a0)
+; RV64IFD-NEXT: fld fa1, 72(a0)
; RV64IFD-NEXT: fsd fa0, 72(a0)
; RV64IFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
@@ -91,8 +91,8 @@
; RV32IFD-LABEL: fld_fsd_constant:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lui a0, 912092
-; RV32IFD-NEXT: fld ft0, -273(a0)
-; RV32IFD-NEXT: fadd.d fa0, fa0, ft0
+; RV32IFD-NEXT: fld fa1, -273(a0)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fsd fa0, -273(a0)
; RV32IFD-NEXT: ret
;
@@ -100,8 +100,8 @@
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, 228023
; RV64IFD-NEXT: slli a0, a0, 2
-; RV64IFD-NEXT: fld ft0, -273(a0)
-; RV64IFD-NEXT: fadd.d fa0, fa0, ft0
+; RV64IFD-NEXT: fld fa1, -273(a0)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fsd fa0, -273(a0)
; RV64IFD-NEXT: ret
%1 = inttoptr i32 3735928559 to double*
@@ -122,8 +122,8 @@
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead@plt
-; RV32IFD-NEXT: fld ft0, 8(sp)
-; RV32IFD-NEXT: fadd.d fa0, ft0, fs0
+; RV32IFD-NEXT: fld fa0, 8(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fs0
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
@@ -137,8 +137,8 @@
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: addi a0, sp, 8
; RV64IFD-NEXT: call notdead@plt
-; RV64IFD-NEXT: fld ft0, 8(sp)
-; RV64IFD-NEXT: fadd.d fa0, ft0, fs0
+; RV64IFD-NEXT: fld fa0, 8(sp)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fs0
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32
@@ -156,8 +156,8 @@
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fsd ft0, 0(sp)
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV32IFD-NEXT: fsd fa0, 0(sp)
; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -168,8 +168,8 @@
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fsd ft0, 0(sp)
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
+; RV64IFD-NEXT: fsd fa0, 0(sp)
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -187,14 +187,14 @@
define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
; RV32IFD-LABEL: fsd_trunc:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.s.d ft0, fa0
-; RV32IFD-NEXT: fsw ft0, 0(a0)
+; RV32IFD-NEXT: fcvt.s.d fa0, fa0
+; RV32IFD-NEXT: fsw fa0, 0(a0)
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd_trunc:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.s.d ft0, fa0
-; RV64IFD-NEXT: fsw ft0, 0(a0)
+; RV64IFD-NEXT: fcvt.s.d fa0, fa0
+; RV64IFD-NEXT: fsw fa0, 0(a0)
; RV64IFD-NEXT: ret
%1 = fptrunc double %b to float
store float %1, float* %a, align 4
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -22,14 +22,14 @@
; RV32IFD-NEXT: call test@plt
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
-; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: fld fa0, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT: flt.d a0, ft0, ft1
+; RV32IFD-NEXT: fld fa2, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT: flt.d a0, fa0, fa1
; RV32IFD-NEXT: not a0, a0
-; RV32IFD-NEXT: flt.d a1, ft2, ft0
+; RV32IFD-NEXT: flt.d a1, fa2, fa0
; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB1_2
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -36,9 +36,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB1_2
@@ -46,8 +46,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB1_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB1_9
; RV32IFD-NEXT: # %bb.3:
@@ -129,8 +129,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB3_2
@@ -138,8 +139,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB3_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI3_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB3_7
@@ -209,9 +210,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI5_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB5_2
@@ -219,8 +220,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB5_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI5_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB5_9
; RV32IFD-NEXT: # %bb.3:
@@ -302,8 +303,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB7_2
@@ -311,8 +313,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB7_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI7_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI7_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB7_7
@@ -382,9 +384,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI9_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB9_2
@@ -392,8 +394,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB9_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI9_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB9_9
; RV32IFD-NEXT: # %bb.3:
@@ -475,8 +477,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB11_2
@@ -484,8 +487,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB11_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB11_7
@@ -555,9 +558,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI13_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB13_2
@@ -565,8 +568,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB13_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI13_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB13_9
; RV32IFD-NEXT: # %bb.3:
@@ -648,8 +651,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB15_2
@@ -657,8 +661,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB15_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI15_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI15_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB15_7
@@ -728,9 +732,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_0)(a0)
+; RV32IFD-NEXT: fld fa1, %lo(.LCPI17_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB17_2
@@ -738,8 +742,8 @@
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB17_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI17_1)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_1)(a0)
-; RV32IFD-NEXT: flt.d a3, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI17_1)(a0)
+; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB17_9
; RV32IFD-NEXT: # %bb.3:
@@ -821,8 +825,9 @@
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: fmv.d fs0, fa0
-; RV32IFD-NEXT: fcvt.d.w ft0, zero
-; RV32IFD-NEXT: fle.d s0, ft0, fa0
+; RV32IFD-NEXT: fcvt.d.w fa0, zero
+; RV32IFD-NEXT: fle.d s0, fa0, fs0
+; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB19_2
@@ -830,8 +835,8 @@
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB19_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI19_0)(a0)
-; RV32IFD-NEXT: flt.d a4, ft0, fs0
+; RV32IFD-NEXT: fld fa0, %lo(.LCPI19_0)(a0)
+; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB19_7
diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
--- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
+++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
@@ -11,22 +11,22 @@
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
-; RV32IFD-NEXT: fld ft0, 16(sp)
+; RV32IFD-NEXT: fld fa0, 16(sp)
; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1
-; RV32IFD-NEXT: fsd ft0, 16(sp)
+; RV32IFD-NEXT: fsd fa0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
-; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
+; RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func@plt
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
-; RV32IFD-NEXT: fld ft0, 16(sp)
-; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
-; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
+; RV32IFD-NEXT: fld fa0, 16(sp)
+; RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
+; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: .LBB0_2: # %return
-; RV32IFD-NEXT: fsd ft0, 16(sp)
+; RV32IFD-NEXT: fsd fa0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@@ -38,18 +38,18 @@
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sext.w a2, a1
-; RV64IFD-NEXT: fmv.d.x ft0, a0
+; RV64IFD-NEXT: fmv.d.x fa0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addiw a1, a1, -1
-; RV64IFD-NEXT: fmv.x.d a0, ft0
-; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fmv.x.d a0, fa0
+; RV64IFD-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func@plt
-; RV64IFD-NEXT: fmv.d.x ft0, a0
-; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
-; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
+; RV64IFD-NEXT: fmv.d.x fa0, a0
+; RV64IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: .LBB0_2: # %return
-; RV64IFD-NEXT: fmv.x.d a0, ft0
+; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/float-arith-strict.ll b/llvm/test/CodeGen/RISCV/float-arith-strict.ll
--- a/llvm/test/CodeGen/RISCV/float-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith-strict.ll
@@ -293,16 +293,16 @@
define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
@@ -357,18 +357,18 @@
define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
@@ -437,18 +437,18 @@
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmadd_s_2:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s_2:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
@@ -517,16 +517,16 @@
define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa0, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa0, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
@@ -579,16 +579,16 @@
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmsub_s_2:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s_2:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -214,16 +214,16 @@
define i32 @fneg_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fneg_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa0
-; RV32IF-NEXT: fneg.s ft1, ft0
-; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: fadd.s fa0, fa0, fa0
+; RV32IF-NEXT: fneg.s fa1, fa0
+; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fneg_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa0
-; RV64IF-NEXT: fneg.s ft1, ft0
-; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: fadd.s fa0, fa0, fa0
+; RV64IF-NEXT: fneg.s fa1, fa0
+; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fneg_s:
@@ -265,14 +265,14 @@
define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fsgnjn_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fsgnjn.s fa0, fa0, ft0
+; RV32IF-NEXT: fadd.s fa1, fa0, fa1
+; RV32IF-NEXT: fsgnjn.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fsgnjn_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fsgnjn.s fa0, fa0, ft0
+; RV64IF-NEXT: fadd.s fa1, fa0, fa1
+; RV64IF-NEXT: fsgnjn.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
@@ -323,16 +323,16 @@
define float @fabs_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fabs_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fabs.s ft1, ft0
-; RV32IF-NEXT: fadd.s fa0, ft1, ft0
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
+; RV32IF-NEXT: fabs.s fa1, fa0
+; RV32IF-NEXT: fadd.s fa0, fa1, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fabs_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fabs.s ft1, ft0
-; RV64IF-NEXT: fadd.s fa0, ft1, ft0
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
+; RV64IF-NEXT: fabs.s fa1, fa0
+; RV64IF-NEXT: fadd.s fa0, fa1, fa0
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fabs_s:
@@ -471,16 +471,16 @@
define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
@@ -535,18 +535,18 @@
define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
@@ -615,18 +615,18 @@
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_2:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s_2:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
@@ -695,16 +695,16 @@
define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa0, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa0, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
@@ -757,16 +757,16 @@
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_2:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s_2:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
@@ -864,16 +864,16 @@
define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s_contract:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmsub_s_contract:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
@@ -934,20 +934,20 @@
define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_contract:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft2, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fadd.s fa2, fa2, fa3
+; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s_contract:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft2, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fadd.s fa2, fa2, fa3
+; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
@@ -1029,18 +1029,18 @@
define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_contract:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2
+; RV32IF-NEXT: fmv.w.x fa3, zero
+; RV32IF-NEXT: fadd.s fa0, fa0, fa3
+; RV32IF-NEXT: fadd.s fa1, fa1, fa3
+; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s_contract:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2
+; RV64IF-NEXT: fmv.w.x fa3, zero
+; RV64IF-NEXT: fadd.s fa0, fa0, fa3
+; RV64IF-NEXT: fadd.s fa1, fa1, fa3
+; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
diff --git a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
@@ -17,42 +17,42 @@
define float @bitcast_and(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_and:
; RV32F: # %bb.0:
-; RV32F-NEXT: fmv.w.x ft0, a1
-; RV32F-NEXT: fmv.w.x ft1, a0
-; RV32F-NEXT: fadd.s ft0, ft1, ft0
-; RV32F-NEXT: fabs.s ft0, ft0
-; RV32F-NEXT: fadd.s ft0, ft1, ft0
-; RV32F-NEXT: fmv.x.w a0, ft0
+; RV32F-NEXT: fmv.w.x fa0, a1
+; RV32F-NEXT: fmv.w.x fa1, a0
+; RV32F-NEXT: fadd.s fa0, fa1, fa0
+; RV32F-NEXT: fabs.s fa0, fa0
+; RV32F-NEXT: fadd.s fa0, fa1, fa0
+; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_and:
; RV32FD: # %bb.0:
-; RV32FD-NEXT: fmv.w.x ft0, a1
-; RV32FD-NEXT: fmv.w.x ft1, a0
-; RV32FD-NEXT: fadd.s ft0, ft1, ft0
-; RV32FD-NEXT: fabs.s ft0, ft0
-; RV32FD-NEXT: fadd.s ft0, ft1, ft0
-; RV32FD-NEXT: fmv.x.w a0, ft0
+; RV32FD-NEXT: fmv.w.x fa0, a1
+; RV32FD-NEXT: fmv.w.x fa1, a0
+; RV32FD-NEXT: fadd.s fa0, fa1, fa0
+; RV32FD-NEXT: fabs.s fa0, fa0
+; RV32FD-NEXT: fadd.s fa0, fa1, fa0
+; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_and:
; RV64F: # %bb.0:
-; RV64F-NEXT: fmv.w.x ft0, a1
-; RV64F-NEXT: fmv.w.x ft1, a0
-; RV64F-NEXT: fadd.s ft0, ft1, ft0
-; RV64F-NEXT: fabs.s ft0, ft0
-; RV64F-NEXT: fadd.s ft0, ft1, ft0
-; RV64F-NEXT: fmv.x.w a0, ft0
+; RV64F-NEXT: fmv.w.x fa0, a1
+; RV64F-NEXT: fmv.w.x fa1, a0
+; RV64F-NEXT: fadd.s fa0, fa1, fa0
+; RV64F-NEXT: fabs.s fa0, fa0
+; RV64F-NEXT: fadd.s fa0, fa1, fa0
+; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_and:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.w.x ft0, a1
-; RV64FD-NEXT: fmv.w.x ft1, a0
-; RV64FD-NEXT: fadd.s ft0, ft1, ft0
-; RV64FD-NEXT: fabs.s ft0, ft0
-; RV64FD-NEXT: fadd.s ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.w a0, ft0
+; RV64FD-NEXT: fmv.w.x fa0, a1
+; RV64FD-NEXT: fmv.w.x fa1, a0
+; RV64FD-NEXT: fadd.s fa0, fa1, fa0
+; RV64FD-NEXT: fabs.s fa0, fa0
+; RV64FD-NEXT: fadd.s fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret
%a3 = fadd float %a1, %a2
%bc1 = bitcast float %a3 to i32
@@ -89,14 +89,14 @@
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
-; RV32FD-NEXT: fld ft0, 8(sp)
+; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
-; RV32FD-NEXT: fld ft1, 8(sp)
-; RV32FD-NEXT: fadd.d ft0, ft1, ft0
-; RV32FD-NEXT: fabs.d ft0, ft0
-; RV32FD-NEXT: fadd.d ft0, ft1, ft0
-; RV32FD-NEXT: fsd ft0, 8(sp)
+; RV32FD-NEXT: fld fa1, 8(sp)
+; RV32FD-NEXT: fadd.d fa0, fa1, fa0
+; RV32FD-NEXT: fabs.d fa0, fa0
+; RV32FD-NEXT: fadd.d fa0, fa1, fa0
+; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
@@ -120,12 +120,12 @@
;
; RV64FD-LABEL: bitcast_double_and:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.d.x ft0, a1
-; RV64FD-NEXT: fmv.d.x ft1, a0
-; RV64FD-NEXT: fadd.d ft0, ft1, ft0
-; RV64FD-NEXT: fabs.d ft0, ft0
-; RV64FD-NEXT: fadd.d ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.d a0, ft0
+; RV64FD-NEXT: fmv.d.x fa0, a1
+; RV64FD-NEXT: fmv.d.x fa1, a0
+; RV64FD-NEXT: fadd.d fa0, fa1, fa0
+; RV64FD-NEXT: fabs.d fa0, fa0
+; RV64FD-NEXT: fadd.d fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret
%a3 = fadd double %a1, %a2
%bc1 = bitcast double %a3 to i64
@@ -139,42 +139,42 @@
define float @bitcast_xor(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_xor:
; RV32F: # %bb.0:
-; RV32F-NEXT: fmv.w.x ft0, a1
-; RV32F-NEXT: fmv.w.x ft1, a0
-; RV32F-NEXT: fmul.s ft0, ft1, ft0
-; RV32F-NEXT: fneg.s ft0, ft0
-; RV32F-NEXT: fmul.s ft0, ft1, ft0
-; RV32F-NEXT: fmv.x.w a0, ft0
+; RV32F-NEXT: fmv.w.x fa0, a1
+; RV32F-NEXT: fmv.w.x fa1, a0
+; RV32F-NEXT: fmul.s fa0, fa1, fa0
+; RV32F-NEXT: fneg.s fa0, fa0
+; RV32F-NEXT: fmul.s fa0, fa1, fa0
+; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_xor:
; RV32FD: # %bb.0:
-; RV32FD-NEXT: fmv.w.x ft0, a1
-; RV32FD-NEXT: fmv.w.x ft1, a0
-; RV32FD-NEXT: fmul.s ft0, ft1, ft0
-; RV32FD-NEXT: fneg.s ft0, ft0
-; RV32FD-NEXT: fmul.s ft0, ft1, ft0
-; RV32FD-NEXT: fmv.x.w a0, ft0
+; RV32FD-NEXT: fmv.w.x fa0, a1
+; RV32FD-NEXT: fmv.w.x fa1, a0
+; RV32FD-NEXT: fmul.s fa0, fa1, fa0
+; RV32FD-NEXT: fneg.s fa0, fa0
+; RV32FD-NEXT: fmul.s fa0, fa1, fa0
+; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_xor:
; RV64F: # %bb.0:
-; RV64F-NEXT: fmv.w.x ft0, a1
-; RV64F-NEXT: fmv.w.x ft1, a0
-; RV64F-NEXT: fmul.s ft0, ft1, ft0
-; RV64F-NEXT: fneg.s ft0, ft0
-; RV64F-NEXT: fmul.s ft0, ft1, ft0
-; RV64F-NEXT: fmv.x.w a0, ft0
+; RV64F-NEXT: fmv.w.x fa0, a1
+; RV64F-NEXT: fmv.w.x fa1, a0
+; RV64F-NEXT: fmul.s fa0, fa1, fa0
+; RV64F-NEXT: fneg.s fa0, fa0
+; RV64F-NEXT: fmul.s fa0, fa1, fa0
+; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_xor:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.w.x ft0, a1
-; RV64FD-NEXT: fmv.w.x ft1, a0
-; RV64FD-NEXT: fmul.s ft0, ft1, ft0
-; RV64FD-NEXT: fneg.s ft0, ft0
-; RV64FD-NEXT: fmul.s ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.w a0, ft0
+; RV64FD-NEXT: fmv.w.x fa0, a1
+; RV64FD-NEXT: fmv.w.x fa1, a0
+; RV64FD-NEXT: fmul.s fa0, fa1, fa0
+; RV64FD-NEXT: fneg.s fa0, fa0
+; RV64FD-NEXT: fmul.s fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32
@@ -211,14 +211,14 @@
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
-; RV32FD-NEXT: fld ft0, 8(sp)
+; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
-; RV32FD-NEXT: fld ft1, 8(sp)
-; RV32FD-NEXT: fmul.d ft0, ft1, ft0
-; RV32FD-NEXT: fneg.d ft0, ft0
-; RV32FD-NEXT: fmul.d ft0, ft1, ft0
-; RV32FD-NEXT: fsd ft0, 8(sp)
+; RV32FD-NEXT: fld fa1, 8(sp)
+; RV32FD-NEXT: fmul.d fa0, fa1, fa0
+; RV32FD-NEXT: fneg.d fa0, fa0
+; RV32FD-NEXT: fmul.d fa0, fa1, fa0
+; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
@@ -243,12 +243,12 @@
;
; RV64FD-LABEL: bitcast_double_xor:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.d.x ft0, a1
-; RV64FD-NEXT: fmv.d.x ft1, a0
-; RV64FD-NEXT: fmul.d ft0, ft1, ft0
-; RV64FD-NEXT: fneg.d ft0, ft0
-; RV64FD-NEXT: fmul.d ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.d a0, ft0
+; RV64FD-NEXT: fmv.d.x fa0, a1
+; RV64FD-NEXT: fmv.d.x fa1, a0
+; RV64FD-NEXT: fmul.d fa0, fa1, fa0
+; RV64FD-NEXT: fneg.d fa0, fa0
+; RV64FD-NEXT: fmul.d fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64
@@ -261,46 +261,46 @@
define float @bitcast_or(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_or:
; RV32F: # %bb.0:
-; RV32F-NEXT: fmv.w.x ft0, a1
-; RV32F-NEXT: fmv.w.x ft1, a0
-; RV32F-NEXT: fmul.s ft0, ft1, ft0
-; RV32F-NEXT: fabs.s ft0, ft0
-; RV32F-NEXT: fneg.s ft0, ft0
-; RV32F-NEXT: fmul.s ft0, ft1, ft0
-; RV32F-NEXT: fmv.x.w a0, ft0
+; RV32F-NEXT: fmv.w.x fa0, a1
+; RV32F-NEXT: fmv.w.x fa1, a0
+; RV32F-NEXT: fmul.s fa0, fa1, fa0
+; RV32F-NEXT: fabs.s fa0, fa0
+; RV32F-NEXT: fneg.s fa0, fa0
+; RV32F-NEXT: fmul.s fa0, fa1, fa0
+; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_or:
; RV32FD: # %bb.0:
-; RV32FD-NEXT: fmv.w.x ft0, a1
-; RV32FD-NEXT: fmv.w.x ft1, a0
-; RV32FD-NEXT: fmul.s ft0, ft1, ft0
-; RV32FD-NEXT: fabs.s ft0, ft0
-; RV32FD-NEXT: fneg.s ft0, ft0
-; RV32FD-NEXT: fmul.s ft0, ft1, ft0
-; RV32FD-NEXT: fmv.x.w a0, ft0
+; RV32FD-NEXT: fmv.w.x fa0, a1
+; RV32FD-NEXT: fmv.w.x fa1, a0
+; RV32FD-NEXT: fmul.s fa0, fa1, fa0
+; RV32FD-NEXT: fabs.s fa0, fa0
+; RV32FD-NEXT: fneg.s fa0, fa0
+; RV32FD-NEXT: fmul.s fa0, fa1, fa0
+; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_or:
; RV64F: # %bb.0:
-; RV64F-NEXT: fmv.w.x ft0, a1
-; RV64F-NEXT: fmv.w.x ft1, a0
-; RV64F-NEXT: fmul.s ft0, ft1, ft0
-; RV64F-NEXT: fabs.s ft0, ft0
-; RV64F-NEXT: fneg.s ft0, ft0
-; RV64F-NEXT: fmul.s ft0, ft1, ft0
-; RV64F-NEXT: fmv.x.w a0, ft0
+; RV64F-NEXT: fmv.w.x fa0, a1
+; RV64F-NEXT: fmv.w.x fa1, a0
+; RV64F-NEXT: fmul.s fa0, fa1, fa0
+; RV64F-NEXT: fabs.s fa0, fa0
+; RV64F-NEXT: fneg.s fa0, fa0
+; RV64F-NEXT: fmul.s fa0, fa1, fa0
+; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_or:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.w.x ft0, a1
-; RV64FD-NEXT: fmv.w.x ft1, a0
-; RV64FD-NEXT: fmul.s ft0, ft1, ft0
-; RV64FD-NEXT: fabs.s ft0, ft0
-; RV64FD-NEXT: fneg.s ft0, ft0
-; RV64FD-NEXT: fmul.s ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.w a0, ft0
+; RV64FD-NEXT: fmv.w.x fa0, a1
+; RV64FD-NEXT: fmv.w.x fa1, a0
+; RV64FD-NEXT: fmul.s fa0, fa1, fa0
+; RV64FD-NEXT: fabs.s fa0, fa0
+; RV64FD-NEXT: fneg.s fa0, fa0
+; RV64FD-NEXT: fmul.s fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32
@@ -337,15 +337,15 @@
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
-; RV32FD-NEXT: fld ft0, 8(sp)
+; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
-; RV32FD-NEXT: fld ft1, 8(sp)
-; RV32FD-NEXT: fmul.d ft0, ft1, ft0
-; RV32FD-NEXT: fabs.d ft0, ft0
-; RV32FD-NEXT: fneg.d ft0, ft0
-; RV32FD-NEXT: fmul.d ft0, ft1, ft0
-; RV32FD-NEXT: fsd ft0, 8(sp)
+; RV32FD-NEXT: fld fa1, 8(sp)
+; RV32FD-NEXT: fmul.d fa0, fa1, fa0
+; RV32FD-NEXT: fabs.d fa0, fa0
+; RV32FD-NEXT: fneg.d fa0, fa0
+; RV32FD-NEXT: fmul.d fa0, fa1, fa0
+; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
@@ -370,13 +370,13 @@
;
; RV64FD-LABEL: bitcast_double_or:
; RV64FD: # %bb.0:
-; RV64FD-NEXT: fmv.d.x ft0, a1
-; RV64FD-NEXT: fmv.d.x ft1, a0
-; RV64FD-NEXT: fmul.d ft0, ft1, ft0
-; RV64FD-NEXT: fabs.d ft0, ft0
-; RV64FD-NEXT: fneg.d ft0, ft0
-; RV64FD-NEXT: fmul.d ft0, ft1, ft0
-; RV64FD-NEXT: fmv.x.d a0, ft0
+; RV64FD-NEXT: fmv.d.x fa0, a1
+; RV64FD-NEXT: fmv.d.x fa1, a0
+; RV64FD-NEXT: fmul.d fa0, fa1, fa0
+; RV64FD-NEXT: fabs.d fa0, fa0
+; RV64FD-NEXT: fneg.d fa0, fa0
+; RV64FD-NEXT: fmul.d fa0, fa1, fa0
+; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64
diff --git a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
@@ -93,10 +93,10 @@
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: xor a1, a1, a2
-; RV32IF-NEXT: fmv.w.x ft0, a1
-; RV32IF-NEXT: fmv.w.x ft1, a0
-; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
-; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: fmv.w.x fa0, a1
+; RV32IF-NEXT: fmv.w.x fa1, a0
+; RV32IF-NEXT: fsgnj.s fa0, fa1, fa0
+; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret
;
; RV64I-LABEL: fcopysign_fneg:
@@ -111,10 +111,10 @@
;
; RV64IF-LABEL: fcopysign_fneg:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fmv.w.x fa0, a1
+; RV64IF-NEXT: fmv.w.x fa1, a0
+; RV64IF-NEXT: fsgnjn.s fa0, fa1, fa0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = fneg float %b
%2 = call float @llvm.copysign.f32(float %a, float %1)
diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
@@ -565,15 +565,15 @@
; RV32IF-LABEL: fcvt_s_w_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: fcvt.s.w ft0, a0
-; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: fcvt.s.w fa0, a0
+; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_demanded_bits:
@@ -622,15 +622,15 @@
; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: fcvt.s.wu ft0, a0
-; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: fcvt.s.wu fa0, a0
+; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_demanded_bits:
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -345,14 +345,14 @@
define i32 @fmv_x_w(float %a, float %b) nounwind {
; RV32IF-LABEL: fmv_x_w:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
+; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmv_x_w:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fmv_x_w:
@@ -521,16 +521,16 @@
define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV32IF-LABEL: fmv_w_x:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: fmv.w.x ft1, a1
-; RV32IF-NEXT: fadd.s fa0, ft0, ft1
+; RV32IF-NEXT: fmv.w.x fa0, a0
+; RV32IF-NEXT: fmv.w.x fa1, a1
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmv_w_x:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fmv.w.x ft1, a1
-; RV64IF-NEXT: fadd.s fa0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fmv.w.x fa1, a1
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fmv_w_x:
@@ -601,9 +601,9 @@
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: lui a0, %hi(.LCPI12_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI12_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI12_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB12_2
@@ -611,8 +611,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB12_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI12_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI12_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI12_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB12_9
; RV32IF-NEXT: # %bb.3: # %start
@@ -834,8 +834,9 @@
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB14_2
@@ -843,8 +844,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB14_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI14_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI14_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI14_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB14_7
@@ -1183,15 +1184,15 @@
; RV32IF-LABEL: fcvt_s_w_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: fcvt.s.w ft0, a0
-; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: fcvt.s.w fa0, a0
+; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_demanded_bits:
@@ -1240,15 +1241,15 @@
; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: fcvt.s.wu ft0, a0
-; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: fcvt.s.wu fa0, a0
+; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_demanded_bits:
@@ -1331,12 +1332,12 @@
; RV32IF-NEXT: beqz a0, .LBB24_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI24_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI24_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI24_1)
-; RV32IF-NEXT: flw ft1, %lo(.LCPI24_1)(a0)
-; RV32IF-NEXT: fmax.s ft0, fa0, ft0
-; RV32IF-NEXT: fmin.s ft0, ft0, ft1
-; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: flw fa2, %lo(.LCPI24_1)(a0)
+; RV32IF-NEXT: fmax.s fa0, fa0, fa1
+; RV32IF-NEXT: fmin.s fa0, fa0, fa2
+; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB24_2: # %start
; RV32IF-NEXT: ret
;
@@ -1346,12 +1347,12 @@
; RV64IF-NEXT: beqz a0, .LBB24_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI24_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0)
+; RV64IF-NEXT: flw fa1, %lo(.LCPI24_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI24_1)
-; RV64IF-NEXT: flw ft1, %lo(.LCPI24_1)(a0)
-; RV64IF-NEXT: fmax.s ft0, fa0, ft0
-; RV64IF-NEXT: fmin.s ft0, ft0, ft1
-; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: flw fa2, %lo(.LCPI24_1)(a0)
+; RV64IF-NEXT: fmax.s fa0, fa0, fa1
+; RV64IF-NEXT: fmin.s fa0, fa0, fa2
+; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: .LBB24_2: # %start
; RV64IF-NEXT: ret
;
@@ -1488,21 +1489,21 @@
; RV32IF-LABEL: fcvt_wu_s_sat_i16:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI26_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI26_0)(a0)
-; RV32IF-NEXT: fmv.w.x ft1, zero
-; RV32IF-NEXT: fmax.s ft1, fa0, ft1
-; RV32IF-NEXT: fmin.s ft0, ft1, ft0
-; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IF-NEXT: flw fa1, %lo(.LCPI26_0)(a0)
+; RV32IF-NEXT: fmv.w.x fa2, zero
+; RV32IF-NEXT: fmax.s fa0, fa0, fa2
+; RV32IF-NEXT: fmin.s fa0, fa0, fa1
+; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_sat_i16:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, %hi(.LCPI26_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI26_0)(a0)
-; RV64IF-NEXT: fmv.w.x ft1, zero
-; RV64IF-NEXT: fmax.s ft1, fa0, ft1
-; RV64IF-NEXT: fmin.s ft0, ft1, ft0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: flw fa1, %lo(.LCPI26_0)(a0)
+; RV64IF-NEXT: fmv.w.x fa2, zero
+; RV64IF-NEXT: fmax.s fa0, fa0, fa2
+; RV64IF-NEXT: fmin.s fa0, fa0, fa1
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i16:
@@ -1623,12 +1624,12 @@
; RV32IF-NEXT: beqz a0, .LBB28_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI28_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI28_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI28_1)
-; RV32IF-NEXT: flw ft1, %lo(.LCPI28_1)(a0)
-; RV32IF-NEXT: fmax.s ft0, fa0, ft0
-; RV32IF-NEXT: fmin.s ft0, ft0, ft1
-; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: flw fa2, %lo(.LCPI28_1)(a0)
+; RV32IF-NEXT: fmax.s fa0, fa0, fa1
+; RV32IF-NEXT: fmin.s fa0, fa0, fa2
+; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB28_2: # %start
; RV32IF-NEXT: ret
;
@@ -1638,12 +1639,12 @@
; RV64IF-NEXT: beqz a0, .LBB28_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI28_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
+; RV64IF-NEXT: flw fa1, %lo(.LCPI28_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI28_1)
-; RV64IF-NEXT: flw ft1, %lo(.LCPI28_1)(a0)
-; RV64IF-NEXT: fmax.s ft0, fa0, ft0
-; RV64IF-NEXT: fmin.s ft0, ft0, ft1
-; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: flw fa2, %lo(.LCPI28_1)(a0)
+; RV64IF-NEXT: fmax.s fa0, fa0, fa1
+; RV64IF-NEXT: fmin.s fa0, fa0, fa2
+; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: .LBB28_2: # %start
; RV64IF-NEXT: ret
;
@@ -1778,21 +1779,21 @@
; RV32IF-LABEL: fcvt_wu_s_sat_i8:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI30_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI30_0)(a0)
-; RV32IF-NEXT: fmv.w.x ft1, zero
-; RV32IF-NEXT: fmax.s ft1, fa0, ft1
-; RV32IF-NEXT: fmin.s ft0, ft1, ft0
-; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IF-NEXT: flw fa1, %lo(.LCPI30_0)(a0)
+; RV32IF-NEXT: fmv.w.x fa2, zero
+; RV32IF-NEXT: fmax.s fa0, fa0, fa2
+; RV32IF-NEXT: fmin.s fa0, fa0, fa1
+; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_sat_i8:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, %hi(.LCPI30_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI30_0)(a0)
-; RV64IF-NEXT: fmv.w.x ft1, zero
-; RV64IF-NEXT: fmax.s ft1, fa0, ft1
-; RV64IF-NEXT: fmin.s ft0, ft1, ft0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: flw fa1, %lo(.LCPI30_0)(a0)
+; RV64IF-NEXT: fmv.w.x fa2, zero
+; RV64IF-NEXT: fmax.s fa0, fa0, fa2
+; RV64IF-NEXT: fmin.s fa0, fa0, fa1
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -24,15 +24,15 @@
; RV32IF-LABEL: float_imm_op:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV32IF-NEXT: fadd.s fa0, fa0, ft0
+; RV32IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_imm_op:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV64IF-NEXT: fadd.s fa0, fa0, ft0
+; RV64IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll
--- a/llvm/test/CodeGen/RISCV/float-mem.ll
+++ b/llvm/test/CodeGen/RISCV/float-mem.ll
@@ -7,16 +7,16 @@
define dso_local float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: flw ft0, 0(a0)
-; RV32IF-NEXT: flw ft1, 12(a0)
-; RV32IF-NEXT: fadd.s fa0, ft0, ft1
+; RV32IF-NEXT: flw fa0, 0(a0)
+; RV32IF-NEXT: flw fa1, 12(a0)
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: flw ft0, 0(a0)
-; RV64IF-NEXT: flw ft1, 12(a0)
-; RV64IF-NEXT: fadd.s fa0, ft0, ft1
+; RV64IF-NEXT: flw fa0, 0(a0)
+; RV64IF-NEXT: flw fa1, 12(a0)
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret
%1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3
@@ -32,16 +32,16 @@
; for the soft float ABI
; RV32IF-LABEL: fsw:
; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fsw ft0, 0(a0)
-; RV32IF-NEXT: fsw ft0, 32(a0)
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
+; RV32IF-NEXT: fsw fa0, 0(a0)
+; RV32IF-NEXT: fsw fa0, 32(a0)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fsw:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fsw ft0, 0(a0)
-; RV64IF-NEXT: fsw ft0, 32(a0)
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
+; RV64IF-NEXT: fsw fa0, 0(a0)
+; RV64IF-NEXT: fsw fa0, 32(a0)
; RV64IF-NEXT: ret
%1 = fadd float %b, %c
store float %1, float* %a
@@ -60,10 +60,10 @@
; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: lui a0, %hi(G)
-; RV32IF-NEXT: flw ft0, %lo(G)(a0)
+; RV32IF-NEXT: flw fa1, %lo(G)(a0)
; RV32IF-NEXT: fsw fa0, %lo(G)(a0)
; RV32IF-NEXT: addi a0, a0, %lo(G)
-; RV32IF-NEXT: flw ft0, 36(a0)
+; RV32IF-NEXT: flw fa1, 36(a0)
; RV32IF-NEXT: fsw fa0, 36(a0)
; RV32IF-NEXT: ret
;
@@ -71,10 +71,10 @@
; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: lui a0, %hi(G)
-; RV64IF-NEXT: flw ft0, %lo(G)(a0)
+; RV64IF-NEXT: flw fa1, %lo(G)(a0)
; RV64IF-NEXT: fsw fa0, %lo(G)(a0)
; RV64IF-NEXT: addi a0, a0, %lo(G)
-; RV64IF-NEXT: flw ft0, 36(a0)
+; RV64IF-NEXT: flw fa1, 36(a0)
; RV64IF-NEXT: fsw fa0, 36(a0)
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
@@ -91,8 +91,8 @@
; RV32IF-LABEL: flw_fsw_constant:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, 912092
-; RV32IF-NEXT: flw ft0, -273(a0)
-; RV32IF-NEXT: fadd.s fa0, fa0, ft0
+; RV32IF-NEXT: flw fa1, -273(a0)
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fsw fa0, -273(a0)
; RV32IF-NEXT: ret
;
@@ -100,8 +100,8 @@
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, 228023
; RV64IF-NEXT: slli a0, a0, 2
-; RV64IF-NEXT: flw ft0, -273(a0)
-; RV64IF-NEXT: fadd.s fa0, fa0, ft0
+; RV64IF-NEXT: flw fa1, -273(a0)
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fsw fa0, -273(a0)
; RV64IF-NEXT: ret
%1 = inttoptr i32 3735928559 to float*
@@ -122,8 +122,8 @@
; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: addi a0, sp, 4
; RV32IF-NEXT: call notdead@plt
-; RV32IF-NEXT: flw ft0, 4(sp)
-; RV32IF-NEXT: fadd.s fa0, ft0, fs0
+; RV32IF-NEXT: flw fa0, 4(sp)
+; RV32IF-NEXT: fadd.s fa0, fa0, fs0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
@@ -137,8 +137,8 @@
; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: mv a0, sp
; RV64IF-NEXT: call notdead@plt
-; RV64IF-NEXT: flw ft0, 0(sp)
-; RV64IF-NEXT: fadd.s fa0, ft0, fs0
+; RV64IF-NEXT: flw fa0, 0(sp)
+; RV64IF-NEXT: fadd.s fa0, fa0, fs0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
@@ -156,8 +156,8 @@
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fsw ft0, 8(sp)
+; RV32IF-NEXT: fadd.s fa0, fa0, fa1
+; RV32IF-NEXT: fsw fa0, 8(sp)
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -168,8 +168,8 @@
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fsw ft0, 4(sp)
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
+; RV64IF-NEXT: fsw fa0, 4(sp)
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
--- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
@@ -36,9 +36,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB1_2
@@ -46,8 +46,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB1_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI1_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI1_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB1_9
; RV32IF-NEXT: # %bb.3:
@@ -129,8 +129,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB3_2
@@ -138,8 +139,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB3_7
@@ -209,9 +210,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI5_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI5_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI5_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB5_2
@@ -219,8 +220,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB5_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI5_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI5_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI5_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB5_9
; RV32IF-NEXT: # %bb.3:
@@ -302,8 +303,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB7_2
@@ -311,8 +313,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB7_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI7_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB7_7
@@ -382,9 +384,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI9_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI9_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB9_2
@@ -392,8 +394,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB9_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI9_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI9_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI9_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB9_9
; RV32IF-NEXT: # %bb.3:
@@ -475,8 +477,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB11_2
@@ -484,8 +487,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB11_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI11_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI11_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI11_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB11_7
@@ -555,9 +558,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI13_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI13_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI13_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB13_2
@@ -565,8 +568,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB13_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI13_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI13_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI13_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB13_9
; RV32IF-NEXT: # %bb.3:
@@ -648,8 +651,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB15_2
@@ -657,8 +661,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB15_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI15_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI15_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI15_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB15_7
@@ -728,9 +732,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI17_0)(a0)
+; RV32IF-NEXT: flw fa1, %lo(.LCPI17_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB17_2
@@ -738,8 +742,8 @@
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB17_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI17_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI17_1)(a0)
-; RV32IF-NEXT: flt.s a3, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI17_1)(a0)
+; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB17_9
; RV32IF-NEXT: # %bb.3:
@@ -821,8 +825,9 @@
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: fmv.s fs0, fa0
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fle.s s0, ft0, fa0
+; RV32IF-NEXT: fmv.w.x fa0, zero
+; RV32IF-NEXT: fle.s s0, fa0, fs0
+; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB19_2
@@ -830,8 +835,8 @@
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI19_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI19_0)(a0)
-; RV32IF-NEXT: flt.s a4, ft0, fs0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI19_0)(a0)
+; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB19_7
diff --git a/llvm/test/CodeGen/RISCV/fp-imm.ll b/llvm/test/CodeGen/RISCV/fp-imm.ll
--- a/llvm/test/CodeGen/RISCV/fp-imm.ll
+++ b/llvm/test/CodeGen/RISCV/fp-imm.ll
@@ -34,26 +34,26 @@
define float @f32_negative_zero(float *%pf) nounwind {
; RV32F-LABEL: f32_negative_zero:
; RV32F: # %bb.0:
-; RV32F-NEXT: fmv.w.x ft0, zero
-; RV32F-NEXT: fneg.s fa0, ft0
+; RV32F-NEXT: fmv.w.x fa0, zero
+; RV32F-NEXT: fneg.s fa0, fa0
; RV32F-NEXT: ret
;
; RV32D-LABEL: f32_negative_zero:
; RV32D: # %bb.0:
-; RV32D-NEXT: fmv.w.x ft0, zero
-; RV32D-NEXT: fneg.s fa0, ft0
+; RV32D-NEXT: fmv.w.x fa0, zero
+; RV32D-NEXT: fneg.s fa0, fa0
; RV32D-NEXT: ret
;
; RV64F-LABEL: f32_negative_zero:
; RV64F: # %bb.0:
-; RV64F-NEXT: fmv.w.x ft0, zero
-; RV64F-NEXT: fneg.s fa0, ft0
+; RV64F-NEXT: fmv.w.x fa0, zero
+; RV64F-NEXT: fneg.s fa0, fa0
; RV64F-NEXT: ret
;
; RV64D-LABEL: f32_negative_zero:
; RV64D: # %bb.0:
-; RV64D-NEXT: fmv.w.x ft0, zero
-; RV64D-NEXT: fneg.s fa0, ft0
+; RV64D-NEXT: fmv.w.x fa0, zero
+; RV64D-NEXT: fneg.s fa0, fa0
; RV64D-NEXT: ret
ret float -0.0
}
@@ -91,8 +91,8 @@
;
; RV32D-LABEL: f64_negative_zero:
; RV32D: # %bb.0:
-; RV32D-NEXT: fcvt.d.w ft0, zero
-; RV32D-NEXT: fneg.d fa0, ft0
+; RV32D-NEXT: fcvt.d.w fa0, zero
+; RV32D-NEXT: fneg.d fa0, fa0
; RV32D-NEXT: ret
;
; RV64F-LABEL: f64_negative_zero:
@@ -103,8 +103,8 @@
;
; RV64D-LABEL: f64_negative_zero:
; RV64D: # %bb.0:
-; RV64D-NEXT: fmv.d.x ft0, zero
-; RV64D-NEXT: fneg.d fa0, ft0
+; RV64D-NEXT: fmv.d.x fa0, zero
+; RV64D-NEXT: fneg.d fa0, fa0
; RV64D-NEXT: ret
ret double -0.0
}
diff --git a/llvm/test/CodeGen/RISCV/half-arith-strict.ll b/llvm/test/CodeGen/RISCV/half-arith-strict.ll
--- a/llvm/test/CodeGen/RISCV/half-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith-strict.ll
@@ -116,16 +116,16 @@
define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fmsub_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmsub_h:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fneg half %c_
@@ -136,18 +136,18 @@
define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_h:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
%a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c
@@ -160,18 +160,18 @@
define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h_2:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_h_2:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret
%b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c
@@ -184,16 +184,16 @@
define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_h:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
%a_ = fadd half 0.0, %a
%nega = fneg half %a_
@@ -204,16 +204,16 @@
define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h_2:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_h_2:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret
%b_ = fadd half 0.0, %b
%negb = fneg half %b_
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -358,16 +358,16 @@
define i32 @fneg_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fneg_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa0
-; RV32IZFH-NEXT: fneg.h ft1, ft0
-; RV32IZFH-NEXT: feq.h a0, ft0, ft1
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa0
+; RV32IZFH-NEXT: fneg.h fa1, fa0
+; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fneg_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa0
-; RV64IZFH-NEXT: fneg.h ft1, ft0
-; RV64IZFH-NEXT: feq.h a0, ft0, ft1
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa0
+; RV64IZFH-NEXT: fneg.h fa1, fa0
+; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fneg_s:
@@ -443,14 +443,14 @@
define half @fsgnjn_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fsgnjn_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
+; RV32IZFH-NEXT: fadd.h fa1, fa0, fa1
+; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsgnjn_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
+; RV64IZFH-NEXT: fadd.h fa1, fa0, fa1
+; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
@@ -543,16 +543,16 @@
define half @fabs_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fabs_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fabs.h ft1, ft0
-; RV32IZFH-NEXT: fadd.h fa0, ft1, ft0
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV32IZFH-NEXT: fabs.h fa1, fa0
+; RV32IZFH-NEXT: fadd.h fa0, fa1, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fabs_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fabs.h ft1, ft0
-; RV64IZFH-NEXT: fadd.h fa0, ft1, ft0
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fabs.h fa1, fa0
+; RV64IZFH-NEXT: fadd.h fa0, fa1, fa0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fabs_s:
@@ -855,16 +855,16 @@
define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fmsub_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmsub_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
@@ -963,18 +963,18 @@
define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
@@ -1103,18 +1103,18 @@
define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s_2:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_s_2:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
@@ -1243,16 +1243,16 @@
define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_s:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
@@ -1349,16 +1349,16 @@
define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s_2:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_s_2:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
@@ -1548,16 +1548,16 @@
define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fmsub_s_contract:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmsub_s_contract:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
@@ -1656,20 +1656,20 @@
define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s_contract:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft2, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_s_contract:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft2, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
+; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
@@ -1805,18 +1805,18 @@
define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s_contract:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
+; RV32IZFH-NEXT: fmv.h.x fa3, zero
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_s_contract:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
+; RV64IZFH-NEXT: fmv.h.x fa3, zero
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
+; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
+; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
diff --git a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
@@ -91,10 +91,10 @@
;
; RV32IZFH-LABEL: fcopysign_fneg:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, a1
-; RV32IZFH-NEXT: fmv.h.x ft1, a0
-; RV32IZFH-NEXT: fsgnjn.h ft0, ft1, ft0
-; RV32IZFH-NEXT: fmv.x.h a0, ft0
+; RV32IZFH-NEXT: fmv.h.x fa0, a1
+; RV32IZFH-NEXT: fmv.h.x fa1, a0
+; RV32IZFH-NEXT: fsgnjn.h fa0, fa1, fa0
+; RV32IZFH-NEXT: fmv.x.h a0, fa0
; RV32IZFH-NEXT: ret
;
; RV64I-LABEL: fcopysign_fneg:
@@ -109,10 +109,10 @@
;
; RV64IZFH-LABEL: fcopysign_fneg:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, a1
-; RV64IZFH-NEXT: fmv.h.x ft1, a0
-; RV64IZFH-NEXT: fsgnjn.h ft0, ft1, ft0
-; RV64IZFH-NEXT: fmv.x.h a0, ft0
+; RV64IZFH-NEXT: fmv.h.x fa0, a1
+; RV64IZFH-NEXT: fmv.h.x fa1, a0
+; RV64IZFH-NEXT: fsgnjn.h fa0, fa1, fa0
+; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret
%1 = fneg half %b
%2 = call half @llvm.copysign.f16(half %a, half %1)
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -642,29 +642,29 @@
; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
-; RV32IZFH-NEXT: fcvt.h.w ft0, a0
-; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
-; RV64IZFH-NEXT: fcvt.h.w ft0, a0
-; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: fcvt.h.w fa0, a0
+; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.w ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
-; RV64IDZFH-NEXT: fcvt.h.w ft0, a0
-; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret
%3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
@@ -677,29 +677,29 @@
; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
-; RV32IZFH-NEXT: fcvt.h.wu ft0, a0
-; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
-; RV64IZFH-NEXT: fcvt.h.wu ft0, a0
-; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
+; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
-; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0
-; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret
%3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -63,65 +63,65 @@
define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_si_h_sat:
; RV32IZFH: # %bb.0: # %start
-; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB1_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
-; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB1_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_si_h_sat:
; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB1_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV64IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
-; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB1_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_si_h_sat:
; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB1_2
; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
-; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB1_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_si_h_sat:
; RV64IDZFH: # %bb.0: # %start
-; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB1_2
; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
-; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB1_2: # %start
; RV64IDZFH-NEXT: ret
;
@@ -278,45 +278,45 @@
; RV32IZFH-LABEL: fcvt_ui_h_sat:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IZFH-NEXT: fmv.w.x ft2, zero
-; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa2, zero
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_ui_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI3_0)
-; RV64IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV64IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IZFH-NEXT: fmv.w.x ft2, zero
-; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: fmv.w.x fa2, zero
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_ui_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IDZFH-NEXT: fmv.w.x ft2, zero
-; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: fmv.w.x fa2, zero
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_ui_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI3_0)
-; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IDZFH-NEXT: fmv.w.x ft2, zero
-; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: fmv.w.x fa2, zero
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_ui_h_sat:
@@ -908,9 +908,9 @@
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI10_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -919,8 +919,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB10_2: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI10_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB10_9
; RV32IZFH-NEXT: # %bb.3: # %start
@@ -973,9 +973,9 @@
; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI10_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
-; RV32IDZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IDZFH-NEXT: fle.s s0, fa1, fs0
; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call __fixsfdi@plt
; RV32IDZFH-NEXT: mv a2, a0
@@ -984,8 +984,8 @@
; RV32IDZFH-NEXT: li a2, 0
; RV32IDZFH-NEXT: .LBB10_2: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_1)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0)
-; RV32IDZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IDZFH-NEXT: flw fa0, %lo(.LCPI10_1)(a0)
+; RV32IDZFH-NEXT: flt.s a3, fa0, fs0
; RV32IDZFH-NEXT: li a0, -1
; RV32IDZFH-NEXT: beqz a3, .LBB10_9
; RV32IDZFH-NEXT: # %bb.3: # %start
@@ -1233,8 +1233,8 @@
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -1243,8 +1243,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB12_2: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI12_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB12_7
@@ -1285,8 +1285,8 @@
; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
-; RV32IDZFH-NEXT: fmv.w.x ft0, zero
-; RV32IDZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IDZFH-NEXT: fmv.w.x fa0, zero
+; RV32IDZFH-NEXT: fle.s s0, fa0, fs0
; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call __fixunssfdi@plt
; RV32IDZFH-NEXT: mv a3, a0
@@ -1295,8 +1295,8 @@
; RV32IDZFH-NEXT: li a3, 0
; RV32IDZFH-NEXT: .LBB12_2: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0)
-; RV32IDZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IDZFH-NEXT: flw fa0, %lo(.LCPI12_0)(a0)
+; RV32IDZFH-NEXT: flt.s a4, fa0, fs0
; RV32IDZFH-NEXT: li a2, -1
; RV32IDZFH-NEXT: li a0, -1
; RV32IDZFH-NEXT: beqz a4, .LBB12_7
@@ -2199,29 +2199,29 @@
; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
-; RV32IZFH-NEXT: fcvt.h.w ft0, a0
-; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
-; RV64IZFH-NEXT: fcvt.h.w ft0, a0
-; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: fcvt.h.w fa0, a0
+; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.w ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
-; RV64IDZFH-NEXT: fcvt.h.w ft0, a0
-; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
+; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_h_w_demanded_bits:
@@ -2272,29 +2272,29 @@
; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
-; RV32IZFH-NEXT: fcvt.h.wu ft0, a0
-; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1
-; RV64IZFH-NEXT: fcvt.h.wu ft0, a0
-; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
+; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1
-; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0
-; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1
-; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0
-; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
+; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_h_wu_demanded_bits:
@@ -2391,65 +2391,65 @@
define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IZFH: # %bb.0: # %start
-; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB32_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0)
-; RV32IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_1)
-; RV32IZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0)
-; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB32_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB32_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0)
-; RV64IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_1)
-; RV64IZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0)
-; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB32_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB32_2
; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
-; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
-; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0)
-; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB32_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start
-; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB32_2
; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
-; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
-; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0)
-; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB32_2: # %start
; RV64IDZFH-NEXT: ret
;
@@ -2607,45 +2607,45 @@
; RV32IZFH-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI34_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0)
-; RV32IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IZFH-NEXT: fmv.w.x ft2, zero
-; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa2, zero
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_s_sat_i16:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI34_0)
-; RV64IZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0)
-; RV64IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IZFH-NEXT: fmv.w.x ft2, zero
-; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: fmv.w.x fa2, zero
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI34_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0)
-; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IDZFH-NEXT: fmv.w.x ft2, zero
-; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: fmv.w.x fa2, zero
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_wu_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI34_0)
-; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0)
-; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IDZFH-NEXT: fmv.w.x ft2, zero
-; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: fmv.w.x fa2, zero
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i16:
@@ -2785,65 +2785,65 @@
define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IZFH: # %bb.0: # %start
-; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB36_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_0)
-; RV32IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_1)
-; RV32IZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0)
-; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB36_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB36_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_0)
-; RV64IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_1)
-; RV64IZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0)
-; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB36_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start
-; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB36_2
; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
-; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
-; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0)
-; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB36_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start
-; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
-; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB36_2
; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
-; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
-; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0)
-; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
-; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
-; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB36_2: # %start
; RV64IDZFH-NEXT: ret
;
@@ -3000,45 +3000,45 @@
; RV32IZFH-LABEL: fcvt_wu_s_sat_i8:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI38_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0)
-; RV32IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IZFH-NEXT: fmv.w.x ft2, zero
-; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
+; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa2, zero
+; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_s_sat_i8:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI38_0)
-; RV64IZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0)
-; RV64IZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IZFH-NEXT: fmv.w.x ft2, zero
-; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
+; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IZFH-NEXT: fmv.w.x fa2, zero
+; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI38_0)
-; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0)
-; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV32IDZFH-NEXT: fmv.w.x ft2, zero
-; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
+; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV32IDZFH-NEXT: fmv.w.x fa2, zero
+; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_wu_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI38_0)
-; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0)
-; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0
-; RV64IDZFH-NEXT: fmv.w.x ft2, zero
-; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2
-; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0
-; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
+; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
+; RV64IDZFH-NEXT: fmv.w.x fa2, zero
+; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
+; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
+; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll
--- a/llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -46,16 +46,16 @@
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: feq.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: feq.h a0, fa1, fa0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_oeq:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: feq.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: feq.h a0, fa1, fa0
; RV64I-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = zext i1 %1 to i32
@@ -75,16 +75,16 @@
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ogt:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: ret
%1 = fcmp ogt half %a, %b
%2 = zext i1 %1 to i32
@@ -104,16 +104,16 @@
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_oge:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: ret
%1 = fcmp oge half %a, %b
%2 = zext i1 %1 to i32
@@ -133,16 +133,16 @@
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_olt:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = zext i1 %1 to i32
@@ -162,16 +162,16 @@
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ole:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32
@@ -195,19 +195,19 @@
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: flt.h a0, ft1, ft0
-; RV32I-NEXT: flt.h a1, ft0, ft1
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: flt.h a0, fa1, fa0
+; RV32I-NEXT: flt.h a1, fa0, fa1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_one:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: flt.h a0, ft1, ft0
-; RV64I-NEXT: flt.h a1, ft0, ft1
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: flt.h a0, fa1, fa0
+; RV64I-NEXT: flt.h a1, fa0, fa1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
%1 = fcmp one half %a, %b
@@ -232,19 +232,19 @@
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: feq.h a0, ft1, ft1
-; RV32I-NEXT: feq.h a1, ft0, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: feq.h a0, fa1, fa1
+; RV32I-NEXT: feq.h a1, fa0, fa0
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ord:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: feq.h a0, ft1, ft1
-; RV64I-NEXT: feq.h a1, ft0, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: feq.h a0, fa1, fa1
+; RV64I-NEXT: feq.h a1, fa0, fa0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
%1 = fcmp ord half %a, %b
@@ -271,20 +271,20 @@
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: flt.h a0, ft1, ft0
-; RV32I-NEXT: flt.h a1, ft0, ft1
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: flt.h a0, fa1, fa0
+; RV32I-NEXT: flt.h a1, fa0, fa1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ueq:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: flt.h a0, ft1, ft0
-; RV64I-NEXT: flt.h a1, ft0, ft1
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: flt.h a0, fa1, fa0
+; RV64I-NEXT: flt.h a1, fa0, fa1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
@@ -308,17 +308,17 @@
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ugt:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ugt half %a, %b
@@ -341,17 +341,17 @@
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_uge:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp uge half %a, %b
@@ -374,17 +374,17 @@
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: fle.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ult:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: fle.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ult half %a, %b
@@ -407,17 +407,17 @@
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: flt.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ule:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: flt.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ule half %a, %b
@@ -440,17 +440,17 @@
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a1
-; RV32I-NEXT: fmv.h.x ft1, a0
-; RV32I-NEXT: feq.h a0, ft1, ft0
+; RV32I-NEXT: fmv.h.x fa0, a1
+; RV32I-NEXT: fmv.h.x fa1, a0
+; RV32I-NEXT: feq.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_une:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a1
-; RV64I-NEXT: fmv.h.x ft1, a0
-; RV64I-NEXT: feq.h a0, ft1, ft0
+; RV64I-NEXT: fmv.h.x fa0, a1
+; RV64I-NEXT: fmv.h.x fa1, a0
+; RV64I-NEXT: feq.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp une half %a, %b
@@ -477,20 +477,20 @@
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
-; RV32I-NEXT: fmv.h.x ft0, a0
-; RV32I-NEXT: fmv.h.x ft1, a1
-; RV32I-NEXT: feq.h a0, ft1, ft1
-; RV32I-NEXT: feq.h a1, ft0, ft0
+; RV32I-NEXT: fmv.h.x fa0, a0
+; RV32I-NEXT: fmv.h.x fa1, a1
+; RV32I-NEXT: feq.h a0, fa1, fa1
+; RV32I-NEXT: feq.h a1, fa0, fa0
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_uno:
; RV64I: # %bb.0:
-; RV64I-NEXT: fmv.h.x ft0, a0
-; RV64I-NEXT: fmv.h.x ft1, a1
-; RV64I-NEXT: feq.h a0, ft1, ft1
-; RV64I-NEXT: feq.h a1, ft0, ft0
+; RV64I-NEXT: fmv.h.x fa0, a0
+; RV64I-NEXT: fmv.h.x fa1, a1
+; RV64I-NEXT: feq.h a0, fa1, fa1
+; RV64I-NEXT: feq.h a1, fa0, fa0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -24,15 +24,15 @@
; RV32IZFH-LABEL: half_imm_op:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
-; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV32IZFH-NEXT: flh fa1, %lo(.LCPI1_0)(a0)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: half_imm_op:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
-; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV64IZFH-NEXT: flh fa1, %lo(.LCPI1_0)(a0)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
%1 = fadd half %a, 1.0
ret half %1
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -322,8 +322,8 @@
; RV32IZFH-NEXT: fcvt.h.s fs1, fa0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call cosf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fadd.h fa0, fs1, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
@@ -342,8 +342,8 @@
; RV64IZFH-NEXT: fcvt.h.s fs1, fa0
; RV64IZFH-NEXT: fmv.s fa0, fs0
; RV64IZFH-NEXT: call cosf@plt
-; RV64IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV64IZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IZFH-NEXT: fadd.h fa0, fs1, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
@@ -362,8 +362,8 @@
; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0
; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call cosf@plt
-; RV32IDZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IDZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IDZFH-NEXT: fadd.h fa0, fs1, fa0
; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
@@ -382,8 +382,8 @@
; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0
; RV64IDZFH-NEXT: fmv.s fa0, fs0
; RV64IDZFH-NEXT: call cosf@plt
-; RV64IDZFH-NEXT: fcvt.h.s ft0, fa0
-; RV64IDZFH-NEXT: fadd.h fa0, fs1, ft0
+; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
+; RV64IDZFH-NEXT: fadd.h fa0, fs1, fa0
; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
--- a/llvm/test/CodeGen/RISCV/half-mem.ll
+++ b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -7,16 +7,16 @@
define half @flh(half *%a) nounwind {
; RV32IZFH-LABEL: flh:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flh ft0, 0(a0)
-; RV32IZFH-NEXT: flh ft1, 6(a0)
-; RV32IZFH-NEXT: fadd.h fa0, ft0, ft1
+; RV32IZFH-NEXT: flh fa0, 0(a0)
+; RV32IZFH-NEXT: flh fa1, 6(a0)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: flh:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flh ft0, 0(a0)
-; RV64IZFH-NEXT: flh ft1, 6(a0)
-; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
+; RV64IZFH-NEXT: flh fa0, 0(a0)
+; RV64IZFH-NEXT: flh fa1, 6(a0)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
%1 = load half, half* %a
%2 = getelementptr half, half* %a, i32 3
@@ -32,16 +32,16 @@
; are used, even for the soft half ABI
; RV32IZFH-LABEL: fsh:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fsh ft0, 0(a0)
-; RV32IZFH-NEXT: fsh ft0, 16(a0)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV32IZFH-NEXT: fsh fa0, 0(a0)
+; RV32IZFH-NEXT: fsh fa0, 16(a0)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsh:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fsh ft0, 0(a0)
-; RV64IZFH-NEXT: fsh ft0, 16(a0)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fsh fa0, 0(a0)
+; RV64IZFH-NEXT: fsh fa0, 16(a0)
; RV64IZFH-NEXT: ret
%1 = fadd half %b, %c
store half %1, half* %a
@@ -60,10 +60,10 @@
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: lui a0, %hi(G)
-; RV32IZFH-NEXT: flh ft0, %lo(G)(a0)
+; RV32IZFH-NEXT: flh fa1, %lo(G)(a0)
; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV32IZFH-NEXT: addi a0, a0, %lo(G)
-; RV32IZFH-NEXT: flh ft0, 18(a0)
+; RV32IZFH-NEXT: flh fa1, 18(a0)
; RV32IZFH-NEXT: fsh fa0, 18(a0)
; RV32IZFH-NEXT: ret
;
@@ -71,10 +71,10 @@
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: lui a0, %hi(G)
-; RV64IZFH-NEXT: flh ft0, %lo(G)(a0)
+; RV64IZFH-NEXT: flh fa1, %lo(G)(a0)
; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV64IZFH-NEXT: addi a0, a0, %lo(G)
-; RV64IZFH-NEXT: flh ft0, 18(a0)
+; RV64IZFH-NEXT: flh fa1, 18(a0)
; RV64IZFH-NEXT: fsh fa0, 18(a0)
; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b
@@ -91,8 +91,8 @@
; RV32IZFH-LABEL: flh_fsh_constant:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, 912092
-; RV32IZFH-NEXT: flh ft0, -273(a0)
-; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV32IZFH-NEXT: flh fa1, -273(a0)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: fsh fa0, -273(a0)
; RV32IZFH-NEXT: ret
;
@@ -100,8 +100,8 @@
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, 228023
; RV64IZFH-NEXT: slli a0, a0, 2
-; RV64IZFH-NEXT: flh ft0, -273(a0)
-; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV64IZFH-NEXT: flh fa1, -273(a0)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fsh fa0, -273(a0)
; RV64IZFH-NEXT: ret
%1 = inttoptr i32 3735928559 to half*
@@ -122,8 +122,8 @@
; RV32IZFH-NEXT: fmv.h fs0, fa0
; RV32IZFH-NEXT: addi a0, sp, 4
; RV32IZFH-NEXT: call notdead@plt
-; RV32IZFH-NEXT: flh ft0, 4(sp)
-; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0
+; RV32IZFH-NEXT: flh fa0, 4(sp)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fs0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -137,8 +137,8 @@
; RV64IZFH-NEXT: fmv.h fs0, fa0
; RV64IZFH-NEXT: mv a0, sp
; RV64IZFH-NEXT: call notdead@plt
-; RV64IZFH-NEXT: flh ft0, 0(sp)
-; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0
+; RV64IZFH-NEXT: flh fa0, 0(sp)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fs0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -156,8 +156,8 @@
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fsh ft0, 8(sp)
+; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV32IZFH-NEXT: fsh fa0, 8(sp)
; RV32IZFH-NEXT: addi a0, sp, 8
; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -168,8 +168,8 @@
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fsh ft0, 4(sp)
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fsh fa0, 4(sp)
; RV64IZFH-NEXT: addi a0, sp, 4
; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
--- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
@@ -37,10 +37,10 @@
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV32IZFH-NEXT: fcvt.h.s ft1, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft1
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -49,8 +49,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB1_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI1_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB1_9
; RV32IZFH-NEXT: # %bb.3:
@@ -132,10 +132,10 @@
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -144,8 +144,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB3_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB3_7
@@ -216,10 +216,10 @@
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_0)(a0)
-; RV32IZFH-NEXT: fcvt.h.s ft1, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft1
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI5_0)(a0)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -228,8 +228,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB5_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI5_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB5_9
; RV32IZFH-NEXT: # %bb.3:
@@ -311,10 +311,10 @@
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -323,8 +323,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB7_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB7_7
@@ -395,10 +395,10 @@
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
-; RV32IZFH-NEXT: fcvt.h.s ft1, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft1
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI9_0)(a0)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -407,8 +407,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB9_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI9_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB9_9
; RV32IZFH-NEXT: # %bb.3:
@@ -490,10 +490,10 @@
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -502,8 +502,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB11_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI11_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI11_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB11_7
@@ -574,10 +574,10 @@
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI13_0)(a0)
-; RV32IZFH-NEXT: fcvt.h.s ft1, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft1
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI13_0)(a0)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -586,8 +586,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB13_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI13_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI13_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB13_9
; RV32IZFH-NEXT: # %bb.3:
@@ -669,10 +669,10 @@
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -681,8 +681,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB15_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI15_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI15_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB15_7
@@ -753,10 +753,10 @@
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI17_0)(a0)
-; RV32IZFH-NEXT: fcvt.h.s ft1, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft1
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: flw fa1, %lo(.LCPI17_0)(a0)
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0
@@ -765,8 +765,8 @@
; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB17_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_1)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI17_1)(a0)
-; RV32IZFH-NEXT: flt.s a3, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI17_1)(a0)
+; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB17_9
; RV32IZFH-NEXT: # %bb.3:
@@ -848,10 +848,10 @@
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt
-; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
-; RV32IZFH-NEXT: fcvt.s.h fs0, ft0
-; RV32IZFH-NEXT: fmv.w.x ft0, zero
-; RV32IZFH-NEXT: fle.s s0, ft0, fs0
+; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
+; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
+; RV32IZFH-NEXT: fmv.w.x fa0, zero
+; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0
@@ -860,8 +860,8 @@
; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB19_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
-; RV32IZFH-NEXT: flw ft0, %lo(.LCPI19_0)(a0)
-; RV32IZFH-NEXT: flt.s a4, ft0, fs0
+; RV32IZFH-NEXT: flw fa0, %lo(.LCPI19_0)(a0)
+; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB19_7
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
@@ -12,13 +12,13 @@
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp)
-; RV32F-NEXT: fld ft0, 8(sp)
+; RV32F-NEXT: fld fa0, 8(sp)
; RV32F-NEXT: lui a0, %hi(gd)
-; RV32F-NEXT: fld ft1, %lo(gd)(a0)
+; RV32F-NEXT: fld fa1, %lo(gd)(a0)
; RV32F-NEXT: #APP
-; RV32F-NEXT: fadd.d ft0, ft0, ft1
+; RV32F-NEXT: fadd.d fa0, fa0, fa1
; RV32F-NEXT: #NO_APP
-; RV32F-NEXT: fsd ft0, 8(sp)
+; RV32F-NEXT: fsd fa0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
@@ -27,12 +27,12 @@
; RV64F-LABEL: constraint_f_double:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gd)
-; RV64F-NEXT: fld ft0, %lo(gd)(a1)
-; RV64F-NEXT: fmv.d.x ft1, a0
+; RV64F-NEXT: fld fa0, %lo(gd)(a1)
+; RV64F-NEXT: fmv.d.x fa1, a0
; RV64F-NEXT: #APP
-; RV64F-NEXT: fadd.d ft0, ft1, ft0
+; RV64F-NEXT: fadd.d fa0, fa1, fa0
; RV64F-NEXT: #NO_APP
-; RV64F-NEXT: fmv.x.d a0, ft0
+; RV64F-NEXT: fmv.x.d a0, fa0
; RV64F-NEXT: ret
%1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
@@ -79,8 +79,8 @@
; RV32F-NEXT: .cfi_def_cfa_offset 32
; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp)
-; RV32F-NEXT: fld ft0, 8(sp)
-; RV32F-NEXT: fsd ft0, 24(sp)
+; RV32F-NEXT: fld fa0, 8(sp)
+; RV32F-NEXT: fsd fa0, 24(sp)
; RV32F-NEXT: lw a0, 24(sp)
; RV32F-NEXT: lw a1, 28(sp)
; RV32F-NEXT: #APP
@@ -88,8 +88,8 @@
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: sw a1, 20(sp)
; RV32F-NEXT: sw a0, 16(sp)
-; RV32F-NEXT: fld ft0, 16(sp)
-; RV32F-NEXT: fsd ft0, 8(sp)
+; RV32F-NEXT: fld fa0, 16(sp)
+; RV32F-NEXT: fsd fa0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 32
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
@@ -15,23 +15,23 @@
; RV32F-LABEL: constraint_f_float:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
-; RV32F-NEXT: flw ft0, %lo(gf)(a1)
-; RV32F-NEXT: fmv.w.x ft1, a0
+; RV32F-NEXT: flw fa0, %lo(gf)(a1)
+; RV32F-NEXT: fmv.w.x fa1, a0
; RV32F-NEXT: #APP
-; RV32F-NEXT: fadd.s ft0, ft1, ft0
+; RV32F-NEXT: fadd.s fa0, fa1, fa0
; RV32F-NEXT: #NO_APP
-; RV32F-NEXT: fmv.x.w a0, ft0
+; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_f_float:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
-; RV64F-NEXT: flw ft0, %lo(gf)(a1)
-; RV64F-NEXT: fmv.w.x ft1, a0
+; RV64F-NEXT: flw fa0, %lo(gf)(a1)
+; RV64F-NEXT: fmv.w.x fa1, a0
; RV64F-NEXT: #APP
-; RV64F-NEXT: fadd.s ft0, ft1, ft0
+; RV64F-NEXT: fadd.s fa0, fa1, fa0
; RV64F-NEXT: #NO_APP
-; RV64F-NEXT: fmv.x.w a0, ft0
+; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret
%1 = load float, float* @gf
%2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
@@ -14,36 +14,36 @@
; RV32ZFH-LABEL: constraint_f_half:
; RV32ZFH: # %bb.0:
; RV32ZFH-NEXT: lui a0, %hi(gh)
-; RV32ZFH-NEXT: flh ft0, %lo(gh)(a0)
+; RV32ZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV32ZFH-NEXT: #APP
-; RV32ZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV32ZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32ZFH-NEXT: #NO_APP
; RV32ZFH-NEXT: ret
;
; RV64ZFH-LABEL: constraint_f_half:
; RV64ZFH: # %bb.0:
; RV64ZFH-NEXT: lui a0, %hi(gh)
-; RV64ZFH-NEXT: flh ft0, %lo(gh)(a0)
+; RV64ZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV64ZFH-NEXT: #APP
-; RV64ZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV64ZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64ZFH-NEXT: #NO_APP
; RV64ZFH-NEXT: ret
;
; RV32DZFH-LABEL: constraint_f_half:
; RV32DZFH: # %bb.0:
; RV32DZFH-NEXT: lui a0, %hi(gh)
-; RV32DZFH-NEXT: flh ft0, %lo(gh)(a0)
+; RV32DZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV32DZFH-NEXT: #APP
-; RV32DZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV32DZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32DZFH-NEXT: #NO_APP
; RV32DZFH-NEXT: ret
;
; RV64DZFH-LABEL: constraint_f_half:
; RV64DZFH: # %bb.0:
; RV64DZFH-NEXT: lui a0, %hi(gh)
-; RV64DZFH-NEXT: flh ft0, %lo(gh)(a0)
+; RV64DZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV64DZFH-NEXT: #APP
-; RV64DZFH-NEXT: fadd.h fa0, fa0, ft0
+; RV64DZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64DZFH-NEXT: #NO_APP
; RV64DZFH-NEXT: ret
%1 = load half, half* @gh
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
--- a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
@@ -211,18 +211,18 @@
; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32IF-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
-; CHECK-RV32IF-NEXT: fsw ft1, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32IF-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32IF-NEXT: fsw fa1, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: lui a0, %hi(e)
-; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
+; CHECK-RV32IF-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
-; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
-; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
+; CHECK-RV32IF-NEXT: flw fa1, %lo(f)(a0)
+; CHECK-RV32IF-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IF-NEXT: lui a0, %hi(d)
-; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IF-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; CHECK-RV32IF-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
-; CHECK-RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32IF-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32IF-NEXT: flw fa1, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret
;
@@ -230,18 +230,18 @@
; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
-; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
+; CHECK-RV32IFD-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
-; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
-; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
+; CHECK-RV32IFD-NEXT: flw fa1, %lo(f)(a0)
+; CHECK-RV32IFD-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
-; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IFD-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e
@@ -309,21 +309,21 @@
; CHECK-RV32IF-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; CHECK-RV32IF-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
-; CHECK-RV32IF-NEXT: fsw ft1, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32IF-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32IF-NEXT: fsw fa1, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: addi s0, sp, 32
; CHECK-RV32IF-NEXT: lui a0, %hi(e)
-; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
+; CHECK-RV32IF-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
-; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
-; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
+; CHECK-RV32IF-NEXT: flw fa1, %lo(f)(a0)
+; CHECK-RV32IF-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IF-NEXT: lui a0, %hi(d)
-; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IF-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; CHECK-RV32IF-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
-; CHECK-RV32IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32IF-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32IF-NEXT: flw fa1, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 32
; CHECK-RV32IF-NEXT: mret
;
@@ -333,21 +333,21 @@
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
-; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
+; CHECK-RV32IFD-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
-; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
-; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
+; CHECK-RV32IFD-NEXT: flw fa1, %lo(f)(a0)
+; CHECK-RV32IFD-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
-; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IFD-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e
@@ -526,18 +526,18 @@
; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
-; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
+; CHECK-RV32IFD-NEXT: fld fa0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
-; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
-; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
+; CHECK-RV32IFD-NEXT: fld fa1, %lo(i)(a0)
+; CHECK-RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
-; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
+; CHECK-RV32IFD-NEXT: fsd fa0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h
@@ -723,21 +723,21 @@
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
-; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
+; CHECK-RV32IFD-NEXT: fsd fa1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
-; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
+; CHECK-RV32IFD-NEXT: fld fa0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
-; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
-; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
+; CHECK-RV32IFD-NEXT: fld fa1, %lo(i)(a0)
+; CHECK-RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
-; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
+; CHECK-RV32IFD-NEXT: fsd fa0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; CHECK-RV32IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h
diff --git a/llvm/test/CodeGen/RISCV/module-target-abi.ll b/llvm/test/CodeGen/RISCV/module-target-abi.ll
--- a/llvm/test/CodeGen/RISCV/module-target-abi.ll
+++ b/llvm/test/CodeGen/RISCV/module-target-abi.ll
@@ -12,9 +12,9 @@
define float @foo(i32 %a) nounwind #0 {
; DEFAULT: # %bb.0:
-; DEFAULT: fmv.x.w a0, ft0
+; DEFAULT: fmv.x.w a0, fa0
; RV32IF-ILP32: # %bb.0:
-; RV32IF-ILP32: fmv.x.w a0, ft0
+; RV32IF-ILP32: fmv.x.w a0, fa0
%conv = sitofp i32 %a to float
ret float %conv
}
diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
@@ -10,8 +10,8 @@
define i32 @aext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -21,8 +21,8 @@
define signext i32 @sext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -31,8 +31,8 @@
define zeroext i32 @zext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
@@ -43,8 +43,8 @@
define i32 @aext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -54,8 +54,8 @@
define signext i32 @sext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -64,8 +64,8 @@
define zeroext i32 @zext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
@@ -74,8 +74,8 @@
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -85,8 +85,8 @@
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -95,8 +95,8 @@
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -105,8 +105,8 @@
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -116,8 +116,8 @@
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
@@ -126,8 +126,8 @@
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
--- a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
@@ -10,8 +10,8 @@
define i32 @aext_fptosi(float %a) nounwind {
; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
@@ -20,8 +20,8 @@
define signext i32 @sext_fptosi(float %a) nounwind {
; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
@@ -30,8 +30,8 @@
define zeroext i32 @zext_fptosi(float %a) nounwind {
; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
@@ -42,8 +42,8 @@
define i32 @aext_fptoui(float %a) nounwind {
; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -52,8 +52,8 @@
define signext i32 @sext_fptoui(float %a) nounwind {
; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -62,8 +62,8 @@
define zeroext i32 @zext_fptoui(float %a) nounwind {
; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
@@ -72,10 +72,10 @@
define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_aext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fmv.w.x fa0, a1
+; RV64IF-NEXT: fmv.w.x fa1, a0
+; RV64IF-NEXT: fadd.s fa0, fa1, fa0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = bitcast float %1 to i32
@@ -85,10 +85,10 @@
define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_sext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fmv.w.x fa0, a1
+; RV64IF-NEXT: fmv.w.x fa1, a0
+; RV64IF-NEXT: fadd.s fa0, fa1, fa0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = bitcast float %1 to i32
@@ -98,10 +98,10 @@
define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_zext_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a1
-; RV64IF-NEXT: fmv.w.x ft1, a0
-; RV64IF-NEXT: fadd.s ft0, ft1, ft0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fmv.w.x fa0, a1
+; RV64IF-NEXT: fmv.w.x fa1, a0
+; RV64IF-NEXT: fadd.s fa0, fa1, fa0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
@@ -113,10 +113,10 @@
define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fmv.w.x ft1, a1
-; RV64IF-NEXT: fadd.s ft0, ft0, ft1
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fmv.w.x fa0, a0
+; RV64IF-NEXT: fmv.w.x fa1, a1
+; RV64IF-NEXT: fadd.s fa0, fa0, fa1
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = trunc i64 %a to i32
%2 = trunc i64 %b to i32
@@ -129,8 +129,8 @@
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -139,8 +139,8 @@
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -149,8 +149,8 @@
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.wu fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
@@ -159,8 +159,8 @@
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
@@ -169,8 +169,8 @@
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
@@ -179,8 +179,8 @@
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w ft0, a0
-; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: fcvt.s.w fa0, a0
+; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
--- a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
@@ -66,8 +66,8 @@
define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_aext_i16:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fmv.x.h a0, ft0
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b
%2 = bitcast half %1 to i16
@@ -77,8 +77,8 @@
define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_sext_i16:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fmv.x.h a0, ft0
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b
%2 = bitcast half %1 to i16
@@ -88,8 +88,8 @@
define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_zext_i16:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fmv.x.h a0, ft0
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: slli a0, a0, 48
; RV64IZFH-NEXT: srli a0, a0, 48
; RV64IZFH-NEXT: ret
@@ -101,9 +101,9 @@
define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, a0
-; RV64IZFH-NEXT: fmv.h.x ft1, a1
-; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
+; RV64IZFH-NEXT: fmv.h.x fa0, a0
+; RV64IZFH-NEXT: fmv.h.x fa1, a1
+; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
%1 = trunc i64 %a to i16
%2 = trunc i64 %b to i16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
@@ -11,14 +11,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -34,14 +34,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -57,14 +57,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -80,14 +80,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0)
-; CHECK-NEXT: vfadd.vf v12, v10, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
+; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -103,14 +103,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0)
-; CHECK-NEXT: vfadd.vf v16, v12, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
+; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -126,14 +126,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0)
-; CHECK-NEXT: vfadd.vf v24, v16, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
+; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
@@ -149,14 +149,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -172,14 +172,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -195,14 +195,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0)
-; CHECK-NEXT: vfadd.vf v12, v10, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
+; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -218,14 +218,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0)
-; CHECK-NEXT: vfadd.vf v16, v12, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
+; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -241,14 +241,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0)
-; CHECK-NEXT: vfadd.vf v24, v16, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
+; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
@@ -264,14 +264,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -287,14 +287,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0)
-; CHECK-NEXT: vfadd.vf v12, v10, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
+; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -310,14 +310,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0)
-; CHECK-NEXT: vfadd.vf v16, v12, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
+; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -333,14 +333,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0)
-; CHECK-NEXT: vfadd.vf v24, v16, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
+; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
@@ -11,14 +11,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -34,14 +34,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -57,14 +57,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -80,14 +80,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0)
-; CHECK-NEXT: vfsub.vf v12, v10, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
+; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -103,14 +103,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0)
-; CHECK-NEXT: vfsub.vf v16, v12, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
+; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -126,14 +126,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0)
-; CHECK-NEXT: vfsub.vf v24, v16, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
+; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
@@ -149,14 +149,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -172,14 +172,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -195,14 +195,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0)
-; CHECK-NEXT: vfsub.vf v12, v10, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
+; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -218,14 +218,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0)
-; CHECK-NEXT: vfsub.vf v16, v12, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
+; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -241,14 +241,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0)
-; CHECK-NEXT: vfsub.vf v24, v16, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
+; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
@@ -264,14 +264,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
@@ -287,14 +287,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0)
-; CHECK-NEXT: vfsub.vf v12, v10, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
+; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
@@ -310,14 +310,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0)
-; CHECK-NEXT: vfsub.vf v16, v12, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
+; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
@@ -333,14 +333,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0)
-; CHECK-NEXT: vfsub.vf v24, v16, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
+; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v24, ft1
+; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
@@ -136,14 +136,14 @@
define void @fadd_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fadd_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: fld ft0, 8(a0)
-; CHECK-NEXT: fld ft1, 0(a0)
-; CHECK-NEXT: fld ft2, 0(a1)
-; CHECK-NEXT: fld ft3, 8(a1)
-; CHECK-NEXT: fadd.d ft1, ft1, ft2
-; CHECK-NEXT: fadd.d ft0, ft0, ft3
-; CHECK-NEXT: fsd ft0, 8(a0)
-; CHECK-NEXT: fsd ft1, 0(a0)
+; CHECK-NEXT: fld fa0, 8(a0)
+; CHECK-NEXT: fld fa1, 0(a0)
+; CHECK-NEXT: fld fa2, 0(a1)
+; CHECK-NEXT: fld fa3, 8(a1)
+; CHECK-NEXT: fadd.d fa1, fa1, fa2
+; CHECK-NEXT: fadd.d fa0, fa0, fa3
+; CHECK-NEXT: fsd fa0, 8(a0)
+; CHECK-NEXT: fsd fa1, 0(a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -173,10 +173,10 @@
define void @fadd_v1f64(<1 x double>* %x, <1 x double>* %y) {
; CHECK-LABEL: fadd_v1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: fld ft0, 0(a0)
-; CHECK-NEXT: fld ft1, 0(a1)
-; CHECK-NEXT: fadd.d ft0, ft0, ft1
-; CHECK-NEXT: fsd ft0, 0(a0)
+; CHECK-NEXT: fld fa0, 0(a0)
+; CHECK-NEXT: fld fa1, 0(a1)
+; CHECK-NEXT: fadd.d fa0, fa0, fa1
+; CHECK-NEXT: fsd fa0, 0(a0)
; CHECK-NEXT: ret
%a = load <1 x double>, <1 x double>* %x
%b = load <1 x double>, <1 x double>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -149,9 +149,9 @@
; CHECK-LABEL: buildvec_dominant2_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1)
+; CHECK-NEXT: flw fa1, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.s.f v8, fa1
; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1
@@ -172,24 +172,24 @@
; RV32-NEXT: li a1, 6
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: lui a2, %hi(.LCPI7_0)
-; RV32-NEXT: flw ft0, %lo(.LCPI7_0)(a2)
+; RV32-NEXT: flw fa1, %lo(.LCPI7_0)(a2)
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vfmv.v.f v8, fa0
-; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV32-NEXT: vfmerge.vfm v8, v8, fa1, v0
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_merge0_v4f32:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI7_0)
-; RV64-NEXT: flw ft0, %lo(.LCPI7_0)(a1)
+; RV64-NEXT: flw fa1, %lo(.LCPI7_0)(a1)
; RV64-NEXT: li a1, 6
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vfmv.v.f v8, fa0
-; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV64-NEXT: vfmerge.vfm v8, v8, fa1, v0
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
@@ -33,22 +33,22 @@
; RV32: # %bb.0:
; RV32-NEXT: li a0, 9
; RV32-NEXT: lui a1, %hi(.LCPI2_0)
-; RV32-NEXT: fld ft0, %lo(.LCPI2_0)(a1)
+; RV32-NEXT: fld fa0, %lo(.LCPI2_0)(a1)
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_fv_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI2_0)
-; RV64-NEXT: fld ft0, %lo(.LCPI2_0)(a0)
+; RV64-NEXT: fld fa0, %lo(.LCPI2_0)(a0)
; RV64-NEXT: li a0, 9
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV64-NEXT: ret
%s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
ret <4 x double> %s
@@ -59,22 +59,22 @@
; RV32: # %bb.0:
; RV32-NEXT: li a0, 6
; RV32-NEXT: lui a1, %hi(.LCPI3_0)
-; RV32-NEXT: fld ft0, %lo(.LCPI3_0)(a1)
+; RV32-NEXT: fld fa0, %lo(.LCPI3_0)(a1)
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_vf_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI3_0)
-; RV64-NEXT: fld ft0, %lo(.LCPI3_0)(a0)
+; RV64-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
; RV64-NEXT: li a0, 6
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
ret <4 x double> %s
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -1970,9 +1970,9 @@
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI91_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI91_0)(a1)
+; CHECK-NEXT: flh fa0, %lo(.LCPI91_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -1992,9 +1992,9 @@
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI92_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI92_0)(a1)
+; CHECK-NEXT: flw fa0, %lo(.LCPI92_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -2014,9 +2014,9 @@
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI93_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI93_0)(a1)
+; CHECK-NEXT: fld fa0, %lo(.LCPI93_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -2038,14 +2038,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI94_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI94_0)(a1)
+; CHECK-NEXT: flh fa0, %lo(.LCPI94_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI94_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI94_1)(a1)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI94_1)(a1)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0)
@@ -2065,14 +2065,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI95_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI95_0)(a1)
+; CHECK-NEXT: flw fa0, %lo(.LCPI95_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI95_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI95_1)(a1)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI95_1)(a1)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0)
@@ -2092,14 +2092,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI96_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI96_0)(a1)
+; CHECK-NEXT: fld fa0, %lo(.LCPI96_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI96_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI96_1)(a1)
-; CHECK-NEXT: vfadd.vf v10, v9, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI96_1)(a1)
+; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0)
@@ -2119,14 +2119,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI97_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI97_0)(a1)
+; CHECK-NEXT: flh fa0, %lo(.LCPI97_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI97_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI97_1)(a1)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flh fa1, %lo(.LCPI97_1)(a1)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0)
@@ -2146,14 +2146,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI98_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI98_0)(a1)
+; CHECK-NEXT: flw fa0, %lo(.LCPI98_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI98_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI98_1)(a1)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: flw fa1, %lo(.LCPI98_1)(a1)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0)
@@ -2173,14 +2173,14 @@
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI99_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI99_0)(a1)
+; CHECK-NEXT: fld fa0, %lo(.LCPI99_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI99_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI99_1)(a1)
-; CHECK-NEXT: vfsub.vf v10, v9, ft0
+; CHECK-NEXT: fld fa1, %lo(.LCPI99_1)(a1)
+; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0)
@@ -2198,12 +2198,12 @@
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI100_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI100_0)(a1)
+; CHECK-NEXT: flh fa0, %lo(.LCPI100_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI100_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI100_1)(a1)
+; CHECK-NEXT: flh fa1, %lo(.LCPI100_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -2223,12 +2223,12 @@
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI101_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI101_0)(a1)
+; CHECK-NEXT: flw fa0, %lo(.LCPI101_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI101_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI101_1)(a1)
+; CHECK-NEXT: flw fa1, %lo(.LCPI101_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -2248,12 +2248,12 @@
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI102_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI102_0)(a1)
+; CHECK-NEXT: fld fa0, %lo(.LCPI102_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI102_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI102_1)(a1)
+; CHECK-NEXT: fld fa1, %lo(.LCPI102_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
@@ -7,8 +7,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -25,8 +25,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -43,8 +43,8 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
@@ -53,8 +53,8 @@
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
@@ -71,8 +71,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -89,8 +89,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -107,8 +107,8 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
@@ -117,8 +117,8 @@
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
@@ -135,8 +135,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -153,8 +153,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -171,8 +171,8 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
@@ -181,8 +181,8 @@
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
@@ -199,8 +199,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -217,8 +217,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -235,8 +235,8 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
@@ -245,8 +245,8 @@
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
@@ -263,8 +263,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -281,8 +281,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -299,8 +299,8 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
@@ -309,8 +309,8 @@
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
@@ -328,8 +328,8 @@
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -347,8 +347,8 @@
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -367,9 +367,9 @@
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v16, (a1)
; RV32-NEXT: vle64.v v24, (a3)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v8, v16, ft0
-; RV32-NEXT: vmfeq.vf v0, v24, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v8, v16, fa0
+; RV32-NEXT: vmfeq.vf v0, v24, fa0
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vle64.v v16, (a1), v0.t
; RV32-NEXT: vmv1r.v v0, v8
@@ -385,9 +385,9 @@
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: vle64.v v24, (a3)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v8, v16, ft0
-; RV64-NEXT: vmfeq.vf v0, v24, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v8, v16, fa0
+; RV64-NEXT: vmfeq.vf v0, v24, fa0
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vle64.v v16, (a1), v0.t
; RV64-NEXT: vmv1r.v v0, v8
@@ -410,8 +410,8 @@
; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -431,9 +431,9 @@
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v16, (a1)
; CHECK-NEXT: vle32.v v24, (a3)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v8, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v24, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v8, v16, fa0
+; CHECK-NEXT: vmfeq.vf v0, v24, fa0
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle32.v v16, (a1), v0.t
; CHECK-NEXT: vmv1r.v v0, v8
@@ -458,9 +458,9 @@
; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vle16.v v24, (a3)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v8, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v24, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v8, v16, fa0
+; CHECK-NEXT: vmfeq.vf v0, v24, fa0
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle16.v v16, (a1), v0.t
; CHECK-NEXT: vmv1r.v v0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
@@ -8,8 +8,8 @@
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x half>, <1 x half>* %m_ptr
@@ -26,8 +26,8 @@
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x float>, <1 x float>* %m_ptr
@@ -44,8 +44,8 @@
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v9, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret
;
@@ -54,8 +54,8 @@
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v9, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret
%m = load <1 x double>, <1 x double>* %m_ptr
@@ -72,8 +72,8 @@
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x half>, <2 x half>* %m_ptr
@@ -90,8 +90,8 @@
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x float>, <2 x float>* %m_ptr
@@ -108,8 +108,8 @@
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v9, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret
;
@@ -118,8 +118,8 @@
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v9, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret
%m = load <2 x double>, <2 x double>* %m_ptr
@@ -136,8 +136,8 @@
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x half>, <4 x half>* %m_ptr
@@ -154,8 +154,8 @@
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x float>, <4 x float>* %m_ptr
@@ -172,8 +172,8 @@
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v10, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v10, (a1), v0.t
; RV32-NEXT: ret
;
@@ -182,8 +182,8 @@
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v10, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v10, (a1), v0.t
; RV64-NEXT: ret
%m = load <4 x double>, <4 x double>* %m_ptr
@@ -200,8 +200,8 @@
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x half>, <8 x half>* %m_ptr
@@ -218,8 +218,8 @@
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x float>, <8 x float>* %m_ptr
@@ -236,8 +236,8 @@
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v12, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v12, (a1), v0.t
; RV32-NEXT: ret
;
@@ -246,8 +246,8 @@
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v12, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v12, (a1), v0.t
; RV64-NEXT: ret
%m = load <8 x double>, <8 x double>* %m_ptr
@@ -264,8 +264,8 @@
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v10, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x half>, <16 x half>* %m_ptr
@@ -282,8 +282,8 @@
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v12, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x float>, <16 x float>* %m_ptr
@@ -300,8 +300,8 @@
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v16, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v16, (a1), v0.t
; RV32-NEXT: ret
;
@@ -310,8 +310,8 @@
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v16, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v16, (a1), v0.t
; RV64-NEXT: ret
%m = load <16 x double>, <16 x double>* %m_ptr
@@ -329,8 +329,8 @@
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v12, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <32 x half>, <32 x half>* %m_ptr
@@ -348,8 +348,8 @@
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v16, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v16, (a1), v0.t
; CHECK-NEXT: ret
%m = load <32 x float>, <32 x float>* %m_ptr
@@ -376,8 +376,8 @@
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: fcvt.d.w fa0, zero
+; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v8, (a0)
@@ -388,7 +388,7 @@
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; RV32-NEXT: vmfeq.vf v8, v16, ft0
+; RV32-NEXT: vmfeq.vf v8, v16, fa0
; RV32-NEXT: vse64.v v24, (a1), v0.t
; RV32-NEXT: addi a0, a1, 128
; RV32-NEXT: vmv1r.v v0, v8
@@ -416,8 +416,8 @@
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: fmv.d.x fa0, zero
+; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v8, (a0)
@@ -428,7 +428,7 @@
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; RV64-NEXT: vmfeq.vf v8, v16, ft0
+; RV64-NEXT: vmfeq.vf v8, v16, fa0
; RV64-NEXT: vse64.v v24, (a1), v0.t
; RV64-NEXT: addi a0, a1, 128
; RV64-NEXT: vmv1r.v v0, v8
@@ -455,8 +455,8 @@
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v16, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v16, (a1), v0.t
; CHECK-NEXT: ret
%m = load <64 x half>, <64 x half>* %m_ptr
@@ -484,8 +484,8 @@
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v8, (a0)
@@ -496,7 +496,7 @@
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vse32.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
; CHECK-NEXT: vmv1r.v v0, v8
@@ -533,8 +533,8 @@
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v8, (a0)
@@ -545,7 +545,7 @@
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vse16.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
; CHECK-NEXT: vmv1r.v v0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -138,9 +138,9 @@
; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t
@@ -170,9 +170,9 @@
; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -9,8 +9,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
@@ -38,12 +38,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
@@ -71,12 +71,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
@@ -104,12 +104,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
@@ -137,12 +137,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
-; CHECK-NEXT: vfmv.s.f v10, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
+; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v10
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
@@ -171,14 +171,14 @@
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v12, ft0
+; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v12
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
@@ -210,14 +210,14 @@
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
@@ -252,14 +252,14 @@
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
@@ -278,9 +278,9 @@
; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v16, v16, v24
-; CHECK-NEXT: vfmv.f.s ft0, v16
+; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8
@@ -297,8 +297,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
@@ -326,8 +326,8 @@
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v9
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v9
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x
%e = fpext <1 x half> %v to <1 x float>
@@ -360,12 +360,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
@@ -391,15 +391,15 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
%e = fpext <2 x half> %v to <2 x float>
@@ -432,12 +432,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
@@ -463,15 +463,15 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%e = fpext <4 x half> %v to <4 x float>
@@ -504,12 +504,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
-; CHECK-NEXT: vfmv.s.f v10, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
+; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v10
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <8 x float>, <8 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
@@ -535,15 +535,15 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x
%e = fpext <8 x half> %v to <8 x float>
@@ -576,12 +576,12 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
-; CHECK-NEXT: vfmv.s.f v12, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
+; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v12
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
@@ -607,15 +607,15 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v10, ft0
+; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x
%e = fpext <16 x half> %v to <16 x float>
@@ -649,14 +649,14 @@
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <32 x float>, <32 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
@@ -686,15 +686,15 @@
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v12, ft0
+; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x
%e = fpext <32 x half> %v to <32 x float>
@@ -732,14 +732,14 @@
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
@@ -758,9 +758,9 @@
; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v16, v16, v24
-; CHECK-NEXT: vfmv.f.s ft0, v16
+; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8
@@ -784,14 +784,14 @@
; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfadd.vv v8, v16, v24
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x
%e = fpext <64 x half> %v to <64 x float>
@@ -813,9 +813,9 @@
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v16, v16, v24
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v16
+; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
@@ -834,8 +834,8 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.d fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.d fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <1 x double>, <1 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
@@ -863,8 +863,8 @@
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v9
-; CHECK-NEXT: fadd.d fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v9
+; CHECK-NEXT: fadd.d fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x
%e = fpext <1 x float> %v to <1 x double>
@@ -897,24 +897,24 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v9
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v9
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <2 x double>, <2 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
@@ -940,30 +940,30 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_v2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
%e = fpext <2 x float> %v to <2 x double>
@@ -996,24 +996,24 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v10, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v10
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v10, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v10
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
@@ -1039,30 +1039,30 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%e = fpext <4 x float> %v to <4 x double>
@@ -1095,24 +1095,24 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v12, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v12
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v12, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v12
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <8 x double>, <8 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
@@ -1138,30 +1138,30 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v10, ft0
+; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v10, ft0
+; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v10
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <8 x float>, <8 x float>* %x
%e = fpext <8 x float> %v to <8 x double>
@@ -1194,24 +1194,24 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v16, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v16, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v16
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v16f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v16, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v16, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v16
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <16 x double>, <16 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
@@ -1237,30 +1237,30 @@
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v12, ft0
+; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v12
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_v16f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v12, ft0
+; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v12
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <16 x float>, <16 x float>* %x
%e = fpext <16 x float> %v to <16 x double>
@@ -1295,13 +1295,13 @@
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v16, (a0)
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v24, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v24, fa1
; RV32-NEXT: vfadd.vv v8, v8, v16
; RV32-NEXT: vfredusum.vs v8, v8, v24
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v32f64:
@@ -1310,13 +1310,13 @@
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v16, (a0)
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v24, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v24, fa1
; RV64-NEXT: vfadd.vv v8, v8, v16
; RV64-NEXT: vfredusum.vs v8, v8, v24
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <32 x double>, <32 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
@@ -1332,8 +1332,8 @@
; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v24
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vfredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -1355,12 +1355,12 @@
; RV32-NEXT: vfwcvt.f.f.v v16, v8
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfadd.vv v8, v16, v24
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
-; RV32-NEXT: vfmv.s.f v16, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
+; RV32-NEXT: vfmv.s.f v16, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v16
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_v32f64:
@@ -1375,12 +1375,12 @@
; RV64-NEXT: vfwcvt.f.f.v v16, v8
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfadd.vv v8, v16, v24
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
-; RV64-NEXT: vfmv.s.f v16, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
+; RV64-NEXT: vfmv.s.f v16, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v16
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%v = load <32 x float>, <32 x float>* %x
%e = fpext <32 x float> %v to <32 x double>
@@ -1401,9 +1401,9 @@
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v16, v16, v24
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v16
+; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v16, ft0
+; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
@@ -2032,8 +2032,8 @@
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
@@ -8,13 +8,13 @@
; CHECK-LABEL: round_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -29,13 +29,13 @@
; CHECK-LABEL: round_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -50,13 +50,13 @@
; CHECK-LABEL: round_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -71,13 +71,13 @@
; CHECK-LABEL: round_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
-; CHECK-NEXT: vfadd.vf v10, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
+; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -92,13 +92,13 @@
; CHECK-LABEL: round_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
-; CHECK-NEXT: vfadd.vf v12, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
+; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -113,13 +113,13 @@
; CHECK-LABEL: round_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
-; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0)
+; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
-; CHECK-NEXT: vfadd.vf v16, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
+; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
@@ -134,13 +134,13 @@
; CHECK-LABEL: round_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0)
+; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -155,13 +155,13 @@
; CHECK-LABEL: round_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0)
+; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -176,13 +176,13 @@
; CHECK-LABEL: round_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0)
+; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
-; CHECK-NEXT: vfadd.vf v10, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
+; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -197,13 +197,13 @@
; CHECK-LABEL: round_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0)
+; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
-; CHECK-NEXT: vfadd.vf v12, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
+; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -218,13 +218,13 @@
; CHECK-LABEL: round_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
-; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0)
+; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
-; CHECK-NEXT: vfadd.vf v16, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
+; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
@@ -239,13 +239,13 @@
; CHECK-LABEL: round_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0)
+; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
-; CHECK-NEXT: vfadd.vf v9, v9, ft1
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
+; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -260,13 +260,13 @@
; CHECK-LABEL: round_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0)
+; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
-; CHECK-NEXT: vfadd.vf v10, v10, ft1
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
+; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -281,13 +281,13 @@
; CHECK-LABEL: round_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0)
+; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
-; CHECK-NEXT: vfadd.vf v12, v12, ft1
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
+; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -302,13 +302,13 @@
; CHECK-LABEL: round_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
-; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0)
+; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
-; CHECK-NEXT: vfadd.vf v16, v16, ft1
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
+; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
@@ -8,10 +8,10 @@
; CHECK-LABEL: trunc_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -26,10 +26,10 @@
; CHECK-LABEL: trunc_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -44,10 +44,10 @@
; CHECK-LABEL: trunc_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -62,10 +62,10 @@
; CHECK-LABEL: trunc_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -80,10 +80,10 @@
; CHECK-LABEL: trunc_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -98,10 +98,10 @@
; CHECK-LABEL: trunc_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
-; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
@@ -116,10 +116,10 @@
; CHECK-LABEL: trunc_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -134,10 +134,10 @@
; CHECK-LABEL: trunc_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -152,10 +152,10 @@
; CHECK-LABEL: trunc_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -170,10 +170,10 @@
; CHECK-LABEL: trunc_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -188,10 +188,10 @@
; CHECK-LABEL: trunc_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
-; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
@@ -206,10 +206,10 @@
; CHECK-LABEL: trunc_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v9, ft0
+; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8
@@ -224,10 +224,10 @@
; CHECK-LABEL: trunc_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v10, ft0
+; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8
@@ -242,10 +242,10 @@
; CHECK-LABEL: trunc_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v12, ft0
+; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8
@@ -260,10 +260,10 @@
; CHECK-LABEL: trunc_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
-; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
-; CHECK-NEXT: vmflt.vf v0, v16, ft0
+; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
@@ -2512,10 +2512,10 @@
define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.d.w ft0, zero
+; CHECK-NEXT: fcvt.d.w fa0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v24, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
@@ -2512,10 +2512,10 @@
define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.d.x ft0, zero
+; CHECK-NEXT: fmv.d.x fa0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v24, v16, ft0
-; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -1540,10 +1540,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB26_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fmul.s ft0, ft0, fa0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fmul.s fa1, fa1, fa0
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB26_6
@@ -1632,10 +1632,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB27_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fdiv.s ft0, ft0, fa0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fdiv.s fa1, fa1, fa0
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB27_6
@@ -1724,10 +1724,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB28_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fdiv.s ft0, fa0, ft0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fdiv.s fa1, fa0, fa1
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB28_6
@@ -1816,10 +1816,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB29_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fadd.s ft0, ft0, fa0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fadd.s fa1, fa1, fa0
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB29_6
@@ -1908,10 +1908,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB30_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fsub.s ft0, ft0, fa0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fsub.s fa1, fa1, fa0
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB30_6
@@ -2000,10 +2000,10 @@
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB31_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
+; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: fsub.s ft0, fa0, ft0
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fsub.s fa1, fa0, fa1
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB31_6
@@ -2178,11 +2178,11 @@
; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB34_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
-; CHECK-NEXT: flw ft1, 0(a1)
+; CHECK-NEXT: flw fa1, 0(a0)
+; CHECK-NEXT: flw fa2, 0(a1)
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: fmadd.s ft0, ft0, fa0, ft1
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fmadd.s fa1, fa1, fa0, fa2
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: addi a0, a0, 4
@@ -2281,11 +2281,11 @@
; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB35_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: flw ft0, 0(a0)
-; CHECK-NEXT: flw ft1, 0(a1)
+; CHECK-NEXT: flw fa1, 0(a0)
+; CHECK-NEXT: flw fa2, 0(a1)
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: fmadd.s ft0, fa0, ft0, ft1
-; CHECK-NEXT: fsw ft0, 0(a0)
+; CHECK-NEXT: fmadd.s fa1, fa0, fa1, fa2
+; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: addi a0, a0, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -9,14 +9,14 @@
define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
ret half %red
@@ -40,14 +40,14 @@
define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
ret half %red
@@ -71,14 +71,14 @@
define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: fneg.h ft0, ft0
+; CHECK-NEXT: fmv.h.x fa1, zero
+; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
ret half %red
@@ -102,14 +102,14 @@
define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -131,15 +131,15 @@
define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
@@ -166,14 +166,14 @@
define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -195,15 +195,15 @@
define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
@@ -230,14 +230,14 @@
define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v10, ft0
+; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red
@@ -259,15 +259,15 @@
define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: fneg.s ft0, ft0
+; CHECK-NEXT: fmv.w.x fa1, zero
+; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v9, ft0
+; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
@@ -294,26 +294,26 @@
define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv1f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v9
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_nxv1f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v9
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
@@ -335,28 +335,28 @@
define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv1f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_nxv1f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
@@ -383,26 +383,26 @@
define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv2f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v10, ft0
+; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v10
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_nxv2f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v10, ft0
+; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v10
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
ret double %red
@@ -424,28 +424,28 @@
define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv2f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v9, ft0
+; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_nxv2f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v9, ft0
+; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
@@ -472,26 +472,26 @@
define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv4f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v12, ft0
+; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v12
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_nxv4f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v12, ft0
+; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v12
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
ret double %red
@@ -513,28 +513,28 @@
define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv4f64:
; RV32: # %bb.0:
-; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: fneg.d ft0, ft0
+; RV32-NEXT: fcvt.d.w fa1, zero
+; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vfmv.s.f v10, ft0
+; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV32-NEXT: vfmv.f.s ft0, v8
-; RV32-NEXT: fadd.d fa0, fa0, ft0
+; RV32-NEXT: vfmv.f.s fa1, v8
+; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_fwadd_nxv4f64:
; RV64: # %bb.0:
-; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: fneg.d ft0, ft0
+; RV64-NEXT: fmv.d.x fa1, zero
+; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vfmv.s.f v10, ft0
+; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v10
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; RV64-NEXT: vfmv.f.s ft0, v8
-; RV64-NEXT: fadd.d fa0, fa0, ft0
+; RV64-NEXT: vfmv.f.s fa1, v8
+; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret
%e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
@@ -1163,8 +1163,8 @@
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: vfmv.f.s fa1, v8
+; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret
%red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -108,10 +108,10 @@
; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: bltu a0, a1, .LBB6_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a1
@@ -143,10 +143,10 @@
; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: bltu a0, a1, .LBB7_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a1
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -244,13 +244,13 @@
; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI4_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
+; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
-; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
+; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_const_fp:
@@ -265,13 +265,13 @@
; RV32IFBT-NEXT: bnez a0, .LBB4_2
; RV32IFBT-NEXT: # %bb.1:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_0)
-; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV32IFBT-NEXT: fmv.x.w a0, ft0
+; RV32IFBT-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
+; RV32IFBT-NEXT: fmv.x.w a0, fa0
; RV32IFBT-NEXT: ret
; RV32IFBT-NEXT: .LBB4_2:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_1)
-; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
-; RV32IFBT-NEXT: fmv.x.w a0, ft0
+; RV32IFBT-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
+; RV32IFBT-NEXT: fmv.x.w a0, fa0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_fp:
@@ -289,13 +289,13 @@
; RV64IFD-NEXT: bnez a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
-; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV64IFD-NEXT: fmv.x.w a0, ft0
+; RV64IFD-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
+; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
-; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
-; RV64IFD-NEXT: fmv.x.w a0, ft0
+; RV64IFD-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
+; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_fp:
@@ -310,13 +310,13 @@
; RV64IFDBT-NEXT: bnez a0, .LBB4_2
; RV64IFDBT-NEXT: # %bb.1:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_0)
-; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
-; RV64IFDBT-NEXT: fmv.x.w a0, ft0
+; RV64IFDBT-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
+; RV64IFDBT-NEXT: fmv.x.w a0, fa0
; RV64IFDBT-NEXT: ret
; RV64IFDBT-NEXT: .LBB4_2:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1)
-; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
-; RV64IFDBT-NEXT: fmv.x.w a0, ft0
+; RV64IFDBT-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
+; RV64IFDBT-NEXT: fmv.x.w a0, fa0
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, float 3.0, float 4.0
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -272,15 +272,15 @@
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: fmv.w.x ft0, a4
-; RV32I-NEXT: fmv.w.x ft1, a2
+; RV32I-NEXT: fmv.w.x fa0, a4
+; RV32I-NEXT: fmv.w.x fa1, a2
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2:
-; RV32I-NEXT: fmv.w.x ft0, a3
-; RV32I-NEXT: fmv.w.x ft1, a1
+; RV32I-NEXT: fmv.w.x fa0, a3
+; RV32I-NEXT: fmv.w.x fa1, a1
; RV32I-NEXT: .LBB4_3: # %entry
-; RV32I-NEXT: fadd.s ft0, ft1, ft0
-; RV32I-NEXT: fmv.x.w a0, ft0
+; RV32I-NEXT: fadd.s fa0, fa1, fa0
+; RV32I-NEXT: fmv.x.w a0, fa0
; RV32I-NEXT: ret
;
; RV32IBT-LABEL: cmovfloat:
@@ -288,15 +288,15 @@
; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: bnez a0, .LBB4_2
; RV32IBT-NEXT: # %bb.1: # %entry
-; RV32IBT-NEXT: fmv.w.x ft0, a4
-; RV32IBT-NEXT: fmv.w.x ft1, a2
+; RV32IBT-NEXT: fmv.w.x fa0, a4
+; RV32IBT-NEXT: fmv.w.x fa1, a2
; RV32IBT-NEXT: j .LBB4_3
; RV32IBT-NEXT: .LBB4_2:
-; RV32IBT-NEXT: fmv.w.x ft0, a3
-; RV32IBT-NEXT: fmv.w.x ft1, a1
+; RV32IBT-NEXT: fmv.w.x fa0, a3
+; RV32IBT-NEXT: fmv.w.x fa1, a1
; RV32IBT-NEXT: .LBB4_3: # %entry
-; RV32IBT-NEXT: fadd.s ft0, ft1, ft0
-; RV32IBT-NEXT: fmv.x.w a0, ft0
+; RV32IBT-NEXT: fadd.s fa0, fa1, fa0
+; RV32IBT-NEXT: fmv.x.w a0, fa0
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovfloat:
@@ -304,15 +304,15 @@
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %entry
-; RV64I-NEXT: fmv.w.x ft0, a4
-; RV64I-NEXT: fmv.w.x ft1, a2
+; RV64I-NEXT: fmv.w.x fa0, a4
+; RV64I-NEXT: fmv.w.x fa1, a2
; RV64I-NEXT: j .LBB4_3
; RV64I-NEXT: .LBB4_2:
-; RV64I-NEXT: fmv.w.x ft0, a3
-; RV64I-NEXT: fmv.w.x ft1, a1
+; RV64I-NEXT: fmv.w.x fa0, a3
+; RV64I-NEXT: fmv.w.x fa1, a1
; RV64I-NEXT: .LBB4_3: # %entry
-; RV64I-NEXT: fadd.s ft0, ft1, ft0
-; RV64I-NEXT: fmv.x.w a0, ft0
+; RV64I-NEXT: fadd.s fa0, fa1, fa0
+; RV64I-NEXT: fmv.x.w a0, fa0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovfloat:
@@ -320,15 +320,15 @@
; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB4_2
; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: fmv.w.x ft0, a4
-; RV64IBT-NEXT: fmv.w.x ft1, a2
+; RV64IBT-NEXT: fmv.w.x fa0, a4
+; RV64IBT-NEXT: fmv.w.x fa1, a2
; RV64IBT-NEXT: j .LBB4_3
; RV64IBT-NEXT: .LBB4_2:
-; RV64IBT-NEXT: fmv.w.x ft0, a3
-; RV64IBT-NEXT: fmv.w.x ft1, a1
+; RV64IBT-NEXT: fmv.w.x fa0, a3
+; RV64IBT-NEXT: fmv.w.x fa1, a1
; RV64IBT-NEXT: .LBB4_3: # %entry
-; RV64IBT-NEXT: fadd.s ft0, ft1, ft0
-; RV64IBT-NEXT: fmv.x.w a0, ft0
+; RV64IBT-NEXT: fadd.s fa0, fa1, fa0
+; RV64IBT-NEXT: fmv.x.w a0, fa0
; RV64IBT-NEXT: ret
entry:
%cond1 = select i1 %a, float %b, float %c
@@ -343,15 +343,15 @@
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: sw a4, 12(sp)
-; RV32I-NEXT: fld ft0, 8(sp)
+; RV32I-NEXT: fld fa0, 8(sp)
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: fld ft0, 8(sp)
+; RV32I-NEXT: fld fa0, 8(sp)
; RV32I-NEXT: .LBB5_2: # %entry
-; RV32I-NEXT: fsd ft0, 8(sp)
+; RV32I-NEXT: fsd fa0, 8(sp)
; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw a1, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@@ -362,15 +362,15 @@
; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw a3, 8(sp)
; RV32IBT-NEXT: sw a4, 12(sp)
-; RV32IBT-NEXT: fld ft0, 8(sp)
+; RV32IBT-NEXT: fld fa0, 8(sp)
; RV32IBT-NEXT: sw a1, 8(sp)
; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: sw a2, 12(sp)
; RV32IBT-NEXT: beqz a0, .LBB5_2
; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: fld ft0, 8(sp)
+; RV32IBT-NEXT: fld fa0, 8(sp)
; RV32IBT-NEXT: .LBB5_2: # %entry
-; RV32IBT-NEXT: fsd ft0, 8(sp)
+; RV32IBT-NEXT: fsd fa0, 8(sp)
; RV32IBT-NEXT: lw a0, 8(sp)
; RV32IBT-NEXT: lw a1, 12(sp)
; RV32IBT-NEXT: addi sp, sp, 16
@@ -381,12 +381,12 @@
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %entry
-; RV64I-NEXT: fmv.d.x ft0, a2
-; RV64I-NEXT: fmv.x.d a0, ft0
+; RV64I-NEXT: fmv.d.x fa0, a2
+; RV64I-NEXT: fmv.x.d a0, fa0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
-; RV64I-NEXT: fmv.d.x ft0, a1
-; RV64I-NEXT: fmv.x.d a0, ft0
+; RV64I-NEXT: fmv.d.x fa0, a1
+; RV64I-NEXT: fmv.x.d a0, fa0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovdouble:
@@ -394,12 +394,12 @@
; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB5_2
; RV64IBT-NEXT: # %bb.1: # %entry
-; RV64IBT-NEXT: fmv.d.x ft0, a2
-; RV64IBT-NEXT: fmv.x.d a0, ft0
+; RV64IBT-NEXT: fmv.d.x fa0, a2
+; RV64IBT-NEXT: fmv.x.d a0, fa0
; RV64IBT-NEXT: ret
; RV64IBT-NEXT: .LBB5_2:
-; RV64IBT-NEXT: fmv.d.x ft0, a1
-; RV64IBT-NEXT: fmv.x.d a0, ft0
+; RV64IBT-NEXT: fmv.d.x fa0, a1
+; RV64IBT-NEXT: fmv.x.d a0, fa0
; RV64IBT-NEXT: ret
entry:
%cond = select i1 %a, double %b, double %c
diff --git a/llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll b/llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
--- a/llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ b/llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -16,13 +16,13 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fsh ft0, 14(sp) # 2-byte Folded Spill
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: fsh fa0, 14(sp) # 2-byte Folded Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: flh ft0, 14(sp) # 2-byte Folded Reload
-; CHECK-NEXT: vfmv.v.f v8, ft0
+; CHECK-NEXT: flh fa0, 14(sp) # 2-byte Folded Reload
+; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -37,13 +37,13 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT: vfmv.v.f v8, ft0
+; CHECK-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -58,13 +58,13 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.f.s ft0, v8
-; CHECK-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vfmv.v.f v8, ft0
+; CHECK-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
--- a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
+++ b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
@@ -9,8 +9,8 @@
define float @foo(i32 %a) nounwind #0 {
-; RV32IF-ILP32: fcvt.s.w ft0, a0
-; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0
+; RV32IF-ILP32: fcvt.s.w fa0, a0
+; RV32IF-ILP32-NEXT: fmv.x.w a0, fa0
; RV32IF-ILP32F: fcvt.s.w fa0, a0
; RV32IF-ILP32F-NEXT: ret
%conv = sitofp i32 %a to float
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -689,8 +689,8 @@
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 0(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld fa0, 0(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd fa0, 0(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
@@ -1019,8 +1019,8 @@
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 8(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld fa0, 0(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd fa0, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0
diff --git a/llvm/test/CodeGen/RISCV/zfh-imm.ll b/llvm/test/CodeGen/RISCV/zfh-imm.ll
--- a/llvm/test/CodeGen/RISCV/zfh-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zfh-imm.ll
@@ -34,26 +34,26 @@
define half @f16_negative_zero(half *%pf) nounwind {
; RV32IZFH-LABEL: f16_negative_zero:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fneg.h fa0, ft0
+; RV32IZFH-NEXT: fmv.h.x fa0, zero
+; RV32IZFH-NEXT: fneg.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: f16_negative_zero:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmv.h.x ft0, zero
-; RV32IDZFH-NEXT: fneg.h fa0, ft0
+; RV32IDZFH-NEXT: fmv.h.x fa0, zero
+; RV32IDZFH-NEXT: fneg.h fa0, fa0
; RV32IDZFH-NEXT: ret
;
; RV64IZFH-LABEL: f16_negative_zero:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fneg.h fa0, ft0
+; RV64IZFH-NEXT: fmv.h.x fa0, zero
+; RV64IZFH-NEXT: fneg.h fa0, fa0
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: f16_negative_zero:
; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmv.h.x ft0, zero
-; RV64IDZFH-NEXT: fneg.h fa0, ft0
+; RV64IDZFH-NEXT: fmv.h.x fa0, zero
+; RV64IDZFH-NEXT: fneg.h fa0, fa0
; RV64IDZFH-NEXT: ret
ret half -0.0
}