diff --git a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
--- a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
+++ b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
@@ -25,7 +25,6 @@
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/Value.h"
-#include "llvm/Support/KnownBits.h"
 #include <cassert>
 #include <utility>
 #include <vector>
@@ -152,11 +151,15 @@
   MachineBasicBlock::iterator InsertPt;
 
   struct LiveOutInfo {
-    unsigned NumSignBits : 31;
-    unsigned IsValid : 1;
-    KnownBits Known = 1;
+    unsigned NumSignBits;
+    unsigned LeadingZeros;
 
-    LiveOutInfo() : NumSignBits(0), IsValid(true) {}
+    LiveOutInfo() : NumSignBits(1), LeadingZeros(0) {}
+
+    void reset() {
+      NumSignBits = 1;
+      LeadingZeros = 0;
+    }
   };
 
   /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
@@ -218,31 +221,20 @@
       return nullptr;
 
     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
-    if (!LOI->IsValid)
-      return nullptr;
-
     return LOI;
   }
 
-  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
-  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
-  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
-  /// the larger bit width by zero extension. The bit width must be no smaller
-  /// than the LiveOutInfo's existing bit width.
-  const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
-
   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
   void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
-                         const KnownBits &Known) {
+                         unsigned LeadingZeros) {
     // Only install this information if it tells us something.
-    if (NumSignBits == 1 && Known.isUnknown())
+    if (NumSignBits == 1 && LeadingZeros == 0)
       return;
 
     LiveOutRegInfo.grow(Reg);
     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
     LOI.NumSignBits = NumSignBits;
-    LOI.Known.One = Known.One;
-    LOI.Known.Zero = Known.Zero;
+    LOI.LeadingZeros = LeadingZeros;
   }
 
   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
@@ -262,7 +254,7 @@
       return;
 
     LiveOutRegInfo.grow(Reg);
-    LiveOutRegInfo[Reg].IsValid = false;
+    LiveOutRegInfo[Reg].reset();
   }
 
   /// setArgumentFrameIndex - Record frame index for the byval
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -405,28 +405,6 @@
                     !TLI->requiresUniformRegister(*MF, V));
 }
 
-/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
-/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
-/// the register's LiveOutInfo is for a smaller bit width, it is extended to
-/// the larger bit width by zero extension. The bit width must be no smaller
-/// than the LiveOutInfo's existing bit width.
-const FunctionLoweringInfo::LiveOutInfo *
-FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
-  if (!LiveOutRegInfo.inBounds(Reg))
-    return nullptr;
-
-  LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
-  if (!LOI->IsValid)
-    return nullptr;
-
-  if (BitWidth > LOI->Known.getBitWidth()) {
-    LOI->NumSignBits = 1;
-    LOI->Known = LOI->Known.anyext(BitWidth);
-  }
-
-  return LOI;
-}
-
 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
 /// register based on the LiveOutInfo of its operands.
 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
@@ -453,48 +431,42 @@
 
   Value *V = PN->getIncomingValue(0);
   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
-    DestLOI.NumSignBits = 1;
-    DestLOI.Known = KnownBits(BitWidth);
+    DestLOI.reset();
     return;
   }
 
   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
     APInt Val = CI->getValue().zextOrSelf(BitWidth);
     DestLOI.NumSignBits = Val.getNumSignBits();
-    DestLOI.Known = KnownBits::makeConstant(Val);
+    DestLOI.LeadingZeros = Val.countLeadingZeros();
   } else {
     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
                                 "CopyToReg node was created.");
     Register SrcReg = ValueMap[V];
     if (!Register::isVirtualRegister(SrcReg)) {
-      DestLOI.IsValid = false;
+      DestLOI.reset();
       return;
     }
-    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
+    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg);
     if (!SrcLOI) {
-      DestLOI.IsValid = false;
+      DestLOI.reset();
       return;
     }
     DestLOI = *SrcLOI;
   }
 
-  assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
-         DestLOI.Known.One.getBitWidth() == BitWidth &&
-         "Masks should have the same bit width as the type.");
-
   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
     Value *V = PN->getIncomingValue(i);
     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
-      DestLOI.NumSignBits = 1;
-      DestLOI.Known = KnownBits(BitWidth);
+      DestLOI.reset();
       return;
     }
 
     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
       APInt Val = CI->getValue().zextOrSelf(BitWidth);
       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
-      DestLOI.Known.Zero &= ~Val;
-      DestLOI.Known.One &= Val;
+      DestLOI.LeadingZeros =
+          std::min(DestLOI.LeadingZeros, Val.countLeadingZeros());
       continue;
     }
 
@@ -502,16 +474,16 @@
                                 "its CopyToReg node was created.");
     Register SrcReg = ValueMap[V];
     if (!SrcReg.isVirtual()) {
-      DestLOI.IsValid = false;
+      DestLOI.reset();
       return;
     }
-    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
+    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg);
     if (!SrcLOI) {
-      DestLOI.IsValid = false;
+      DestLOI.reset();
       return;
     }
     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
-    DestLOI.Known = KnownBits::commonBits(DestLOI.Known, SrcLOI->Known);
+    DestLOI.LeadingZeros = std::min(DestLOI.LeadingZeros, SrcLOI->LeadingZeros);
   }
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -861,7 +861,7 @@
 
       unsigned RegSize = RegisterVT.getScalarSizeInBits();
       unsigned NumSignBits = LOI->NumSignBits;
-      unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
+      unsigned NumZeroBits = LOI->LeadingZeros;
 
       if (NumZeroBits == RegSize) {
         // The current value is a zero.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -757,8 +757,9 @@
       continue;
 
     unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
-    Known = CurDAG->computeKnownBits(Src);
-    FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, Known);
+    unsigned NumLeadingZeros =
+        CurDAG->computeKnownBits(Src).countMinLeadingZeros();
+    FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, NumLeadingZeros);
   } while (!Worklist.empty());
 }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -25,6 +25,7 @@
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/InitializePasses.h"
+#include "llvm/Support/KnownBits.h"
 
 #ifdef EXPENSIVE_CHECKS
 #include "llvm/Analysis/LoopInfo.h"