Index: lib/Target/Sparc/SparcFrameLowering.h =================================================================== --- lib/Target/Sparc/SparcFrameLowering.h +++ lib/Target/Sparc/SparcFrameLowering.h @@ -39,6 +39,8 @@ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; + int getFrameIndexReference(const MachineFunction &MF, int FI, + unsigned &FrameReg) const override; private: // Remap input registers to output registers for leaf procedure. void remapRegsForLeafProc(MachineFunction &MF) const; Index: lib/Target/Sparc/SparcFrameLowering.cpp =================================================================== --- lib/Target/Sparc/SparcFrameLowering.cpp +++ lib/Target/Sparc/SparcFrameLowering.cpp @@ -90,8 +90,22 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); + const SparcRegisterInfo &RegInfo = + *static_cast(MF.getSubtarget().getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); + + // TODO: unfortunately, returning false from canRealignStack + // actually just causes needsStackRealignment to return false, + // rather than reporting an error, as would be sensible. This is + // poor, but fixing that bogosity is going to be a large project. + + // For now, just see if it's lied, and report an error here. + if (!NeedsStackRealignment && MFI->getMaxAlignment() > getStackAlignment()) + report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required " + "stack re-alignment, but LLVM couldn't handle it " + "(probably because it has a dynamic alloca)."); // Get the number of bytes to allocate from the FrameInfo int NumBytes = (int) MFI->getStackSize(); @@ -104,12 +118,14 @@ SAVEri = SP::ADDri; SAVErr = SP::ADDrr; } - NumBytes = -MF.getSubtarget().getAdjustedFrameSize(NumBytes); - emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri); + + NumBytes = MF.getSubtarget().getAdjustedFrameSize(NumBytes); + MFI->setStackSize(NumBytes); // Update stack size with corrected value. + + emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri); MachineModuleInfo &MMI = MF.getMMI(); - const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); + unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); // Emit ".cfi_def_cfa_register 30". unsigned CFIIndex = @@ -122,13 +138,19 @@ BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); - unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); - unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); + unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); + unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); // Emit ".cfi_register 15, 31". CFIIndex = MMI.addFrameInst( MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); + + if (NeedsStackRealignment) { + // andn %o6, MaxAlign-1, %o6 + int MaxAlign = MFI->getMaxAlignment(); + BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1); + } } void SparcFrameLowering:: @@ -167,7 +189,6 @@ if (NumBytes == 0) return; - NumBytes = MF.getSubtarget().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); } @@ -180,12 +201,62 @@ // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. bool SparcFrameLowering::hasFP(const MachineFunction &MF) const { + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); return MF.getTarget().Options.DisableFramePointerElim(MF) || - MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); + RegInfo->needsStackRealignment(MF) || + MFI->hasVarSizedObjects() || + MFI->isFrameAddressTaken(); } +int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + unsigned &FrameReg) const { + const SparcSubtarget &Subtarget = MF.getSubtarget(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); + const SparcMachineFunctionInfo *FuncInfo = MF.getInfo(); + bool isFixed = MFI->isFixedObjectIndex(FI); + + // Addressable stack objects are accessed using neg. offsets from + // %fp, or positive offsets from %sp. + + + // Sparc uses FP-based references in general, even when "hasFP" is + // false. That function is rather a misnomer, because %fp is + // actually always available, unless isLeafProc. + bool UseFP; + + if (FuncInfo->isLeafProc()) { + // If there's a leaf proc, all offsets need to be %sp-based, + // because we haven't caused %fp to actually point to our frame. + UseFP = false; + } else if (isFixed) { + // Otherwise, argument access should always use %fp. + UseFP = true; + } else if (RegInfo->needsStackRealignment(MF)) { + // If there is dynamic stack realignment, all local object + // references need to be via %sp, to take account of the + // re-alignment. + UseFP = false; + } else { + // Finally, default to using %fp. + UseFP = true; + } + + int64_t FrameOffset = MF.getFrameInfo()->getObjectOffset(FI) + + Subtarget.getStackPointerBias(); + + if (UseFP) { + FrameReg = RegInfo->getFrameRegister(MF); + return FrameOffset; + } else { + FrameReg = SP::O6; // %sp + return FrameOffset + MF.getFrameInfo()->getStackSize(); + } +} + static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) { Index: lib/Target/Sparc/SparcRegisterInfo.h =================================================================== --- lib/Target/Sparc/SparcRegisterInfo.h +++ lib/Target/Sparc/SparcRegisterInfo.h @@ -42,8 +42,10 @@ void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS = nullptr) const; - // Debug information queries. unsigned getFrameRegister(const MachineFunction &MF) const override; + + bool canRealignStack(const MachineFunction &MF) const override; + }; } // end namespace llvm Index: lib/Target/Sparc/SparcRegisterInfo.cpp =================================================================== --- lib/Target/Sparc/SparcRegisterInfo.cpp +++ lib/Target/Sparc/SparcRegisterInfo.cpp @@ -170,21 +170,15 @@ MachineInstr &MI = *II; DebugLoc dl = MI.getDebugLoc(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - - // Addressable stack objects are accessed using neg. offsets from %fp MachineFunction &MF = *MI.getParent()->getParent(); const SparcSubtarget &Subtarget = MF.getSubtarget(); - int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + - MI.getOperand(FIOperandNum + 1).getImm() + - Subtarget.getStackPointerBias(); - SparcMachineFunctionInfo *FuncInfo = MF.getInfo(); - unsigned FramePtr = SP::I6; - if (FuncInfo->isLeafProc()) { - // Use %sp and adjust offset if needed. - FramePtr = SP::O6; - int stackSize = MF.getFrameInfo()->getStackSize(); - Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ; - } + const SparcFrameLowering *TFI = getFrameLowering(MF); + + unsigned FrameReg; + int Offset; + Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); + + Offset += MI.getOperand(FIOperandNum + 1).getImm(); // WTF is this about?? if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { if (MI.getOpcode() == SP::STQFri) { @@ -194,8 +188,8 @@ unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); MachineInstr *StMI = BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) - .addReg(FramePtr).addImm(0).addReg(SrcEvenReg); - replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr); + .addReg(FrameReg).addImm(0).addReg(SrcEvenReg); + replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg); MI.setDesc(TII.get(SP::STDFri)); MI.getOperand(2).setReg(SrcOddReg); Offset += 8; @@ -206,8 +200,8 @@ unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); MachineInstr *StMI = BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg) - .addReg(FramePtr).addImm(0); - replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr); + .addReg(FrameReg).addImm(0); + replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg); MI.setDesc(TII.get(SP::LDDFri)); MI.getOperand(0).setReg(DestOddReg); @@ -215,10 +209,33 @@ } } - replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr); + replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg); } unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { return SP::I6; } + +// Sparc has no architectural need for stack realignment support, +// except that LLVM unfortunately currently implements overaligned +// stack objects by depending upon stack realignment support. +// If that ever changes, this can probably be deleted. +bool SparcRegisterInfo::canRealignStack(const MachineFunction &MF) const { + if (!TargetRegisterInfo::canRealignStack(MF)) + return false; + + // Sparc always has a fixed frame pointer register, so don't need to + // worry about needing to reserve it. [even if we don't have a frame + // pointer for our frame, it still cannot be used for other things, + // or register window traps will be SADNESS.] + + // If there's a reserved call frame, we can use SP to access locals. + if (getFrameLowering(MF)->hasReservedCallFrame(MF)) + return true; + + // Otherwise, we'd need a base pointer, but those aren't implemented + // for SPARC at the moment. + + return false; +} Index: test/CodeGen/SPARC/fp128.ll =================================================================== --- test/CodeGen/SPARC/fp128.ll +++ test/CodeGen/SPARC/fp128.ll @@ -45,14 +45,14 @@ ; HARD: std %f{{.+}}, [%[[S1:.+]]] ; HARD-DAG: ldd [%[[S0]]], %f{{.+}} ; HARD-DAG: ldd [%[[S1]]], %f{{.+}} -; HARD: jmp %o7+12 +; HARD: jmp {{%[oi]7}}+12 ; SOFT-LABEL: f128_spill ; SOFT: std %f{{.+}}, [%[[S0:.+]]] ; SOFT: std %f{{.+}}, [%[[S1:.+]]] ; SOFT-DAG: ldd [%[[S0]]], %f{{.+}} ; SOFT-DAG: ldd [%[[S1]]], %f{{.+}} -; SOFT: jmp %o7+12 +; SOFT: jmp {{%[oi]7}}+12 define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { entry: Index: test/CodeGen/SPARC/stack-align.ll =================================================================== --- /dev/null +++ test/CodeGen/SPARC/stack-align.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=sparc < %s | FileCheck %s +declare void @stack_realign_helper(i32 %a, i32* %b) + +@foo = global i32 1 + +;; This is a function where we have a local variable of 64-byte +;; alignment. We want to see that the stack is aligned (the initial +;; andn), that the local var is accessed via stack pointer (to %o0), and that +;; the argument is accessed via frame pointer not stack pointer (to %o1). + +;; CHECK-LABEL: stack_realign: +;; CHECK: andn %sp, 63, %sp +;; CHECK-NEXT: ld [%fp+92], %o0 +;; CHECK-NEXT: call stack_realign_helper +;; CHECK-NEXT: add %sp, 96, %o1 + +define void @stack_realign(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) { +entry: + %aligned = alloca i32, align 64 + call void @stack_realign_helper(i32 %g, i32* %aligned) + ret void +}