Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -347,10 +347,14 @@ // Standalone (codegen-only) immleaf patterns. -// A 12-bit signed immediate plus one where the imm range will be -2047~2048. +// A 12-bit signed immediate plus one where the imm range will be [-2047, 2048]. def simm12_plus1 : ImmLeaf(Imm) && Imm != -2048) || Imm == 2048;}]>; +// A 12-bit signed immediate sub one where the imm range will be [-2049, 2046]. +def simm12_sub1 : ImmLeaf(Imm) && Imm != 2047) || Imm == -2049;}]>; + // A 6-bit constant greater than 32. def uimm6gt32 : ImmLeaf(Imm) && Imm > 32; @@ -373,9 +377,9 @@ N->getValueType(0)); }]>; -// Return an immediate value plus 32. -def ImmPlus32 : SDNodeXFormgetTargetConstant(N->getSExtValue() + 32, SDLoc(N), +// Return an immediate value plus 1. +def ImmPlus1 : SDNodeXFormgetTargetConstant(N->getSExtValue() + 1, SDLoc(N), N->getValueType(0)); }]>; @@ -1208,6 +1212,10 @@ def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>; def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; +def : Pat<(setgt GPR:$rs1, simm12_sub1:$imm), + (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1:$imm)), 1)>; +def : Pat<(setugt GPR:$rs1, simm12_sub1:$imm), + (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1:$imm)), 1)>; def IntCCtoRISCVCC : SDNodeXForm(N->getOperand(2))->get(); Index: llvm/test/CodeGen/RISCV/arith-with-overflow.ll =================================================================== --- llvm/test/CodeGen/RISCV/arith-with-overflow.ll +++ llvm/test/CodeGen/RISCV/arith-with-overflow.ll @@ -27,11 +27,12 @@ define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: ssub: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: sgtz a3, a1 -; RV32I-NEXT: sub a1, a0, a1 -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: xor a0, a3, a0 -; RV32I-NEXT: sw a1, 0(a2) +; RV32I-NEXT: sub a3, a0, a1 +; RV32I-NEXT: slt a0, a3, a0 +; RV32I-NEXT: slti a1, a1, 1 +; RV32I-NEXT: xori a1, a1, 1 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: sw a3, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) Index: llvm/test/CodeGen/RISCV/double-fcmp-strict.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-fcmp-strict.ll +++ llvm/test/CodeGen/RISCV/double-fcmp-strict.ll @@ -68,7 +68,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtdf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -78,7 +79,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtdf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -109,8 +111,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -120,8 +122,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -451,7 +453,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ledf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -461,7 +464,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ledf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -494,8 +498,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -505,8 +509,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -735,7 +739,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtdf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -745,7 +750,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtdf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -770,8 +776,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -781,8 +787,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1066,7 +1072,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ledf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1076,7 +1083,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ledf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1103,8 +1111,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1114,8 +1122,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret Index: llvm/test/CodeGen/RISCV/double-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-fcmp.ll +++ llvm/test/CodeGen/RISCV/double-fcmp.ll @@ -84,7 +84,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtdf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -94,7 +95,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtdf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -119,8 +121,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -130,8 +132,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -415,7 +417,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ledf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -425,7 +428,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ledf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -452,8 +456,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -463,8 +467,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret Index: llvm/test/CodeGen/RISCV/float-fcmp-strict.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-fcmp-strict.ll +++ llvm/test/CodeGen/RISCV/float-fcmp-strict.ll @@ -68,7 +68,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtsf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -78,7 +79,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtsf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -109,8 +111,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -120,8 +122,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -435,7 +437,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __lesf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -445,7 +448,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __lesf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -478,8 +482,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -489,8 +493,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -719,7 +723,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtsf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -729,7 +734,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtsf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -754,8 +760,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -765,8 +771,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1034,7 +1040,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __lesf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1044,7 +1051,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __lesf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1071,8 +1079,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1082,8 +1090,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret Index: llvm/test/CodeGen/RISCV/float-fcmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-fcmp.ll +++ llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -84,7 +84,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gtsf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -94,7 +95,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gtsf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -119,8 +121,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -130,8 +132,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -399,7 +401,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __lesf2@plt -; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: slti a0, a0, 1 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -409,7 +412,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __lesf2@plt -; RV64I-NEXT: sgtz a0, a0 +; RV64I-NEXT: slti a0, a0, 1 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -436,8 +440,8 @@ ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2@plt -; RV32I-NEXT: li a1, -1 -; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -447,8 +451,8 @@ ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2@plt -; RV64I-NEXT: li a1, -1 -; RV64I-NEXT: slt a0, a1, a0 +; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret Index: llvm/test/CodeGen/RISCV/fpclamptosat.ll =================================================================== --- llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -35,7 +35,8 @@ ; RV32IF-NEXT: li a3, -1 ; RV32IF-NEXT: beq a1, a3, .LBB0_6 ; RV32IF-NEXT: # %bb.5: # %entry -; RV32IF-NEXT: slt a1, a3, a1 +; RV32IF-NEXT: slti a1, a1, 0 +; RV32IF-NEXT: xori a1, a1, 1 ; RV32IF-NEXT: beqz a1, .LBB0_7 ; RV32IF-NEXT: j .LBB0_8 ; RV32IF-NEXT: .LBB0_6: @@ -195,7 +196,8 @@ ; RV32IF-NEXT: .LBB2_4: # %entry ; RV32IF-NEXT: beqz a1, .LBB2_6 ; RV32IF-NEXT: # %bb.5: # %entry -; RV32IF-NEXT: sgtz a1, a1 +; RV32IF-NEXT: slti a1, a1, 1 +; RV32IF-NEXT: xori a1, a1, 1 ; RV32IF-NEXT: beqz a1, .LBB2_7 ; RV32IF-NEXT: j .LBB2_8 ; RV32IF-NEXT: .LBB2_6: @@ -391,7 +393,8 @@ ; RV32-NEXT: li a3, -1 ; RV32-NEXT: beq a1, a3, .LBB6_6 ; RV32-NEXT: # %bb.5: # %entry -; RV32-NEXT: slt a1, a3, a1 +; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: xori a1, a1, 1 ; RV32-NEXT: beqz a1, .LBB6_7 ; RV32-NEXT: j .LBB6_8 ; RV32-NEXT: .LBB6_6: @@ -513,7 +516,8 @@ ; RV32-NEXT: .LBB8_4: # %entry ; RV32-NEXT: beqz a1, .LBB8_6 ; RV32-NEXT: # %bb.5: # %entry -; RV32-NEXT: sgtz a1, a1 +; RV32-NEXT: slti a1, a1, 1 +; RV32-NEXT: xori a1, a1, 1 ; RV32-NEXT: beqz a1, .LBB8_7 ; RV32-NEXT: j .LBB8_8 ; RV32-NEXT: .LBB8_6: @@ -1137,7 +1141,8 @@ ; RV32IF-NEXT: and a3, a3, a2 ; RV32IF-NEXT: beq a3, a6, .LBB18_10 ; RV32IF-NEXT: .LBB18_9: # %entry -; RV32IF-NEXT: slt a4, a6, a2 +; RV32IF-NEXT: slti a2, a2, 0 +; RV32IF-NEXT: xori a4, a2, 1 ; RV32IF-NEXT: .LBB18_10: # %entry ; RV32IF-NEXT: bnez a4, .LBB18_12 ; RV32IF-NEXT: # %bb.11: # %entry @@ -1172,7 +1177,8 @@ ; RV64IF-NEXT: slli a3, a2, 63 ; RV64IF-NEXT: beq a1, a2, .LBB18_6 ; RV64IF-NEXT: # %bb.5: # %entry -; RV64IF-NEXT: slt a1, a2, a1 +; RV64IF-NEXT: slti a1, a1, 0 +; RV64IF-NEXT: xori a1, a1, 1 ; RV64IF-NEXT: beqz a1, .LBB18_7 ; RV64IF-NEXT: j .LBB18_8 ; RV64IF-NEXT: .LBB18_6: @@ -1233,7 +1239,8 @@ ; RV32IFD-NEXT: and a3, a3, a2 ; RV32IFD-NEXT: beq a3, a6, .LBB18_10 ; RV32IFD-NEXT: .LBB18_9: # %entry -; RV32IFD-NEXT: slt a4, a6, a2 +; RV32IFD-NEXT: slti a2, a2, 0 +; RV32IFD-NEXT: xori a4, a2, 1 ; RV32IFD-NEXT: .LBB18_10: # %entry ; RV32IFD-NEXT: bnez a4, .LBB18_12 ; RV32IFD-NEXT: # %bb.11: # %entry @@ -1388,33 +1395,34 @@ ; RV32IF-NEXT: .LBB20_5: # %entry ; RV32IF-NEXT: bnez a1, .LBB20_9 ; RV32IF-NEXT: # %bb.6: # %entry -; RV32IF-NEXT: li a0, 0 ; RV32IF-NEXT: li a2, 0 +; RV32IF-NEXT: li a0, 0 ; RV32IF-NEXT: li a3, 1 -; RV32IF-NEXT: bnez a2, .LBB20_10 +; RV32IF-NEXT: bnez a1, .LBB20_10 ; RV32IF-NEXT: .LBB20_7: -; RV32IF-NEXT: snez a4, a3 -; RV32IF-NEXT: bnez a1, .LBB20_11 +; RV32IF-NEXT: snez a4, a0 +; RV32IF-NEXT: bnez a2, .LBB20_11 ; RV32IF-NEXT: .LBB20_8: -; RV32IF-NEXT: snez a5, a0 +; RV32IF-NEXT: snez a5, a3 ; RV32IF-NEXT: or a2, a3, a2 ; RV32IF-NEXT: bnez a2, .LBB20_12 ; RV32IF-NEXT: j .LBB20_13 ; RV32IF-NEXT: .LBB20_9: ; RV32IF-NEXT: lw a1, 12(sp) ; RV32IF-NEXT: lw a0, 8(sp) -; RV32IF-NEXT: beqz a2, .LBB20_7 +; RV32IF-NEXT: beqz a1, .LBB20_7 ; RV32IF-NEXT: .LBB20_10: # %entry -; RV32IF-NEXT: sgtz a4, a2 -; RV32IF-NEXT: beqz a1, .LBB20_8 +; RV32IF-NEXT: snez a4, a1 +; RV32IF-NEXT: beqz a2, .LBB20_8 ; RV32IF-NEXT: .LBB20_11: # %entry -; RV32IF-NEXT: snez a5, a1 +; RV32IF-NEXT: slti a5, a2, 1 +; RV32IF-NEXT: xori a5, a5, 1 ; RV32IF-NEXT: or a2, a3, a2 ; RV32IF-NEXT: beqz a2, .LBB20_13 ; RV32IF-NEXT: .LBB20_12: # %entry -; RV32IF-NEXT: mv a5, a4 +; RV32IF-NEXT: mv a4, a5 ; RV32IF-NEXT: .LBB20_13: # %entry -; RV32IF-NEXT: bnez a5, .LBB20_15 +; RV32IF-NEXT: bnez a4, .LBB20_15 ; RV32IF-NEXT: # %bb.14: # %entry ; RV32IF-NEXT: li a0, 0 ; RV32IF-NEXT: li a1, 0 @@ -1437,7 +1445,8 @@ ; RV64-NEXT: .LBB20_2: # %entry ; RV64-NEXT: beqz a1, .LBB20_4 ; RV64-NEXT: # %bb.3: # %entry -; RV64-NEXT: sgtz a1, a1 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 ; RV64-NEXT: beqz a1, .LBB20_5 ; RV64-NEXT: j .LBB20_6 ; RV64-NEXT: .LBB20_4: @@ -1476,33 +1485,34 @@ ; RV32IFD-NEXT: .LBB20_5: # %entry ; RV32IFD-NEXT: bnez a1, .LBB20_9 ; RV32IFD-NEXT: # %bb.6: # %entry -; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: li a2, 0 +; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: li a3, 1 -; RV32IFD-NEXT: bnez a2, .LBB20_10 +; RV32IFD-NEXT: bnez a1, .LBB20_10 ; RV32IFD-NEXT: .LBB20_7: -; RV32IFD-NEXT: snez a4, a3 -; RV32IFD-NEXT: bnez a1, .LBB20_11 +; RV32IFD-NEXT: snez a4, a0 +; RV32IFD-NEXT: bnez a2, .LBB20_11 ; RV32IFD-NEXT: .LBB20_8: -; RV32IFD-NEXT: snez a5, a0 +; RV32IFD-NEXT: snez a5, a3 ; RV32IFD-NEXT: or a2, a3, a2 ; RV32IFD-NEXT: bnez a2, .LBB20_12 ; RV32IFD-NEXT: j .LBB20_13 ; RV32IFD-NEXT: .LBB20_9: ; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a0, 8(sp) -; RV32IFD-NEXT: beqz a2, .LBB20_7 +; RV32IFD-NEXT: beqz a1, .LBB20_7 ; RV32IFD-NEXT: .LBB20_10: # %entry -; RV32IFD-NEXT: sgtz a4, a2 -; RV32IFD-NEXT: beqz a1, .LBB20_8 +; RV32IFD-NEXT: snez a4, a1 +; RV32IFD-NEXT: beqz a2, .LBB20_8 ; RV32IFD-NEXT: .LBB20_11: # %entry -; RV32IFD-NEXT: snez a5, a1 +; RV32IFD-NEXT: slti a5, a2, 1 +; RV32IFD-NEXT: xori a5, a5, 1 ; RV32IFD-NEXT: or a2, a3, a2 ; RV32IFD-NEXT: beqz a2, .LBB20_13 ; RV32IFD-NEXT: .LBB20_12: # %entry -; RV32IFD-NEXT: mv a5, a4 +; RV32IFD-NEXT: mv a4, a5 ; RV32IFD-NEXT: .LBB20_13: # %entry -; RV32IFD-NEXT: bnez a5, .LBB20_15 +; RV32IFD-NEXT: bnez a4, .LBB20_15 ; RV32IFD-NEXT: # %bb.14: # %entry ; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: li a1, 0 @@ -1569,7 +1579,8 @@ ; RV32-NEXT: and a3, a3, a2 ; RV32-NEXT: beq a3, a6, .LBB21_10 ; RV32-NEXT: .LBB21_9: # %entry -; RV32-NEXT: slt a4, a6, a2 +; RV32-NEXT: slti a2, a2, 0 +; RV32-NEXT: xori a4, a2, 1 ; RV32-NEXT: .LBB21_10: # %entry ; RV32-NEXT: bnez a4, .LBB21_12 ; RV32-NEXT: # %bb.11: # %entry @@ -1684,33 +1695,34 @@ ; RV32-NEXT: .LBB23_5: # %entry ; RV32-NEXT: bnez a1, .LBB23_9 ; RV32-NEXT: # %bb.6: # %entry -; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a2, 0 +; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a3, 1 -; RV32-NEXT: bnez a2, .LBB23_10 +; RV32-NEXT: bnez a1, .LBB23_10 ; RV32-NEXT: .LBB23_7: -; RV32-NEXT: snez a4, a3 -; RV32-NEXT: bnez a1, .LBB23_11 +; RV32-NEXT: snez a4, a0 +; RV32-NEXT: bnez a2, .LBB23_11 ; RV32-NEXT: .LBB23_8: -; RV32-NEXT: snez a5, a0 +; RV32-NEXT: snez a5, a3 ; RV32-NEXT: or a2, a3, a2 ; RV32-NEXT: bnez a2, .LBB23_12 ; RV32-NEXT: j .LBB23_13 ; RV32-NEXT: .LBB23_9: ; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a0, 8(sp) -; RV32-NEXT: beqz a2, .LBB23_7 +; RV32-NEXT: beqz a1, .LBB23_7 ; RV32-NEXT: .LBB23_10: # %entry -; RV32-NEXT: sgtz a4, a2 -; RV32-NEXT: beqz a1, .LBB23_8 +; RV32-NEXT: snez a4, a1 +; RV32-NEXT: beqz a2, .LBB23_8 ; RV32-NEXT: .LBB23_11: # %entry -; RV32-NEXT: snez a5, a1 +; RV32-NEXT: slti a5, a2, 1 +; RV32-NEXT: xori a5, a5, 1 ; RV32-NEXT: or a2, a3, a2 ; RV32-NEXT: beqz a2, .LBB23_13 ; RV32-NEXT: .LBB23_12: # %entry -; RV32-NEXT: mv a5, a4 +; RV32-NEXT: mv a4, a5 ; RV32-NEXT: .LBB23_13: # %entry -; RV32-NEXT: bnez a5, .LBB23_15 +; RV32-NEXT: bnez a4, .LBB23_15 ; RV32-NEXT: # %bb.14: # %entry ; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a1, 0 @@ -1733,7 +1745,8 @@ ; RV64-NEXT: .LBB23_2: # %entry ; RV64-NEXT: beqz a1, .LBB23_4 ; RV64-NEXT: # %bb.3: # %entry -; RV64-NEXT: sgtz a1, a1 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 ; RV64-NEXT: beqz a1, .LBB23_5 ; RV64-NEXT: j .LBB23_6 ; RV64-NEXT: .LBB23_4: @@ -1806,7 +1819,8 @@ ; RV32-NEXT: and a3, a3, a2 ; RV32-NEXT: beq a3, a6, .LBB24_10 ; RV32-NEXT: .LBB24_9: # %entry -; RV32-NEXT: slt a4, a6, a2 +; RV32-NEXT: slti a2, a2, 0 +; RV32-NEXT: xori a4, a2, 1 ; RV32-NEXT: .LBB24_10: # %entry ; RV32-NEXT: bnez a4, .LBB24_12 ; RV32-NEXT: # %bb.11: # %entry @@ -1843,7 +1857,8 @@ ; RV64-NEXT: slli a3, a2, 63 ; RV64-NEXT: beq a1, a2, .LBB24_6 ; RV64-NEXT: # %bb.5: # %entry -; RV64-NEXT: slt a1, a2, a1 +; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: xori a1, a1, 1 ; RV64-NEXT: beqz a1, .LBB24_7 ; RV64-NEXT: j .LBB24_8 ; RV64-NEXT: .LBB24_6: @@ -1957,33 +1972,34 @@ ; RV32-NEXT: .LBB26_5: # %entry ; RV32-NEXT: bnez a1, .LBB26_9 ; RV32-NEXT: # %bb.6: # %entry -; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a2, 0 +; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a3, 1 -; RV32-NEXT: bnez a2, .LBB26_10 +; RV32-NEXT: bnez a1, .LBB26_10 ; RV32-NEXT: .LBB26_7: -; RV32-NEXT: snez a4, a3 -; RV32-NEXT: bnez a1, .LBB26_11 +; RV32-NEXT: snez a4, a0 +; RV32-NEXT: bnez a2, .LBB26_11 ; RV32-NEXT: .LBB26_8: -; RV32-NEXT: snez a5, a0 +; RV32-NEXT: snez a5, a3 ; RV32-NEXT: or a2, a3, a2 ; RV32-NEXT: bnez a2, .LBB26_12 ; RV32-NEXT: j .LBB26_13 ; RV32-NEXT: .LBB26_9: ; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a0, 8(sp) -; RV32-NEXT: beqz a2, .LBB26_7 +; RV32-NEXT: beqz a1, .LBB26_7 ; RV32-NEXT: .LBB26_10: # %entry -; RV32-NEXT: sgtz a4, a2 -; RV32-NEXT: beqz a1, .LBB26_8 +; RV32-NEXT: snez a4, a1 +; RV32-NEXT: beqz a2, .LBB26_8 ; RV32-NEXT: .LBB26_11: # %entry -; RV32-NEXT: snez a5, a1 +; RV32-NEXT: slti a5, a2, 1 +; RV32-NEXT: xori a5, a5, 1 ; RV32-NEXT: or a2, a3, a2 ; RV32-NEXT: beqz a2, .LBB26_13 ; RV32-NEXT: .LBB26_12: # %entry -; RV32-NEXT: mv a5, a4 +; RV32-NEXT: mv a4, a5 ; RV32-NEXT: .LBB26_13: # %entry -; RV32-NEXT: bnez a5, .LBB26_15 +; RV32-NEXT: bnez a4, .LBB26_15 ; RV32-NEXT: # %bb.14: # %entry ; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a1, 0 @@ -2008,7 +2024,8 @@ ; RV64-NEXT: .LBB26_2: # %entry ; RV64-NEXT: beqz a1, .LBB26_4 ; RV64-NEXT: # %bb.3: # %entry -; RV64-NEXT: sgtz a1, a1 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 ; RV64-NEXT: beqz a1, .LBB26_5 ; RV64-NEXT: j .LBB26_6 ; RV64-NEXT: .LBB26_4: @@ -3602,7 +3619,8 @@ ; RV32IF-NEXT: .LBB47_18: # %entry ; RV32IF-NEXT: beqz a2, .LBB47_23 ; RV32IF-NEXT: .LBB47_19: # %entry -; RV32IF-NEXT: sgtz a5, a2 +; RV32IF-NEXT: slti a5, a2, 1 +; RV32IF-NEXT: xori a5, a5, 1 ; RV32IF-NEXT: beqz a5, .LBB47_24 ; RV32IF-NEXT: j .LBB47_25 ; RV32IF-NEXT: .LBB47_20: # %entry @@ -3751,7 +3769,8 @@ ; RV32IFD-NEXT: .LBB47_18: # %entry ; RV32IFD-NEXT: beqz a2, .LBB47_23 ; RV32IFD-NEXT: .LBB47_19: # %entry -; RV32IFD-NEXT: sgtz a5, a2 +; RV32IFD-NEXT: slti a5, a2, 1 +; RV32IFD-NEXT: xori a5, a5, 1 ; RV32IFD-NEXT: beqz a5, .LBB47_24 ; RV32IFD-NEXT: j .LBB47_25 ; RV32IFD-NEXT: .LBB47_20: # %entry @@ -4077,7 +4096,8 @@ ; RV32-NEXT: .LBB50_18: # %entry ; RV32-NEXT: beqz a2, .LBB50_23 ; RV32-NEXT: .LBB50_19: # %entry -; RV32-NEXT: sgtz a5, a2 +; RV32-NEXT: slti a5, a2, 1 +; RV32-NEXT: xori a5, a5, 1 ; RV32-NEXT: beqz a5, .LBB50_24 ; RV32-NEXT: j .LBB50_25 ; RV32-NEXT: .LBB50_20: # %entry @@ -4494,7 +4514,8 @@ ; RV32-NEXT: .LBB53_18: # %entry ; RV32-NEXT: beqz a2, .LBB53_23 ; RV32-NEXT: .LBB53_19: # %entry -; RV32-NEXT: sgtz a5, a2 +; RV32-NEXT: slti a5, a2, 1 +; RV32-NEXT: xori a5, a5, 1 ; RV32-NEXT: beqz a5, .LBB53_24 ; RV32-NEXT: j .LBB53_25 ; RV32-NEXT: .LBB53_20: # %entry Index: llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll =================================================================== --- llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll +++ llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll @@ -1481,7 +1481,8 @@ ; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: beq a1, a0, .LBB18_11 ; CHECK-NEXT: .LBB18_8: # %entry -; CHECK-NEXT: slt a1, a0, a1 +; CHECK-NEXT: slti a1, a1, 0 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bne s1, a0, .LBB18_12 ; CHECK-NEXT: .LBB18_9: ; CHECK-NEXT: sltu a0, a3, s0 @@ -1496,7 +1497,8 @@ ; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: beq s1, a0, .LBB18_9 ; CHECK-NEXT: .LBB18_12: # %entry -; CHECK-NEXT: slt a0, a0, s1 +; CHECK-NEXT: slti a0, s1, 0 +; CHECK-NEXT: xori a0, a0, 1 ; CHECK-NEXT: bnez a0, .LBB18_14 ; CHECK-NEXT: .LBB18_13: # %entry ; CHECK-NEXT: mv s0, a3 @@ -1598,7 +1600,8 @@ ; CHECK-NEXT: .LBB20_4: # %entry ; CHECK-NEXT: beqz a3, .LBB20_11 ; CHECK-NEXT: .LBB20_5: # %entry -; CHECK-NEXT: sgtz a1, a3 +; CHECK-NEXT: slti a1, a3, 1 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bnez a2, .LBB20_12 ; CHECK-NEXT: .LBB20_6: ; CHECK-NEXT: snez a2, a0 @@ -1621,7 +1624,8 @@ ; CHECK-NEXT: snez a1, s0 ; CHECK-NEXT: beqz a2, .LBB20_6 ; CHECK-NEXT: .LBB20_12: # %entry -; CHECK-NEXT: sgtz a2, a2 +; CHECK-NEXT: slti a2, a2, 1 +; CHECK-NEXT: xori a2, a2, 1 ; CHECK-NEXT: bnez a2, .LBB20_14 ; CHECK-NEXT: .LBB20_13: # %entry ; CHECK-NEXT: li a0, 0 @@ -1692,7 +1696,8 @@ ; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: beq a1, a0, .LBB21_11 ; CHECK-NEXT: .LBB21_8: # %entry -; CHECK-NEXT: slt a1, a0, a1 +; CHECK-NEXT: slti a1, a1, 0 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bne s1, a0, .LBB21_12 ; CHECK-NEXT: .LBB21_9: ; CHECK-NEXT: sltu a0, a3, s0 @@ -1707,7 +1712,8 @@ ; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: beq s1, a0, .LBB21_9 ; CHECK-NEXT: .LBB21_12: # %entry -; CHECK-NEXT: slt a0, a0, s1 +; CHECK-NEXT: slti a0, s1, 0 +; CHECK-NEXT: xori a0, a0, 1 ; CHECK-NEXT: bnez a0, .LBB21_14 ; CHECK-NEXT: .LBB21_13: # %entry ; CHECK-NEXT: mv s0, a3 @@ -1809,7 +1815,8 @@ ; CHECK-NEXT: .LBB23_4: # %entry ; CHECK-NEXT: beqz a3, .LBB23_11 ; CHECK-NEXT: .LBB23_5: # %entry -; CHECK-NEXT: sgtz a1, a3 +; CHECK-NEXT: slti a1, a3, 1 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bnez a2, .LBB23_12 ; CHECK-NEXT: .LBB23_6: ; CHECK-NEXT: snez a2, a0 @@ -1832,7 +1839,8 @@ ; CHECK-NEXT: snez a1, s0 ; CHECK-NEXT: beqz a2, .LBB23_6 ; CHECK-NEXT: .LBB23_12: # %entry -; CHECK-NEXT: sgtz a2, a2 +; CHECK-NEXT: slti a2, a2, 1 +; CHECK-NEXT: xori a2, a2, 1 ; CHECK-NEXT: bnez a2, .LBB23_14 ; CHECK-NEXT: .LBB23_13: # %entry ; CHECK-NEXT: li a0, 0 @@ -1905,7 +1913,8 @@ ; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: beq a1, a0, .LBB24_11 ; CHECK-NEXT: .LBB24_8: # %entry -; CHECK-NEXT: slt a1, a0, a1 +; CHECK-NEXT: slti a1, a1, 0 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bne s1, a0, .LBB24_12 ; CHECK-NEXT: .LBB24_9: ; CHECK-NEXT: sltu a0, a3, s0 @@ -1920,7 +1929,8 @@ ; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: beq s1, a0, .LBB24_9 ; CHECK-NEXT: .LBB24_12: # %entry -; CHECK-NEXT: slt a0, a0, s1 +; CHECK-NEXT: slti a0, s1, 0 +; CHECK-NEXT: xori a0, a0, 1 ; CHECK-NEXT: bnez a0, .LBB24_14 ; CHECK-NEXT: .LBB24_13: # %entry ; CHECK-NEXT: mv s0, a3 @@ -2026,7 +2036,8 @@ ; CHECK-NEXT: .LBB26_4: # %entry ; CHECK-NEXT: beqz a3, .LBB26_11 ; CHECK-NEXT: .LBB26_5: # %entry -; CHECK-NEXT: sgtz a1, a3 +; CHECK-NEXT: slti a1, a3, 1 +; CHECK-NEXT: xori a1, a1, 1 ; CHECK-NEXT: bnez a2, .LBB26_12 ; CHECK-NEXT: .LBB26_6: ; CHECK-NEXT: snez a2, a0 @@ -2049,7 +2060,8 @@ ; CHECK-NEXT: snez a1, s0 ; CHECK-NEXT: beqz a2, .LBB26_6 ; CHECK-NEXT: .LBB26_12: # %entry -; CHECK-NEXT: sgtz a2, a2 +; CHECK-NEXT: slti a2, a2, 1 +; CHECK-NEXT: xori a2, a2, 1 ; CHECK-NEXT: bnez a2, .LBB26_14 ; CHECK-NEXT: .LBB26_13: # %entry ; CHECK-NEXT: li a0, 0 Index: llvm/test/CodeGen/RISCV/i32-icmp.ll =================================================================== --- llvm/test/CodeGen/RISCV/i32-icmp.ll +++ llvm/test/CodeGen/RISCV/i32-icmp.ll @@ -136,6 +136,39 @@ ret i32 %2 } +define i32 @icmp_ugt_constant_2047(i32 %a) nounwind { +; RV32I-LABEL: icmp_ugt_constant_2047: +; RV32I: # %bb.0: +; RV32I-NEXT: li a1, 2047 +; RV32I-NEXT: sltu a0, a1, a0 +; RV32I-NEXT: ret + %1 = icmp ugt i32 %a, 2047 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_ugt_constant_2046(i32 %a) nounwind { +; RV32I-LABEL: icmp_ugt_constant_2046: +; RV32I: # %bb.0: +; RV32I-NEXT: sltiu a0, a0, 2047 +; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: ret + %1 = icmp ugt i32 %a, 2046 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind { +; RV32I-LABEL: icmp_ugt_constant_neg_2049: +; RV32I: # %bb.0: +; RV32I-NEXT: sltiu a0, a0, -2048 +; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: ret + %1 = icmp ugt i32 %a, -2049 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_uge(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_uge: ; RV32I: # %bb.0: @@ -157,6 +190,36 @@ ret i32 %2 } +define i32 @icmp_ult_constant_2047(i32 %a) nounwind { +; RV32I-LABEL: icmp_ult_constant_2047: +; RV32I: # %bb.0: +; RV32I-NEXT: sltiu a0, a0, 2047 +; RV32I-NEXT: ret + %1 = icmp ult i32 %a, 2047 + %2 = zext i1 %1 to i32 + ret i32 %2 +} +define i32 @icmp_ult_constant_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_ult_constant_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a0, a0, 11 +; RV32I-NEXT: seqz a0, a0 +; RV32I-NEXT: ret + %1 = icmp ult i32 %a, 2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_ult_constant_neg_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: sltiu a0, a0, -2048 +; RV32I-NEXT: ret + %1 = icmp ult i32 %a, -2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_ule(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_ule: ; RV32I: # %bb.0: @@ -178,6 +241,62 @@ ret i32 %2 } +define i32 @icmp_sgt_constant(i32 %a) nounwind { +; RV32I-LABEL: icmp_sgt_constant: +; RV32I: # %bb.0: +; RV32I-NEXT: slti a0, a0, 6 +; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: ret + %1 = icmp sgt i32 %a, 5 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_sgt_constant_2046(i32 %a) nounwind { +; RV32I-LABEL: icmp_sgt_constant_2046: +; RV32I: # %bb.0: +; RV32I-NEXT: slti a0, a0, 2047 +; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: ret + %1 = icmp sgt i32 %a, 2046 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_sgt_constant_2047(i32 %a) nounwind { +; RV32I-LABEL: icmp_sgt_constant_2047: +; RV32I: # %bb.0: +; RV32I-NEXT: li a1, 2047 +; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: ret + %1 = icmp sgt i32 %a, 2047 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_sgt_constant_neg_2049(i32 %a) nounwind { +; RV32I-LABEL: icmp_sgt_constant_neg_2049: +; RV32I: # %bb.0: +; RV32I-NEXT: slti a0, a0, -2048 +; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: ret + %1 = icmp sgt i32 %a, -2049 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_sgt_constant_neg_2050(i32 %a) nounwind { +; RV32I-LABEL: icmp_sgt_constant_neg_2050: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 1048575 +; RV32I-NEXT: addi a1, a1, 2046 +; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: ret + %1 = icmp sgt i32 %a, -2050 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_sge(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_sge: ; RV32I: # %bb.0: @@ -209,5 +328,3 @@ %2 = zext i1 %1 to i32 ret i32 %2 } - -; TODO: check variants with an immediate? Index: llvm/test/CodeGen/RISCV/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-constant-xor.ll +++ llvm/test/CodeGen/RISCV/select-constant-xor.ll @@ -48,8 +48,8 @@ define i32 @selecti64i32(i64 %a) { ; RV32-LABEL: selecti64i32: ; RV32: # %bb.0: -; RV32-NEXT: li a0, -1 -; RV32-NEXT: slt a0, a0, a1 +; RV32-NEXT: slti a0, a1, 0 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: sub a0, a1, a0 ; RV32-NEXT: ret Index: llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll =================================================================== --- llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll +++ llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll @@ -106,8 +106,8 @@ ; ; RV64-LABEL: pos_sel_special_constant: ; RV64: # %bb.0: -; RV64-NEXT: li a1, -1 -; RV64-NEXT: slt a0, a1, a0 +; RV64-NEXT: slti a0, a0, 0 +; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: slli a0, a0, 9 ; RV64-NEXT: ret %tmp.1 = icmp sgt i32 %a, -1 Index: llvm/test/CodeGen/RISCV/ssub_sat.ll =================================================================== --- llvm/test/CodeGen/RISCV/ssub_sat.ll +++ llvm/test/CodeGen/RISCV/ssub_sat.ll @@ -16,10 +16,11 @@ ; RV32I-LABEL: func: ; RV32I: # %bb.0: ; RV32I-NEXT: mv a2, a0 -; RV32I-NEXT: sgtz a3, a1 ; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: slt a1, a0, a2 -; RV32I-NEXT: beq a3, a1, .LBB0_2 +; RV32I-NEXT: slt a2, a0, a2 +; RV32I-NEXT: slti a1, a1, 1 +; RV32I-NEXT: xori a1, a1, 1 +; RV32I-NEXT: beq a1, a2, .LBB0_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srai a0, a0, 31 ; RV32I-NEXT: lui a1, 524288 @@ -47,10 +48,11 @@ ; RV32IZbbNOZbt-LABEL: func: ; RV32IZbbNOZbt: # %bb.0: ; RV32IZbbNOZbt-NEXT: mv a2, a0 -; RV32IZbbNOZbt-NEXT: sgtz a3, a1 ; RV32IZbbNOZbt-NEXT: sub a0, a0, a1 -; RV32IZbbNOZbt-NEXT: slt a1, a0, a2 -; RV32IZbbNOZbt-NEXT: beq a3, a1, .LBB0_2 +; RV32IZbbNOZbt-NEXT: slt a2, a0, a2 +; RV32IZbbNOZbt-NEXT: slti a1, a1, 1 +; RV32IZbbNOZbt-NEXT: xori a1, a1, 1 +; RV32IZbbNOZbt-NEXT: beq a1, a2, .LBB0_2 ; RV32IZbbNOZbt-NEXT: # %bb.1: ; RV32IZbbNOZbt-NEXT: srai a0, a0, 31 ; RV32IZbbNOZbt-NEXT: lui a1, 524288 @@ -69,14 +71,15 @@ ; ; RV32IZbbZbt-LABEL: func: ; RV32IZbbZbt: # %bb.0: -; RV32IZbbZbt-NEXT: sgtz a2, a1 -; RV32IZbbZbt-NEXT: sub a1, a0, a1 -; RV32IZbbZbt-NEXT: slt a0, a1, a0 -; RV32IZbbZbt-NEXT: xor a0, a2, a0 -; RV32IZbbZbt-NEXT: srai a2, a1, 31 +; RV32IZbbZbt-NEXT: sub a2, a0, a1 +; RV32IZbbZbt-NEXT: slt a0, a2, a0 +; RV32IZbbZbt-NEXT: slti a1, a1, 1 +; RV32IZbbZbt-NEXT: xori a1, a1, 1 +; RV32IZbbZbt-NEXT: xor a0, a1, a0 +; RV32IZbbZbt-NEXT: srai a1, a2, 31 ; RV32IZbbZbt-NEXT: lui a3, 524288 -; RV32IZbbZbt-NEXT: xor a2, a2, a3 -; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1 +; RV32IZbbZbt-NEXT: xor a1, a1, a3 +; RV32IZbbZbt-NEXT: cmov a0, a0, a1, a2 ; RV32IZbbZbt-NEXT: ret %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y); ret i32 %tmp; @@ -105,10 +108,11 @@ ; RV64I-LABEL: func2: ; RV64I: # %bb.0: ; RV64I-NEXT: mv a2, a0 -; RV64I-NEXT: sgtz a3, a1 ; RV64I-NEXT: sub a0, a0, a1 -; RV64I-NEXT: slt a1, a0, a2 -; RV64I-NEXT: beq a3, a1, .LBB1_2 +; RV64I-NEXT: slt a2, a0, a2 +; RV64I-NEXT: slti a1, a1, 1 +; RV64I-NEXT: xori a1, a1, 1 +; RV64I-NEXT: beq a1, a2, .LBB1_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: srai a0, a0, 63 ; RV64I-NEXT: li a1, -1 @@ -139,10 +143,11 @@ ; RV64IZbbNOZbt-LABEL: func2: ; RV64IZbbNOZbt: # %bb.0: ; RV64IZbbNOZbt-NEXT: mv a2, a0 -; RV64IZbbNOZbt-NEXT: sgtz a3, a1 ; RV64IZbbNOZbt-NEXT: sub a0, a0, a1 -; RV64IZbbNOZbt-NEXT: slt a1, a0, a2 -; RV64IZbbNOZbt-NEXT: beq a3, a1, .LBB1_2 +; RV64IZbbNOZbt-NEXT: slt a2, a0, a2 +; RV64IZbbNOZbt-NEXT: slti a1, a1, 1 +; RV64IZbbNOZbt-NEXT: xori a1, a1, 1 +; RV64IZbbNOZbt-NEXT: beq a1, a2, .LBB1_2 ; RV64IZbbNOZbt-NEXT: # %bb.1: ; RV64IZbbNOZbt-NEXT: srai a0, a0, 63 ; RV64IZbbNOZbt-NEXT: li a1, -1 @@ -170,15 +175,16 @@ ; ; RV64IZbbZbt-LABEL: func2: ; RV64IZbbZbt: # %bb.0: -; RV64IZbbZbt-NEXT: sgtz a2, a1 -; RV64IZbbZbt-NEXT: sub a1, a0, a1 -; RV64IZbbZbt-NEXT: slt a0, a1, a0 -; RV64IZbbZbt-NEXT: xor a0, a2, a0 -; RV64IZbbZbt-NEXT: srai a2, a1, 63 +; RV64IZbbZbt-NEXT: sub a2, a0, a1 +; RV64IZbbZbt-NEXT: slt a0, a2, a0 +; RV64IZbbZbt-NEXT: slti a1, a1, 1 +; RV64IZbbZbt-NEXT: xori a1, a1, 1 +; RV64IZbbZbt-NEXT: xor a0, a1, a0 +; RV64IZbbZbt-NEXT: srai a1, a2, 63 ; RV64IZbbZbt-NEXT: li a3, -1 ; RV64IZbbZbt-NEXT: slli a3, a3, 63 -; RV64IZbbZbt-NEXT: xor a2, a2, a3 -; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1 +; RV64IZbbZbt-NEXT: xor a1, a1, a3 +; RV64IZbbZbt-NEXT: cmov a0, a0, a1, a2 ; RV64IZbbZbt-NEXT: ret %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y); ret i64 %tmp; Index: llvm/test/CodeGen/RISCV/ssub_sat_plus.ll =================================================================== --- llvm/test/CodeGen/RISCV/ssub_sat_plus.ll +++ llvm/test/CodeGen/RISCV/ssub_sat_plus.ll @@ -16,10 +16,11 @@ ; RV32I-LABEL: func32: ; RV32I: # %bb.0: ; RV32I-NEXT: mv a3, a0 -; RV32I-NEXT: mul a0, a1, a2 -; RV32I-NEXT: sgtz a1, a0 -; RV32I-NEXT: sub a0, a3, a0 +; RV32I-NEXT: mul a1, a1, a2 +; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: slt a2, a0, a3 +; RV32I-NEXT: slti a1, a1, 1 +; RV32I-NEXT: xori a1, a1, 1 ; RV32I-NEXT: beq a1, a2, .LBB0_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srai a0, a0, 31 @@ -50,10 +51,11 @@ ; RV32IZbbNOZbt-LABEL: func32: ; RV32IZbbNOZbt: # %bb.0: ; RV32IZbbNOZbt-NEXT: mv a3, a0 -; RV32IZbbNOZbt-NEXT: mul a0, a1, a2 -; RV32IZbbNOZbt-NEXT: sgtz a1, a0 -; RV32IZbbNOZbt-NEXT: sub a0, a3, a0 +; RV32IZbbNOZbt-NEXT: mul a1, a1, a2 +; RV32IZbbNOZbt-NEXT: sub a0, a0, a1 ; RV32IZbbNOZbt-NEXT: slt a2, a0, a3 +; RV32IZbbNOZbt-NEXT: slti a1, a1, 1 +; RV32IZbbNOZbt-NEXT: xori a1, a1, 1 ; RV32IZbbNOZbt-NEXT: beq a1, a2, .LBB0_2 ; RV32IZbbNOZbt-NEXT: # %bb.1: ; RV32IZbbNOZbt-NEXT: srai a0, a0, 31 @@ -76,14 +78,15 @@ ; RV32IZbbZbt-LABEL: func32: ; RV32IZbbZbt: # %bb.0: ; RV32IZbbZbt-NEXT: mul a1, a1, a2 -; RV32IZbbZbt-NEXT: sgtz a2, a1 -; RV32IZbbZbt-NEXT: sub a1, a0, a1 -; RV32IZbbZbt-NEXT: slt a0, a1, a0 -; RV32IZbbZbt-NEXT: xor a0, a2, a0 -; RV32IZbbZbt-NEXT: srai a2, a1, 31 +; RV32IZbbZbt-NEXT: sub a2, a0, a1 +; RV32IZbbZbt-NEXT: slt a0, a2, a0 +; RV32IZbbZbt-NEXT: slti a1, a1, 1 +; RV32IZbbZbt-NEXT: xori a1, a1, 1 +; RV32IZbbZbt-NEXT: xor a0, a1, a0 +; RV32IZbbZbt-NEXT: srai a1, a2, 31 ; RV32IZbbZbt-NEXT: lui a3, 524288 -; RV32IZbbZbt-NEXT: xor a2, a2, a3 -; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1 +; RV32IZbbZbt-NEXT: xor a1, a1, a3 +; RV32IZbbZbt-NEXT: cmov a0, a0, a1, a2 ; RV32IZbbZbt-NEXT: ret %a = mul i32 %y, %z %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a) @@ -113,10 +116,11 @@ ; RV64I-LABEL: func64: ; RV64I: # %bb.0: ; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: sgtz a3, a2 ; RV64I-NEXT: sub a0, a0, a2 ; RV64I-NEXT: slt a1, a0, a1 -; RV64I-NEXT: beq a3, a1, .LBB1_2 +; RV64I-NEXT: slti a2, a2, 1 +; RV64I-NEXT: xori a2, a2, 1 +; RV64I-NEXT: beq a2, a1, .LBB1_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: srai a0, a0, 63 ; RV64I-NEXT: li a1, -1 @@ -147,10 +151,11 @@ ; RV64IZbbNOZbt-LABEL: func64: ; RV64IZbbNOZbt: # %bb.0: ; RV64IZbbNOZbt-NEXT: mv a1, a0 -; RV64IZbbNOZbt-NEXT: sgtz a3, a2 ; RV64IZbbNOZbt-NEXT: sub a0, a0, a2 ; RV64IZbbNOZbt-NEXT: slt a1, a0, a1 -; RV64IZbbNOZbt-NEXT: beq a3, a1, .LBB1_2 +; RV64IZbbNOZbt-NEXT: slti a2, a2, 1 +; RV64IZbbNOZbt-NEXT: xori a2, a2, 1 +; RV64IZbbNOZbt-NEXT: beq a2, a1, .LBB1_2 ; RV64IZbbNOZbt-NEXT: # %bb.1: ; RV64IZbbNOZbt-NEXT: srai a0, a0, 63 ; RV64IZbbNOZbt-NEXT: li a1, -1 @@ -178,15 +183,16 @@ ; ; RV64IZbbZbt-LABEL: func64: ; RV64IZbbZbt: # %bb.0: -; RV64IZbbZbt-NEXT: sgtz a1, a2 -; RV64IZbbZbt-NEXT: sub a2, a0, a2 -; RV64IZbbZbt-NEXT: slt a0, a2, a0 -; RV64IZbbZbt-NEXT: xor a0, a1, a0 -; RV64IZbbZbt-NEXT: srai a1, a2, 63 +; RV64IZbbZbt-NEXT: sub a1, a0, a2 +; RV64IZbbZbt-NEXT: slt a0, a1, a0 +; RV64IZbbZbt-NEXT: slti a2, a2, 1 +; RV64IZbbZbt-NEXT: xori a2, a2, 1 +; RV64IZbbZbt-NEXT: xor a0, a2, a0 +; RV64IZbbZbt-NEXT: srai a2, a1, 63 ; RV64IZbbZbt-NEXT: li a3, -1 ; RV64IZbbZbt-NEXT: slli a3, a3, 63 -; RV64IZbbZbt-NEXT: xor a1, a1, a3 -; RV64IZbbZbt-NEXT: cmov a0, a0, a1, a2 +; RV64IZbbZbt-NEXT: xor a2, a2, a3 +; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1 ; RV64IZbbZbt-NEXT: ret %a = mul i64 %y, %z %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z) Index: llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll =================================================================== --- llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -195,8 +195,8 @@ ; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: neg a0, a0 ; RV32-NEXT: andi a0, a0, 15 -; RV32-NEXT: li a1, 3 -; RV32-NEXT: sltu a0, a1, a0 +; RV32-NEXT: sltiu a0, a0, 4 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret ; ; RV64-LABEL: test_urem_odd_setne: @@ -205,8 +205,8 @@ ; RV64-NEXT: addw a0, a1, a0 ; RV64-NEXT: negw a0, a0 ; RV64-NEXT: andi a0, a0, 15 -; RV64-NEXT: li a1, 3 -; RV64-NEXT: sltu a0, a1, a0 +; RV64-NEXT: sltiu a0, a0, 4 +; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: ret ; ; RV32M-LABEL: test_urem_odd_setne: @@ -215,8 +215,8 @@ ; RV32M-NEXT: add a0, a1, a0 ; RV32M-NEXT: neg a0, a0 ; RV32M-NEXT: andi a0, a0, 15 -; RV32M-NEXT: li a1, 3 -; RV32M-NEXT: sltu a0, a1, a0 +; RV32M-NEXT: sltiu a0, a0, 4 +; RV32M-NEXT: xori a0, a0, 1 ; RV32M-NEXT: ret ; ; RV64M-LABEL: test_urem_odd_setne: @@ -225,8 +225,8 @@ ; RV64M-NEXT: addw a0, a1, a0 ; RV64M-NEXT: negw a0, a0 ; RV64M-NEXT: andi a0, a0, 15 -; RV64M-NEXT: li a1, 3 -; RV64M-NEXT: sltu a0, a1, a0 +; RV64M-NEXT: sltiu a0, a0, 4 +; RV64M-NEXT: xori a0, a0, 1 ; RV64M-NEXT: ret ; ; RV32MV-LABEL: test_urem_odd_setne: @@ -235,8 +235,8 @@ ; RV32MV-NEXT: add a0, a1, a0 ; RV32MV-NEXT: neg a0, a0 ; RV32MV-NEXT: andi a0, a0, 15 -; RV32MV-NEXT: li a1, 3 -; RV32MV-NEXT: sltu a0, a1, a0 +; RV32MV-NEXT: sltiu a0, a0, 4 +; RV32MV-NEXT: xori a0, a0, 1 ; RV32MV-NEXT: ret ; ; RV64MV-LABEL: test_urem_odd_setne: @@ -245,8 +245,8 @@ ; RV64MV-NEXT: addw a0, a1, a0 ; RV64MV-NEXT: negw a0, a0 ; RV64MV-NEXT: andi a0, a0, 15 -; RV64MV-NEXT: li a1, 3 -; RV64MV-NEXT: sltu a0, a1, a0 +; RV64MV-NEXT: sltiu a0, a0, 4 +; RV64MV-NEXT: xori a0, a0, 1 ; RV64MV-NEXT: ret %urem = urem i4 %X, 5 %cmp = icmp ne i4 %urem, 0 @@ -261,8 +261,8 @@ ; RV32-NEXT: li a1, 307 ; RV32-NEXT: call __mulsi3@plt ; RV32-NEXT: andi a0, a0, 511 -; RV32-NEXT: li a1, 1 -; RV32-NEXT: sltu a0, a1, a0 +; RV32-NEXT: sltiu a0, a0, 2 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret @@ -274,8 +274,8 @@ ; RV64-NEXT: li a1, 307 ; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: andi a0, a0, 511 -; RV64-NEXT: li a1, 1 -; RV64-NEXT: sltu a0, a1, a0 +; RV64-NEXT: sltiu a0, a0, 2 +; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret @@ -285,8 +285,8 @@ ; RV32M-NEXT: li a1, 307 ; RV32M-NEXT: mul a0, a0, a1 ; RV32M-NEXT: andi a0, a0, 511 -; RV32M-NEXT: li a1, 1 -; RV32M-NEXT: sltu a0, a1, a0 +; RV32M-NEXT: sltiu a0, a0, 2 +; RV32M-NEXT: xori a0, a0, 1 ; RV32M-NEXT: ret ; ; RV64M-LABEL: test_urem_negative_odd: @@ -294,8 +294,8 @@ ; RV64M-NEXT: li a1, 307 ; RV64M-NEXT: mulw a0, a0, a1 ; RV64M-NEXT: andi a0, a0, 511 -; RV64M-NEXT: li a1, 1 -; RV64M-NEXT: sltu a0, a1, a0 +; RV64M-NEXT: sltiu a0, a0, 2 +; RV64M-NEXT: xori a0, a0, 1 ; RV64M-NEXT: ret ; ; RV32MV-LABEL: test_urem_negative_odd: @@ -303,8 +303,8 @@ ; RV32MV-NEXT: li a1, 307 ; RV32MV-NEXT: mul a0, a0, a1 ; RV32MV-NEXT: andi a0, a0, 511 -; RV32MV-NEXT: li a1, 1 -; RV32MV-NEXT: sltu a0, a1, a0 +; RV32MV-NEXT: sltiu a0, a0, 2 +; RV32MV-NEXT: xori a0, a0, 1 ; RV32MV-NEXT: ret ; ; RV64MV-LABEL: test_urem_negative_odd: @@ -312,8 +312,8 @@ ; RV64MV-NEXT: li a1, 307 ; RV64MV-NEXT: mulw a0, a0, a1 ; RV64MV-NEXT: andi a0, a0, 511 -; RV64MV-NEXT: li a1, 1 -; RV64MV-NEXT: sltu a0, a1, a0 +; RV64MV-NEXT: sltiu a0, a0, 2 +; RV64MV-NEXT: xori a0, a0, 1 ; RV64MV-NEXT: ret %urem = urem i9 %X, -5 %cmp = icmp ne i9 %urem, 0 @@ -344,22 +344,22 @@ ; RV32-NEXT: srli a0, a0, 22 ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: andi a0, a0, 2047 -; RV32-NEXT: li a1, 341 -; RV32-NEXT: sltu s3, a1, a0 +; RV32-NEXT: sltiu a0, a0, 342 +; RV32-NEXT: xori s3, a0, 1 ; RV32-NEXT: li a1, 819 ; RV32-NEXT: mv a0, s1 ; RV32-NEXT: call __mulsi3@plt ; RV32-NEXT: addi a0, a0, -1638 ; RV32-NEXT: andi a0, a0, 2047 -; RV32-NEXT: li a1, 1 -; RV32-NEXT: sltu s1, a1, a0 +; RV32-NEXT: sltiu a0, a0, 2 +; RV32-NEXT: xori s1, a0, 1 ; RV32-NEXT: li a1, 1463 ; RV32-NEXT: mv a0, s2 ; RV32-NEXT: call __mulsi3@plt ; RV32-NEXT: addi a0, a0, -1463 ; RV32-NEXT: andi a0, a0, 2047 -; RV32-NEXT: li a1, 292 -; RV32-NEXT: sltu a0, a1, a0 +; RV32-NEXT: sltiu a0, a0, 293 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: neg a1, s3 ; RV32-NEXT: neg a0, a0 ; RV32-NEXT: neg a2, s1 @@ -404,22 +404,22 @@ ; RV64-NEXT: srli a0, a0, 54 ; RV64-NEXT: or a0, a0, a1 ; RV64-NEXT: andi a0, a0, 2047 -; RV64-NEXT: li a1, 341 -; RV64-NEXT: sltu s3, a1, a0 +; RV64-NEXT: sltiu a0, a0, 342 +; RV64-NEXT: xori s3, a0, 1 ; RV64-NEXT: li a1, 819 ; RV64-NEXT: mv a0, s2 ; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: addiw a0, a0, -1638 ; RV64-NEXT: andi a0, a0, 2047 -; RV64-NEXT: li a1, 1 -; RV64-NEXT: sltu s2, a1, a0 +; RV64-NEXT: sltiu a0, a0, 2 +; RV64-NEXT: xori s2, a0, 1 ; RV64-NEXT: li a1, 1463 ; RV64-NEXT: mv a0, s1 ; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: addiw a0, a0, -1463 ; RV64-NEXT: andi a0, a0, 2047 -; RV64-NEXT: li a1, 292 -; RV64-NEXT: sltu a0, a1, a0 +; RV64-NEXT: sltiu a0, a0, 293 +; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: negw a1, s3 ; RV64-NEXT: negw a0, a0 ; RV64-NEXT: andi a1, a1, 2047 @@ -456,20 +456,20 @@ ; RV32M-NEXT: srli a2, a2, 22 ; RV32M-NEXT: or a2, a2, a4 ; RV32M-NEXT: andi a2, a2, 2047 -; RV32M-NEXT: li a4, 341 -; RV32M-NEXT: sltu a2, a4, a2 +; RV32M-NEXT: sltiu a2, a2, 342 +; RV32M-NEXT: xori a2, a2, 1 ; RV32M-NEXT: li a4, 819 ; RV32M-NEXT: mul a1, a1, a4 ; RV32M-NEXT: addi a1, a1, -1638 ; RV32M-NEXT: andi a1, a1, 2047 -; RV32M-NEXT: li a4, 1 -; RV32M-NEXT: sltu a1, a4, a1 +; RV32M-NEXT: sltiu a1, a1, 2 +; RV32M-NEXT: xori a1, a1, 1 ; RV32M-NEXT: li a4, 1463 ; RV32M-NEXT: mul a3, a3, a4 ; RV32M-NEXT: addi a3, a3, -1463 ; RV32M-NEXT: andi a3, a3, 2047 -; RV32M-NEXT: li a4, 292 -; RV32M-NEXT: sltu a3, a4, a3 +; RV32M-NEXT: sltiu a3, a3, 293 +; RV32M-NEXT: xori a3, a3, 1 ; RV32M-NEXT: neg a2, a2 ; RV32M-NEXT: neg a3, a3 ; RV32M-NEXT: neg a4, a1 @@ -501,20 +501,20 @@ ; RV64M-NEXT: srli a1, a1, 54 ; RV64M-NEXT: or a1, a1, a4 ; RV64M-NEXT: andi a1, a1, 2047 -; RV64M-NEXT: li a4, 341 -; RV64M-NEXT: sltu a1, a4, a1 +; RV64M-NEXT: sltiu a1, a1, 342 +; RV64M-NEXT: xori a1, a1, 1 ; RV64M-NEXT: li a4, 819 ; RV64M-NEXT: mulw a3, a3, a4 ; RV64M-NEXT: addiw a3, a3, -1638 ; RV64M-NEXT: andi a3, a3, 2047 -; RV64M-NEXT: li a4, 1 -; RV64M-NEXT: sltu a3, a4, a3 +; RV64M-NEXT: sltiu a3, a3, 2 +; RV64M-NEXT: xori a3, a3, 1 ; RV64M-NEXT: li a4, 1463 ; RV64M-NEXT: mulw a2, a2, a4 ; RV64M-NEXT: addiw a2, a2, -1463 ; RV64M-NEXT: andi a2, a2, 2047 -; RV64M-NEXT: li a4, 292 -; RV64M-NEXT: sltu a2, a4, a2 +; RV64M-NEXT: sltiu a2, a2, 293 +; RV64M-NEXT: xori a2, a2, 1 ; RV64M-NEXT: negw a1, a1 ; RV64M-NEXT: negw a2, a2 ; RV64M-NEXT: andi a1, a1, 2047 Index: llvm/test/CodeGen/RISCV/xaluo.ll =================================================================== --- llvm/test/CodeGen/RISCV/xaluo.ll +++ llvm/test/CodeGen/RISCV/xaluo.ll @@ -477,11 +477,12 @@ define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) { ; RV32-LABEL: ssubo1.i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: sgtz a3, a1 -; RV32-NEXT: sub a1, a0, a1 -; RV32-NEXT: slt a0, a1, a0 -; RV32-NEXT: xor a0, a3, a0 -; RV32-NEXT: sw a1, 0(a2) +; RV32-NEXT: sub a3, a0, a1 +; RV32-NEXT: slt a0, a3, a0 +; RV32-NEXT: slti a1, a1, 1 +; RV32-NEXT: xori a1, a1, 1 +; RV32-NEXT: xor a0, a1, a0 +; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: ret ; ; RV64-LABEL: ssubo1.i32: @@ -497,11 +498,12 @@ ; ; RV32ZBA-LABEL: ssubo1.i32: ; RV32ZBA: # %bb.0: # %entry -; RV32ZBA-NEXT: sgtz a3, a1 -; RV32ZBA-NEXT: sub a1, a0, a1 -; RV32ZBA-NEXT: slt a0, a1, a0 -; RV32ZBA-NEXT: xor a0, a3, a0 -; RV32ZBA-NEXT: sw a1, 0(a2) +; RV32ZBA-NEXT: sub a3, a0, a1 +; RV32ZBA-NEXT: slt a0, a3, a0 +; RV32ZBA-NEXT: slti a1, a1, 1 +; RV32ZBA-NEXT: xori a1, a1, 1 +; RV32ZBA-NEXT: xor a0, a1, a0 +; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: ret ; ; RV64ZBA-LABEL: ssubo1.i32: @@ -582,11 +584,12 @@ ; ; RV64-LABEL: ssubo.i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: sgtz a3, a1 -; RV64-NEXT: sub a1, a0, a1 -; RV64-NEXT: slt a0, a1, a0 -; RV64-NEXT: xor a0, a3, a0 -; RV64-NEXT: sd a1, 0(a2) +; RV64-NEXT: sub a3, a0, a1 +; RV64-NEXT: slt a0, a3, a0 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 +; RV64-NEXT: xor a0, a1, a0 +; RV64-NEXT: sd a3, 0(a2) ; RV64-NEXT: ret ; ; RV32ZBA-LABEL: ssubo.i64: @@ -606,11 +609,12 @@ ; ; RV64ZBA-LABEL: ssubo.i64: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: sgtz a3, a1 -; RV64ZBA-NEXT: sub a1, a0, a1 -; RV64ZBA-NEXT: slt a0, a1, a0 -; RV64ZBA-NEXT: xor a0, a3, a0 -; RV64ZBA-NEXT: sd a1, 0(a2) +; RV64ZBA-NEXT: sub a3, a0, a1 +; RV64ZBA-NEXT: slt a0, a3, a0 +; RV64ZBA-NEXT: slti a1, a1, 1 +; RV64ZBA-NEXT: xori a1, a1, 1 +; RV64ZBA-NEXT: xor a0, a1, a0 +; RV64ZBA-NEXT: sd a3, 0(a2) ; RV64ZBA-NEXT: ret entry: %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) @@ -1584,8 +1588,8 @@ ; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: not a1, a1 ; RV32-NEXT: and a0, a1, a0 -; RV32-NEXT: li a1, -1 -; RV32-NEXT: slt a0, a1, a0 +; RV32-NEXT: slti a0, a0, 0 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret ; ; RV64-LABEL: saddo.not.i64: @@ -1607,8 +1611,8 @@ ; RV32ZBA-NEXT: xor a1, a1, a3 ; RV32ZBA-NEXT: not a1, a1 ; RV32ZBA-NEXT: and a0, a1, a0 -; RV32ZBA-NEXT: li a1, -1 -; RV32ZBA-NEXT: slt a0, a1, a0 +; RV32ZBA-NEXT: slti a0, a0, 0 +; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: ret ; ; RV64ZBA-LABEL: saddo.not.i64: @@ -1821,10 +1825,11 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) { ; RV32-LABEL: ssubo.select.i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: sgtz a2, a1 -; RV32-NEXT: sub a3, a0, a1 -; RV32-NEXT: slt a3, a3, a0 -; RV32-NEXT: bne a2, a3, .LBB34_2 +; RV32-NEXT: sub a2, a0, a1 +; RV32-NEXT: slt a2, a2, a0 +; RV32-NEXT: slti a3, a1, 1 +; RV32-NEXT: xori a3, a3, 1 +; RV32-NEXT: bne a3, a2, .LBB34_2 ; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: mv a0, a1 ; RV32-NEXT: .LBB34_2: # %entry @@ -1844,10 +1849,11 @@ ; ; RV32ZBA-LABEL: ssubo.select.i32: ; RV32ZBA: # %bb.0: # %entry -; RV32ZBA-NEXT: sgtz a2, a1 -; RV32ZBA-NEXT: sub a3, a0, a1 -; RV32ZBA-NEXT: slt a3, a3, a0 -; RV32ZBA-NEXT: bne a2, a3, .LBB34_2 +; RV32ZBA-NEXT: sub a2, a0, a1 +; RV32ZBA-NEXT: slt a2, a2, a0 +; RV32ZBA-NEXT: slti a3, a1, 1 +; RV32ZBA-NEXT: xori a3, a3, 1 +; RV32ZBA-NEXT: bne a3, a2, .LBB34_2 ; RV32ZBA-NEXT: # %bb.1: # %entry ; RV32ZBA-NEXT: mv a0, a1 ; RV32ZBA-NEXT: .LBB34_2: # %entry @@ -1874,10 +1880,11 @@ define i1 @ssubo.not.i32(i32 %v1, i32 %v2) { ; RV32-LABEL: ssubo.not.i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: sgtz a2, a1 -; RV32-NEXT: sub a1, a0, a1 -; RV32-NEXT: slt a0, a1, a0 -; RV32-NEXT: xor a0, a2, a0 +; RV32-NEXT: sub a2, a0, a1 +; RV32-NEXT: slt a0, a2, a0 +; RV32-NEXT: slti a1, a1, 1 +; RV32-NEXT: xori a1, a1, 1 +; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret ; @@ -1893,10 +1900,11 @@ ; ; RV32ZBA-LABEL: ssubo.not.i32: ; RV32ZBA: # %bb.0: # %entry -; RV32ZBA-NEXT: sgtz a2, a1 -; RV32ZBA-NEXT: sub a1, a0, a1 -; RV32ZBA-NEXT: slt a0, a1, a0 -; RV32ZBA-NEXT: xor a0, a2, a0 +; RV32ZBA-NEXT: sub a2, a0, a1 +; RV32ZBA-NEXT: slt a0, a2, a0 +; RV32ZBA-NEXT: slti a1, a1, 1 +; RV32ZBA-NEXT: xori a1, a1, 1 +; RV32ZBA-NEXT: xor a0, a1, a0 ; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: ret ; @@ -1934,10 +1942,11 @@ ; ; RV64-LABEL: ssubo.select.i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: sgtz a2, a1 -; RV64-NEXT: sub a3, a0, a1 -; RV64-NEXT: slt a3, a3, a0 -; RV64-NEXT: bne a2, a3, .LBB36_2 +; RV64-NEXT: sub a2, a0, a1 +; RV64-NEXT: slt a2, a2, a0 +; RV64-NEXT: slti a3, a1, 1 +; RV64-NEXT: xori a3, a3, 1 +; RV64-NEXT: bne a3, a2, .LBB36_2 ; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: mv a0, a1 ; RV64-NEXT: .LBB36_2: # %entry @@ -1960,10 +1969,11 @@ ; ; RV64ZBA-LABEL: ssubo.select.i64: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: sgtz a2, a1 -; RV64ZBA-NEXT: sub a3, a0, a1 -; RV64ZBA-NEXT: slt a3, a3, a0 -; RV64ZBA-NEXT: bne a2, a3, .LBB36_2 +; RV64ZBA-NEXT: sub a2, a0, a1 +; RV64ZBA-NEXT: slt a2, a2, a0 +; RV64ZBA-NEXT: slti a3, a1, 1 +; RV64ZBA-NEXT: xori a3, a3, 1 +; RV64ZBA-NEXT: bne a3, a2, .LBB36_2 ; RV64ZBA-NEXT: # %bb.1: # %entry ; RV64ZBA-NEXT: mv a0, a1 ; RV64ZBA-NEXT: .LBB36_2: # %entry @@ -1984,16 +1994,17 @@ ; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: and a0, a1, a0 -; RV32-NEXT: li a1, -1 -; RV32-NEXT: slt a0, a1, a0 +; RV32-NEXT: slti a0, a0, 0 +; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret ; ; RV64-LABEL: ssub.not.i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: sgtz a2, a1 -; RV64-NEXT: sub a1, a0, a1 -; RV64-NEXT: slt a0, a1, a0 -; RV64-NEXT: xor a0, a2, a0 +; RV64-NEXT: sub a2, a0, a1 +; RV64-NEXT: slt a0, a2, a0 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 +; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: ret ; @@ -2005,16 +2016,17 @@ ; RV32ZBA-NEXT: xor a0, a1, a0 ; RV32ZBA-NEXT: xor a1, a1, a3 ; RV32ZBA-NEXT: and a0, a1, a0 -; RV32ZBA-NEXT: li a1, -1 -; RV32ZBA-NEXT: slt a0, a1, a0 +; RV32ZBA-NEXT: slti a0, a0, 0 +; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: ret ; ; RV64ZBA-LABEL: ssub.not.i64: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: sgtz a2, a1 -; RV64ZBA-NEXT: sub a1, a0, a1 -; RV64ZBA-NEXT: slt a0, a1, a0 -; RV64ZBA-NEXT: xor a0, a2, a0 +; RV64ZBA-NEXT: sub a2, a0, a1 +; RV64ZBA-NEXT: slt a0, a2, a0 +; RV64ZBA-NEXT: slti a1, a1, 1 +; RV64ZBA-NEXT: xori a1, a1, 1 +; RV64ZBA-NEXT: xor a0, a1, a0 ; RV64ZBA-NEXT: xori a0, a0, 1 ; RV64ZBA-NEXT: ret entry: @@ -3101,10 +3113,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) { ; RV32-LABEL: ssubo.br.i32: ; RV32: # %bb.0: # %entry -; RV32-NEXT: sgtz a2, a1 -; RV32-NEXT: sub a1, a0, a1 -; RV32-NEXT: slt a0, a1, a0 -; RV32-NEXT: beq a2, a0, .LBB54_2 +; RV32-NEXT: sub a2, a0, a1 +; RV32-NEXT: slt a0, a2, a0 +; RV32-NEXT: slti a1, a1, 1 +; RV32-NEXT: xori a1, a1, 1 +; RV32-NEXT: beq a1, a0, .LBB54_2 ; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret @@ -3128,10 +3141,11 @@ ; ; RV32ZBA-LABEL: ssubo.br.i32: ; RV32ZBA: # %bb.0: # %entry -; RV32ZBA-NEXT: sgtz a2, a1 -; RV32ZBA-NEXT: sub a1, a0, a1 -; RV32ZBA-NEXT: slt a0, a1, a0 -; RV32ZBA-NEXT: beq a2, a0, .LBB54_2 +; RV32ZBA-NEXT: sub a2, a0, a1 +; RV32ZBA-NEXT: slt a0, a2, a0 +; RV32ZBA-NEXT: slti a1, a1, 1 +; RV32ZBA-NEXT: xori a1, a1, 1 +; RV32ZBA-NEXT: beq a1, a0, .LBB54_2 ; RV32ZBA-NEXT: # %bb.1: # %overflow ; RV32ZBA-NEXT: li a0, 0 ; RV32ZBA-NEXT: ret @@ -3184,10 +3198,11 @@ ; ; RV64-LABEL: ssubo.br.i64: ; RV64: # %bb.0: # %entry -; RV64-NEXT: sgtz a2, a1 -; RV64-NEXT: sub a1, a0, a1 -; RV64-NEXT: slt a0, a1, a0 -; RV64-NEXT: beq a2, a0, .LBB55_2 +; RV64-NEXT: sub a2, a0, a1 +; RV64-NEXT: slt a0, a2, a0 +; RV64-NEXT: slti a1, a1, 1 +; RV64-NEXT: xori a1, a1, 1 +; RV64-NEXT: beq a1, a0, .LBB55_2 ; RV64-NEXT: # %bb.1: # %overflow ; RV64-NEXT: li a0, 0 ; RV64-NEXT: ret @@ -3213,10 +3228,11 @@ ; ; RV64ZBA-LABEL: ssubo.br.i64: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: sgtz a2, a1 -; RV64ZBA-NEXT: sub a1, a0, a1 -; RV64ZBA-NEXT: slt a0, a1, a0 -; RV64ZBA-NEXT: beq a2, a0, .LBB55_2 +; RV64ZBA-NEXT: sub a2, a0, a1 +; RV64ZBA-NEXT: slt a0, a2, a0 +; RV64ZBA-NEXT: slti a1, a1, 1 +; RV64ZBA-NEXT: xori a1, a1, 1 +; RV64ZBA-NEXT: beq a1, a0, .LBB55_2 ; RV64ZBA-NEXT: # %bb.1: # %overflow ; RV64ZBA-NEXT: li a0, 0 ; RV64ZBA-NEXT: ret