diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -17518,9 +17518,9 @@ return SDValue(); ISD::CondCode CC = cast(SetCC->getOperand(2))->get(); - auto InverseSetCC = DAG.getSetCC( - SDLoc(SetCC), SetCC.getValueType(), SetCC.getOperand(0), - SetCC.getOperand(1), ISD::getSetCCInverse(CC, SetCC.getValueType())); + auto InverseSetCC = + DAG.getSetCC(SDLoc(SetCC), SetCC.getValueType(), SetCC.getOperand(0), + SetCC.getOperand(1), ISD::getSetCCInverse(CC, NTy)); return DAG.getNode(ISD::VSELECT, SDLoc(N), NTy, {InverseSetCC, SelectB, SelectA}); diff --git a/llvm/test/CodeGen/AArch64/sve-select.ll b/llvm/test/CodeGen/AArch64/sve-select.ll --- a/llvm/test/CodeGen/AArch64/sve-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-select.ll @@ -547,7 +547,8 @@ ; CHECK-LABEL: select_f32_invert_fmul: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: not p0.b, p0/z, p1.b ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret %p = fcmp oeq %a, zeroinitializer @@ -560,7 +561,8 @@ ; CHECK-LABEL: select_f32_invert_fadd: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: not p0.b, p0/z, p1.b ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret %p = fcmp oeq %a, zeroinitializer @@ -573,7 +575,8 @@ ; CHECK-LABEL: select_f32_invert_fsub: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: not p0.b, p0/z, p1.b ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret %p = fcmp oeq %a, zeroinitializer