diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -679,6 +679,20 @@
   switch (MI.getOpcode()) {
   default:
     return false;
+  case RISCV::PseudoVSM_V_B1:
+  case RISCV::PseudoVSM_V_B2:
+  case RISCV::PseudoVSM_V_B4:
+  case RISCV::PseudoVSM_V_B8:
+  case RISCV::PseudoVSM_V_B16:
+  case RISCV::PseudoVSM_V_B32:
+  case RISCV::PseudoVSM_V_B64:
+  case RISCV::PseudoVLM_V_B1:
+  case RISCV::PseudoVLM_V_B2:
+  case RISCV::PseudoVLM_V_B4:
+  case RISCV::PseudoVLM_V_B8:
+  case RISCV::PseudoVLM_V_B16:
+  case RISCV::PseudoVLM_V_B32:
+  case RISCV::PseudoVLM_V_B64:
   case RISCV::PseudoVLE8_V_M1:
   case RISCV::PseudoVLE8_V_M1_MASK:
   case RISCV::PseudoVLE8_V_M2: