diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32)
 
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
 
 declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32)